TC7135 [MICROCHIP]
4-1/2 Digit A/D Converter; 4-1 / 2位A / D转换器
| 型号： | TC7135 |
| 厂家： | 
MICROCHIP |
| 描述： | 4-1/2 Digit A/D Converter |
| 文件： | 总22页 (文件大小：533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC7135
4-1/2 Digit A/D Converter
Features
General Description
• Low Rollover Error: ±1 Count Max
• Nonlinearity Error: ±1 Count Max
• Reading for 0V Input
The TC7135 4-1/2 digit A/D converter (ADC) offers
50ppm (1 part in 20,000) resolution with a maximum
nonlinearity error of 1 count. An auto zero cycle
reduces zero error to below 10µV and zero drift to
0.5µV/°C. Source impedance errors are minimized by
a 10pA maximum input current. Rollover error is limited
to ±1 count.
• True Polarity Indication at Zero for Null Detection
• Multiplexed BCD Data Output
• TTL-Compatible Outputs
• Differential Input
Microprocessor based measurement systems are sup-
ported by BUSY, STROBE and RUN/HOLD control sig-
nals. Remote data acquisition systems with data
transfer via UARTs are also possible. The additional
control pins and multiplexed BCD outputs make the
TC7135 the ideal converter for display or
microprocessor based measurement systems.
• Control Signals Permit Interface to UARTs and
Microprocessors
• Blinking Display Visually Indicates Overrange
Condition
• Low Input Current: 1pA
• Low Zero Reading Drift: 2µV/°C
• Auto-Ranging Supported with Overrange and
Underrange Signals
Functional Block Diagram
–5V
TC7135
SET V
= 1V
• Available in PDIP and Surface-Mount Packages
REF
IN
V
1
2
3
4
REF
V-
28
Applications
UNDERRANGE
OVERRANGE
100kΩ
REF IN
27
26
25
24
23
22
21
20
19
• Precision Analog Signal Processor
• Precision Sensor Interface
ANALOG
STROBE
COMMON
Analog GND
0.47µF
RUN/HOLD
INT OUT
• High Accuracy DC Measurements
1µF
5
6
DIGTAL GND
POLARITY
CLOCK IN
BUSY
AZ IN
Device Selection Table
BUFF OUT
100kΩ
7
8
9
Clock
Input
C
C
-
REF
REF
100
Signal
Input
Part Number
Package
Temperature Range
1µF
kΩ
120kHz
+
TC7135CLI
TC7135CPI
TC7135CBU
28-PinPLCC
28-Pin PDIP
64-PinPQFP
0°C to +70°C
0°C to +70°C
0°C to +70°C
-INPUT
(LSD) D1
D2
0.1µF
10
11
12
13
14
+INPUT
V+
18
D3
+
5V
17
16
15
D5 (MSD)
D4
B1 (LSB)
B2
(MSB) B8
B4
2002 Microchip Technology Inc.
DS21460B-page 1
TC7135
Package Types
28-Pin PDIP
28-Pin PDIP
UNDERRANGE
28
V-
1
2
27 OVERRANGE
REF IN
ANALOG
COM
INT OUT
26
25
24
23
22
21
20
19
18
17
16
15
STROBE
RUN/HOLD
DIGTAL GND
POLARITY
CLOCK IN
BUSY
3
4
3
2
1 28 27 26
4
AZ IN
BUFF OUT
REF CAP–
REF CAP+
–INPUT
5
6
7
8
9
25
RUN/HOLD
5
AZ IN
24 DIGTAL GND
BUFF OUT
6
23
22
21
20
19
POLARITY
CLOCK IN
BUSY
C
-
REF
7
TC7135
TC7135
C
REF
+
8
9
D1 (LSD)
D2
– INPUT
+INPUT 10
11
D1 (LSD)
D2
10
11
12
13
14
+INPUT
V+
D3
V+
(MSD) D5
(LSB) B1
B2
12 13 14 15 16 17 18
D4
B8 (MSB)
B4
64-Pin PQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
l
1
2
48
47
46
45
NC
NC
NC
D3
NC
NC
NC
NC
NC
NC
3
4
5
44 D4
6
43
42
41
40
39
38
37
36
35
34
33
B8
B4
B2
NC
7
OVERRANGE
TC7135
8
UNDERRANGE
9
NC
10
11
12
13
14
15
16
V-
B1
D5
NC
NC
NC
NC
NC
REF IN
ANALOG COM
NC
NC
NC
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTE: NC = No internal connection.
DS21460B-page 2
2002 Microchip Technology Inc.
TC7135
*Stresses above those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at
these or any other conditions above those indicated in the
operation sections of the specifications is not implied. Expo-
sure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
Positive Supply Voltage..........................................+6V
Negative Supply Voltage....................................... - 9V
Analog Input Voltage (Pin 9 or 10) .... V+ to V- (Note 2)
Reference Input Voltage (Pin 2)...................... V+ to V-
Clock Input Voltage ........................................ 0V to V+
Operating Temperature Range ...............0°C to +70°C
Storage Temperature Range............– 65°C to +150°C
Package Power Dissipation; (T ≤ 70°C)
A
28-Pin PDIP ..................................... 1.14Ω
28-Pin PLCC .................................... 1.00Ω
64-Pin PQFP .....................................1.14Ω
TC7135 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: TA = +25°C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified
(see Functional Block Diagram).
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Analog
Display Reading with Zero Volt Input
Zero Reading Temperature Coefficient
-0.0000 ±0.0000 +0.0000
Display Reading Note 2 and Note 3
TCZ
—
—
0.5
—
2
5
µV/°C
VIN = 0V, (Note 4)
TCFS Full Scale Temperature Coefficient
ppm/°C
VIN = 2V,
(Note 4 and Note 5)
NL
Nonlinearity Error
—
—
0.5
1
Count
LSB
Note 6
Note 6
DNL
Differential Linearity Error
0.01
—
Display Reading in Ratiometric Operation +0.9996 +0.9999 +1.0000
Display Reading VIN = VREF, (Note 2)
±FSE ± Full Scale Symmetry Error
(Rollover Error)
—
0.5
1
Count
-VIN = +VIN, (Note 7)
IIN
eN
Input Leakage Current
Noise
—
—
1
10
—
pA
Note 3
15
µVP-P
Peak-to-Peak Value not
Exceeded 95% of Time
Digital
IIL
Input Low Current
Input High Current
Output Low Voltage
—
—
10
0.08
0.2
100
10
0.4
5
µA
µA
V
VIN = 0V
IIH
VIN = +5V
IOL = 1.6mA
VOL
VOH
—
Output High Voltage;
B1, B2, B4, B8, D1 –D5
Busy, Polarity, Overrange,
Underrange, Strobe
2.4
4.9
4.4
V
IOH = 1mA
4.99
5
V
IOH = 10µA
FCLK
Clock Frequency
0
200
1200
kHz
Note 8
Note 1: Limit input current to under 100µA if input voltages exceed supply voltage.
2: Full scale voltage = 2V.
3: VIN = 0V.
4: 30°C ≤ TA ≤ +70°C
5: .External reference temperature coefficient less than 0.01ppm/°C.
6: -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line.
7: IVIN| = 1.9959.
8: Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased
errors result at higher operating frequencies.
2002 Microchip Technology Inc.
DS21460B-page 3
TC7135
TC7135 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: TA = +25°C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified
(see Functional Block Diagram).
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Power Supply
V+
V-
I+
Positive Supply Voltage
4
5
-5
6
-8
3
V
V
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
-3
—
—
—
1
mA
mA
mW
FCLK = 0Hz
I-
0.7
8.5
3
FCLK = 0Hz
FCLK = 0Hz
PD
30
Note 1: Limit input current to under 100µA if input voltages exceed supply voltage.
2: Full scale voltage = 2V.
3: VIN = 0V.
4: 30°C ≤ TA ≤ +70°C
5: .External reference temperature coefficient less than 0.01ppm/°C.
6: -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line.
7: IVIN| = 1.9959.
8: Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased
errors result at higher operating frequencies.
DS21460B-page 4
2002 Microchip Technology Inc.
TC7135
2.0
PIN DESCRIPTIONS
The description of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
28-Pin PDIP
Symbol
Description
1
2
V-
Negative power supply input.
External reference input.
REF IN
3
ANALOG COMMON Reference point for REF IN.
4
INT OUT
AZ IN
Integrator output. Integrator capacitor connection.
Auto zero inpt. Auto-zero capacitor connection.
Analog input buffer output. Integrator resistor connection.
Reference capacitor input. Reference capacitor negative connection.
Reference capacitor input. Reference capacitor positive connection.
Analog input. Analog input negative connection.
Analog input. Analog input positive connection.
Positive power supply input.
5
6
BUFF OUT
7
CREF
CREF
-
8
+
9
-INPUT
+INPUT
V+
10
11
12
13
14
15
16
17
18
19
20
21
D5
Digit drive output. Most Significant Digit (MSD)
Binary Coded Decimal (BCD) output. Least Significant Bit (LSB)
BCD output.
B1
B2
B4
BCD output.
B8
BCD output. Most Significant Bit (MSB)
Digit drive output.
D4
D3
Digit drive output.
D2
Digit drive output.
D1
Digit drive output. Least Significant Digit (LSD)
BUSY
Busy output. At the beginning of the signal-integration phase, BUSY goes High and
remains High until the first clock pulse after the integrator zero crossing.
22
23
CLOCK IN
POLARITY
Clock input. Conversion clock connection.
Polarity output. A positive input is indicated by a logic High output. The polarity output is
valid at the beginning of the reference integrate phase and remains valid until determined
during the next conversion.
24
25
DGND
Digital logic reference input.
RUN/HOLD
Run / Hold input. When at a logic High, conversions are performed continuously. A logic
Low holds the current data as long as the Low condition exists.
26
27
STROBE
Strobe output. The STROBE output pulses low in the center of the digit drive outputs.
OVERRANGE
Over range output. A logic High indicates that the analog input exceeds the full scale input
range.
28
UNDERRANGE
Under range output. A logic High indicates that the analog input is less than 9% of the full
scale input range.
2002 Microchip Technology Inc.
DS21460B-page 5
TC7135
ent benefit is noise immunity. Noise spikes are inte-
grated, or averaged, to zero during the integration
periods.
3.0
DETAILED DESCRIPTION
(All Pin Designations Refer to 28-Pin DIP)
Integrating ADCs are immune to the large conversion
errors that plague successive approximation convert-
ers in high-noise environments (see Figure 3-1).
3.1
Dual Slope Conversion Principles
The TC7135 is a dual slope, integrating A/D converter.
An understanding of the dual slope conversion tech-
nique will aid in following the detailed TC7135
operational theory.
FIGURE 3-1:
BASIC DUAL SLOPE
CONVERTER
The conventional dual slope converter measurement
cycle has two distinct phases:
Analog Input
Signal
Integrator
-
Comparator
1. Input signal integration
-
+
2. Reference voltage integration (de-integration)
+
The input signal being converted is integrated for a
fixed time period. Time is measured by counting clock
pulses. An opposite polarity constant reference voltage
is then integrated until the integrator output voltage
returns to zero. The reference integration time is
directly proportional to the input signal.
Switch
Drive
Clock
Phase
REF
Control
Logic
Control
Voltage
Polarity Control
In a simple dual slope converter, a complete conver-
sion requires the integrator output to "ramp-up" and
"ramp-down."
Counter
Display
V
IN
V
IN
≈ V
REF
A simple mathematical equation relates the input sig-
nal, reference voltage, and integration time:
≈ 1/2 V
REF
Fixed Variable
Signal Reference
Integrate Integrate
Time Time
EQUATION 3-1:
T
V
T
1
INT
REF DEINT
R
V
(T)DT =
IN
R
C
C
0
INT INT
INT INT
3.2
TC7135 Operational Theory
where:
The TC7135 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase dual-slope measurement cycle. Reduced sys-
tem errors, fewer calibration steps, and a shorter over-
range recovery time result.
V
= Reference voltage
REF
T
T
= Signal integration time (fixed)
INT
= Reference voltage integration time
(variable).
DEINT
The TC7135 measurement cycle contains four phases:
For a constant V
:
1. System zero
IN
2. Analog input signal integration
3. Reference voltage integration
4. Integrator output zero
EQUATION 3-2:
V
T
REF DEINT
V
=
IN
T
INT
Internal analog gate status for each phase is shown in
Figure 3-1.
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An inher-
TABLE 3-1:
INTERNAL ANALOG GATE STATUS
Conversion Cycle Phase
SWI
SWRI
+
SWRI
-
SWZ
SWR
SW1
SWIZ
Reference Figures
System Zero
Closed
Closed
Closed
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Input Signal Integration
Reference Voltage Integration
Integrator Output Zero
Closed
Closed*
Closed
Closed
Closed
*Note:
Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
DS21460B-page 6
2002 Microchip Technology Inc.
TC7135
3.2.1
SYSTEM ZERO
3.2.3
REFERENCE VOLTAGE
INTEGRATION
During this phase, errors due to buffer, integrator, and
comparator offset voltages are compensated for by
charging C (auto zero capacitor) with a compensat-
ing error voltage. With a zero input voltage the integra-
tor output will remain at zero.
The previously-charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero (see Figure 3-4). The digital
reading displayed is:
AZ
The external input signal is disconnected from the inter-
EQUATION 3-3:
nal circuitry by opening the two SW switches. The
I
internal input points connect to ANALOG COMMON.
The reference capacitor charges to the reference volt-
[Differential Input]
Reading = 10,000
V
REF
age potential through SW . A feedback loop, closed
R
around the integrator and comparator, charges the C
AZ
FIGURE 3-4:
REFERENCE VOLTAGE
INTEGRATION CYCLE
capacitor with a voltage to compensate for buffer ampli-
fier, integrator, and comparator offset voltages (see
Figure 3-2).
Analog
SW
I
Input Buffer
C
R
INT
INT
+
+IN
FIGURE 3-2:
SYSTEM ZERO PHASE
-
SW - SW
RI
+
RI
C
Analog
SZ
Input Buffer
SW
I
SW
SW
Z
IZ
C
R
INT
INT
+
+IN
-
Comparator
C
SW
REF
R
+
REF
IN
-
+
SW - SW
RI
+
RI
-
C
To Digital
Section
SZ
Integrator
SW
SW
Z
Z
SW
SW
Z
IZ
-
SW + SW
RI RI
-
C
REF
Comparator
SW
R
+
Analog
Common
REF
IN
+
-
To Digital
Section
SW
Integrator
1
SW
SW
Z
SW
Z
I
Switch Open
–
IN
Switch Closed
SW + SW
RI RI
-
Analog
Common
SW
1
SW
3.2.4
INTEGRATOR OUTPUT ZERO
I
Switch Open
Switch Closed
–
IN
This phase ensures the integrator output is at 0V when
the system zero phase is entered. It also ensures that
the true system offset voltages are compensated for.
This phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles (see Figure 3-5).
3.2.2
ANALOG INPUT SIGNAL
INTEGRATION
The TC7135 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
must be within the device Common mode range; - 1V
from either supply rail, typically. The input signal polar-
ity is determined at the end of this phase.
FIGURE 3-5:
INTEGRATOR OUTPUT
ZERO PHASE
See Figure 2-3
Analog
Input Buffer
+
SW
I
R
C
INT
INT
+
IN
FIGURE 3-3:
INPUT SIGNAL
INTEGRATION PHASE
-
SW - SW
RI RI
+
C
SZ
Analog
SW
Z
SW
IZ
Input Buffer
SW
I
-
C
SW
SW
REF
Comparator
R
C
R
INT
+
-
INT
+
+IN
REF
IN
+
-
To Digital
Section
SW - SW
RI
+
RI
Integrator
C
SZ
SW
Z
Z
SW + SW
RI RI
-
SW
SW
IZ
Z
-
C
REF
Comparator
Analog
SW
R
+
Common
REF
IN
+
SW
1
-
SW
To
I
Switch Open
Integrator
Digital
Section
–
IN
SW
SW
Z
Switch Closed
Z
SW + SW
RI RI
-
Analog
Common
SW
1
SW
Switch Open
I
–
IN
Switch Closed
.
2002 Microchip Technology Inc.
DS21460B-page 7
TC7135
FIGURE 4-1:
USING AN EXTERNAL
REFERENCE
4.0
ANALOG SECTION
FUNCTIONAL DESCRIPTION
V+
4.1
Differential Inputs
The TC7135 operates with differential voltages
(+INPUT, pin 10 and -INPUT, pin 9) within the input
amplifier Common mode range, which extends from 1V
below the positive supply to 1V above the negative
supply. Within this Common mode voltage range, an
86dB Common mode rejection ratio is typical.
V+
10k
MCP1525
2.5 V
TC7135
REF
REF
IN
10k
1µF
ANALOG
COMMON
The integrator output also follows the Common mode
voltage and must not be allowed to saturate. A worst-
case condition exists, for example, when a large posi-
tive Common mode voltage with a near full scale neg-
ative differential input voltage is applied. The negative
input signal drives the integrator positive when most of
its swing has been used up by the positive Common
mode voltage. For these critical applications, the
integrator swing can be reduced to less than the
recommended 4V full scale swing, with some loss of
accuracy. The integrator output can swing within 0.3V
of either supply without loss of linearity.
Analog Ground
4.2
Analog Common Input
ANALOG COMMON is used as the -INPUT return dur-
ing auto zero and de-integrate. If -INPUT is different
from ANALOG COMMON, a Common mode voltage
exists in the system. However, this signal is rejected by
the excellent CMRR of the converter. In most applica-
tions, –INPUT will be set at a fixed, known voltage
(power supply common, for instance). In this applica-
tion, ANALOG COMMON should be tied to the same
point, thus removing the Common mode voltage from
the converter. The reference voltage is referenced to
ANALOG COMMON.
4.3
Reference Voltage Input
The reference voltage input (REF IN) must be a posi-
tive voltage with respect to ANALOG COMMON. A
reference voltage circuit is shown in Figure 4-1.
DS21460B-page 8
2002 Microchip Technology Inc.
TC7135
5.0
DIGITAL SECTION
FUNCTIONAL DESCRIPTION
The major digital subsystems within the TC7135 are
illustrated in Figure 5-1, with timing relationships
shown in Figure 5-2. The multiplexed BCD output data
can be displayed on LCD or LED displays. The digital
section is best described through a discussion of the
control signals and data outputs.
FIGURE 5-1:
DIGITAL SECTION FUNCTIONAL DIAGRAM
Polarity
D5
MSB
D4
Digit
D3
Drive
D2
D1
13 B1
14 B2
15 B4
16 B8
Signal
LSB
Data
Multiplexer
Output
From
Analog
Section
Latch
Latch
Latch
Latch
Latch
Polarity
FF
Counters
Zero
Cross
Detect
Control Logic
27
24
22
Clock
25
RUN/
28
26
21
DGND
Overrange Underrange STROBE
Busy
In
HOLD
2002 Microchip Technology Inc.
DS21460B-page 9
TC7135
FIGURE 5-2:
TIMING DIAGRAMS FOR
OUTPUTS
5.2
STROBE Output
During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur
in the center of the digit drive signals (D , D , D , D )
Integrator
Output
1
2
3
5
Signal
(see Figure 5-3).
Integrate
10,000
Counts
(Fixed)
System
Zero
Reference
Integrate
D (MSD) goes high for 201 counts when the measure-
10,001
Counts
20,001
5
Counts (Max)
ment cycles end. In the center of the D pulse, 101
clock pulses after the end of the measurement cycle,
the first STROBE occurs for one half clock pulse. After
the D digit strobe, D goes high for 200 clock pulses.
The STROBE then goes low 100 clock pulses after D
5
Full Measurement Cycle
40,002 Counts
Busy
5
4
Overrange when
Applicable
4
goes high. This continues through the D digit drive
pulse.
1
Underrange when
Applicable
Expanded Scale Below
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will
not continue if the previous signal resulted in an
overrange condition.
Digit Scan
D5
D4
D3
D2
The active low STROBE pulses aid BCD data transfer
to UARTs, processors and external latches. For more
information, please refer to Application Note 784.
D1
100
First D5 of System Zero and
Reference Integrate One Count
Longer
*
Counts
STROBE
Reference
Signal
FIGURE 5-3:
STROBE SIGNAL LOW
FIVE TIMES PER
CONVERSION
Auto Zero
Integrate
Integrate
*
Digit Scan
D5
D4
D3
D2
D1
for Overrange
*
TC835
Outputs
Busy
End of Conversion
*
B1–B8
D3
D2
Data
D1 (LSD)
Data
D5
Data
D5 (MSD)
Data
D4
Data
Data
STROBE
5.1
RUN/HOLD Input
Note Absence of
STROBE
200
Counts
When left open, this pin assumes a logic "1" level. With
a RUN/HOLD = 1, the TC7135 performs conversions
continuously, with a new measurement cycle beginning
every 40,002 clock pulses.
201
Counts
200
Counts
D5
D4
D3
200
Counts
When RUN/HOLD changes to a logic "0," the measure-
ment cycle in progress will be completed, data held and
displayed, as long as the logic "0" condition exists.
200
Counts
A positive pulse (>300nsec) at RUN/HOLD initiates a
new measurement cycle. The measurement cycle in
progress when RUN/HOLD initially assumed the logic
"0" state must be completed before the positive pulse
200
Counts
D2
D1
200
Counts
can be recognized as
command.
a single conversion run
*Delay between Busy going Low and First STROBE pulse is
dependent on Analog Input.
The new measurement cycle begins with a 10,001-
count auto zero phase. At the end of this phase the
busy signal goes high.
DS21460B-page 10
2002 Microchip Technology Inc.
TC7135
5.3
BUSY Output
At the beginning of the signal integration phase, BUSY
goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to the
logic "0" state after the measurement cycle ends in an
overrange condition. The internal display latches are
loaded during the first clock pulse after BUSY and are
latched at the clock pulse end. The BUSY signal does
not go high at the beginning of the measurement cycle,
which starts with the auto zero cycle.
5.4
OVERRANGE Output
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVER-
RANGE output is set to a logic "1." The overrange
output register is set when BUSY goes low and is reset
at the beginning of the next reference integration
phase.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800
counts), the underrange register bit is set at the end of
BUSY. The bit is set low at the next signal integration
phase.
5.6
POLARITY Output
A positive input is registered by a logic "1" polarity sig-
nal. The polarity bit is valid at the beginning of refer-
ence integrate and remains valid until determined
during the next conversion.
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal polar-
ity determined correctly. This is useful in null
applications.
5.7
Digit Drive Outputs
Digit drive signals are positive-going signals. The scan
sequence is D5 to D1. All positive pulses are 200 clock
pulses wide, with the exception D5, which is 201 clock
pulses wide.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange condition,
all digit drives are held low from the final STROBE
pulse until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
provides a blinking visual display indication.
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B , B , B , and B
1
8
4
2
are positive-true logic signals. The data bits become
active at the same time as the digit drive signals. In an
overrange condition, all data bits are at a logic "0" state.
2002 Microchip Technology Inc.
DS21460B-page 11
TC7135
The dielectric absorption of the reference and auto zero
capacitors are only important at power-on or when the
circuit is recovering from an overload. Smaller or
cheaper capacitors can be used if accurate readings
are not required for the first few seconds of recovery.
6.0
6.1
TYPICAL APPLICATIONS
Component Value Selection
6.1.1
INTEGRATING RESISTOR
The integrating resistor R
scale input voltage and the output current of the buffer
used to charge the integrator capacitor, C . Both the
buffer amplifier and the integrator have a class A output
stage, with 100µA of quiescent current. A 20µA drive
current gives negligible linearity errors. Values of 5µA
to 40µA give good results. The exact value of an
integrating resistor for
calculated.
is determined by the full
6.1.4
REFERENCE VOLTAGE
INT
The analog input required to generate a full scale out-
put is V = 2 V
INT
.
REF
IN
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this
reason, it is recommended that a high-quality reference
be used where high-accuracy absolute measurements
are being made.
a 20µA current is easily
6.2
Conversion Timing
EQUATION 6-1:
Full scale voltage
R
=
6.2.1
LINE FREQUENCY REJECTION
INT
20µA
A signal integration period at a multiple of the 60Hz line
frequency will maximize 60Hz "line noise" rejection. A
100kHz clock frequency will reject 50Hz, 60Hz and
400Hz noise. This corresponds to five readings per
second (see Table 6-1 and Table 6-2).
6.1.2
INTEGRATING CAPACITOR (C
)
INT
The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing that
ensures the tolerance buildup will not saturate the inte-
grator swing (approximately 0.3V from either supply).
For ±5V supplies and ANALOG COMMON tied to sup-
ply ground, a ±3.5V to ±4V full scale integrator swing is
adequate. A 0.10µF to 0.47µF is recommended. In
TABLE 6-1:
CONVERSION RATE VS.
CLOCK FREQUENCY
Oscillator Frequency
(kHz)
Conversion Rate
(Conv./Sec.)
general, the value of C
is given by:
INT
100
120
200
300
400
800
1200
2.5
3
EQUATION 6-2:
[10,000 x clock period] x I
5
INT
C
=
INT
7.5
10
20
30
Integrator output voltage swing
(10,000) (clock period) (20µA)
=
Integrator output voltage swing
A very important characteristic of the integrating capac-
itor C is that it has low dielectric absorption to pre-
INT
vent rollover or ratiometric errors. A good test for
dielectric absorption is to use the capacitor with the
input tied to the reference. This ratiometric condition
should read half scale 0.9999, with any deviation
probably due to dielectric absorption. Polypropylene
capacitors give undetectable errors at reasonable cost.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
6.1.3
AUTO ZERO AND REFERENCE
CAPACITORS
The size of the auto zero capacitor has some influence
on the noise of the system. A large capacitor reduces
the noise. The reference capacitor should be large
enough such that stray capacitance to ground from its
nodes is negligible.
DS21460B-page 12
2002 Microchip Technology Inc.
TC7135
ator delay can be compensated and the maximum
clock frequency extended by approximately a factor of
3. At higher frequencies, ringing and second-order
breaks will cause significant nonlinearities in the first
few counts of the instrument.
TABLE 6-2:
LINE FREQUENCY
REJECTION VS. CLOCK
FREQUENCY
Oscillator Frequency
(kHz)
Line Frequency Rejection
(Hz)
The minimum clock frequency is established by leak-
age on the auto zero and reference capacitors. With
most devices, measurement cycles as long as 10 sec-
onds give no measurable leakage error.
300
200
60
150
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators
are shown in Section 6.0, Typical Applications. The
multiplexed output means that if the display takes sig-
nificant current from the logic supply, the clock should
have good PSRR.
120
100
40
33-1/3
250
50
166-2/3
125
6.4
Zero Crossing Flip Flop
100
The flip flop interrogates the data once every clock
pulse after the transients of the previous clock pulse and
half clock pulse have died down. False zero crossings
caused by clock pulses are not recognized. Of course,
the flip flop delays the true zero crossing by up to one
count in every instance. If a correction were not made,
the display would always be one count too high. There-
fore, the counter is disabled for one clock pulse at the
beginning of the reference integrate (de-integrate)
phase. This one-count delay compensates for the delay
of the zero crossing flip flop and allows the correct num-
ber to be latched into the display. Similarly, a one-count
delay at the beginning of auto zero gives an overload
display of 0000 instead of 0001. No delay occurs during
signal integrate so that true ratiometric readings result.
100
50, 60,400
The conversion rate is easily calculated:
EQUATION 6-3:
Clock Frequency (Hz)
Reading 1/sec =
4000
6.3
High Speed Operation
The maximum conversion rate of most dual slope A/D
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the
integrator ramp with a 3µsec delay, at a clock fre-
quency of 160 kHz (6µsec period), Half of the first ref-
erence integrate clock period is lost in delay. This
means that the meter reading will change from 0 to 1
with a 50µV input, 1 to 2 with 150µV, 2 to 3 at 250µV,
etc. This transition at midpoint is considered desirable
by most users. However, if the clock frequency is
increased appreciably above 200kHz, the instrument
will flash "1" on noise peaks, even when the input is
shorted.
6.5
Generating a Negative Supply
A negative voltage can be generated from the positive
supply by using a TC7660 (see Figure 6-1).
FIGURE 6-1:
NEGATIVE SUPPLY
VOLTAGE GENERATOR
+5V
11
1
For many dedicated applications where the input signal
is always of one polarity, the delay of the comparator
need not be a limitation. Since the nonlinearity and
noise do not increase substantially with frequency, clock
rates of up to ~1MHz may be used. For a fixed clock fre-
quency, the extra count, or counts, caused by compara-
tor delay, will be a constant and can be subtracted out
digitally.
V+
8
TC7135
(-5V)
10µF
5
V–
TC7660
+
4
2
3
+
24
10µF
The clock frequency may be extended above 160kHz
without this error, however, by using a low value resis-
tor in series with the integrating capacitor. The effect of
the resistor is to introduce a small pedestal voltage on
to the integrator output at the beginning of the refer-
ence integrate phase. By careful selection of the ratio
between this resistor and the integrating resistor (a few
tens of ohms in the recommended circuit), the compar-
2002 Microchip Technology Inc.
DS21460B-page 13
TC7135
FIGURE 6-2:
4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON ANODE LED DISPLAY
+5V
20 19 18 17 12
D1 D2 D3 D4 D5
INT OUT
4
5
0.33µF
1µF
AZ IN
4.7kΩ
1µF
23
7
POL
6
BUFF
b
c
7
7
7
7
OUT
C
-
100kΩ
REF
22
10
TC7135
F
IN
200kHz
X7
8
C
+
REF
Blank MSD On Zero
100kΩ
+
+INPUT
9–15
5
Analog
16
15
14
13
6
2
1
7
1µF
Input
B8
D
C
B
A
9
3
RBI
DM7447A
–INPUT
–
B4
B2
B1
16
+5V
ANALOG
COMMON
REF
V–
IN
V+
1
2
11
V+
–5V
100kΩ
MCP1525
1µF
FIGURE 6-3:
RC OSCILLATOR CIRCUIT
FIGURE 6-4:
COMPARATOR CLOCK
CIRCUITS
R
2
R
1
+5V
C
F
O
16kΩ
1kΩ
56kΩ
Gates are 74C04
2
3
+
8
V
OUT
0.22µF
7
1
R R
1
2
LM311
, R =
1. F
=
P
O
-
R + R
1
2C(0.41 R + 0.7 R )
1
2
P
1
30kΩ
390pF
4
16kΩ
a. If R1 = R2 = R1, F≅ 0.55/RC
b. If R2 >> R1, F ≅ 0.45/R1C
c. If R2 << R1, F ≅ 0.72/R1C
+5V
R2
100kΩ
R4
2kΩ
2. Examples:
a. F = 120kHz, C = 420pF
R1 = R2 ≈ 10.9 kΩ
C2
10pF
2
3
+
6
b. F = 120kHz, C = 420pF, R2 = 50kΩ
R1 = 8.93kΩ
7
R2
100kΩ
V
LM311
OUT
-
4
R3
50kΩ
c. F = 120 kHz, C = 220 pF, R2 = 5kΩ
1
R = 27.3kΩ
C1
0.1µF
1
DS21460B-page 14
2002 Microchip Technology Inc.
TC7135
FIGURE 6-5:
4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON CATHODE LED DISPLAY
+5V
+5V
SET V
= 1V
REF
–5V
28
27
26
1
2
3
V-
UR
OR
TC7135
MCP1525
100
REF IN
kΩ
150Ω
1µF
ANALOG
GND
STROBE
47
kΩ
10
11
9
8
7
6
5
4
3
2
1
Analog
GND
150Ω
25
24
23
22
21
20
4
5
6
7
8
9
INT
OUT
RUN/HOLD
DGND
POLARITY
CLK IN
BUSY
1µF
0.33µF
12
13
14
15
AZ IN
BUFF
OUT
MC14513
100 kΩ
1µF
C
+
REF
REF
100
kΩ
+
SIG
C
-
+5V
16
17
(LSD) D1
D2
–INPUT
0.1
µF
10
11
12
19
18
17
+INPUT
IN
–
18
+5V
D3
V+
D4
D5 (MSD)
13
14
16
15
(MSB) B8
B4
B1 (LSB)
B2
F
OSC
= 200kHz
2002 Microchip Technology Inc.
DS21460B-page 15
TC7135
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time.
7.2
Taping Forms
Component Taping Orientation for 28-Pin PLCC Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
28-Pin PLCC
24 mm
16 mm
750
13 in
Component Taping Orientation for 64-Pin PQFP Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
64-Pin PQFP
32 mm
24 mm
250
13 in
NOTE: Drawing does not represent total number of pins.
DS21460B-page 16
2002 Microchip Technology Inc.
TC7135
7.3
Package Dimensions
28-Pin PDIP (Wide)
PIN 1
.555 (14.10)
.530 (13.46)
1.465 (37.21)
1.435 (36.45)
.610 (15.49)
.590 (14.99)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51)
.015 (0.38)
.008 (0.20)
3˚MIN.
.150 (3.81)
.115 (2.92)
.700 (17.78)
.610 (15.50)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.022 (0.56)
.015 (0.38)
Dimensions: inches (mm)
28-Pin PLCC
PIN 1
.021 (0.53)
.013 (0.33)
.050 (1.27) TYP.
.495 (12.58)
.485 (12.32)
.430 (10.92)
.390 (9.91)
.456 (11.58)
.450 (11.43)
.032 (0.81)
.026 (0.66)
.456 (11.58)
.450 (11.43)
.020 (0.51) MIN.
.120 (3.05)
.090 (2.29)
.495 (12.58)
.485 (12.32)
.180 (4.57)
.165 (4.19)
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21460B-page 17
TC7135
7.3
Packaging Dimensions (Continued)
64-Pin PQFP
7˚ MAX.
.009 (0.23)
.005 (0.13)
.041 (1.03)
.031 (0.78)
PIN 1
.018 (0.45)
.012 (0.30)
.555 (14.10)
.547 (13.90)
.687 (17.45)
.667 (16.95)
.031 (0.80) TYP.
.010 (0.25) TYP.
.555 (14.10)
.547 (13.90)
.120 (3.05)
.100 (2.55)
.687 (17.45)
.667 (16.95)
.130 (3.30) MAX.
Dimensions: inches (mm)
DS21460B-page 18
2002 Microchip Technology Inc.
TC7135
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21460B-page 19
TC7135
NOTES:
DS21460B-page 20
2002 Microchip Technology Inc.
TC7135
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
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dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
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and Mountain View, California in March 2002.
The Company’s quality system processes and
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devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
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design and manufacture of development
systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21460B-page 21
WORLDWIDE SALES AND SERVICE
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04/20/02
DS21460B-page 22
2002 Microchip Technology Inc.
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