TC7135 [TELCOM]
4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER; 4-1 / 2位模拟数字转换器
| 型号： | TC7135 |
| 厂家： | 
TELCOM SEMICONDUCTOR, INC |
| 描述： | 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总13页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3
TC7135
4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
FEATURES
GENERAL DESCRIPTION
■ Low Roll-Over Error ......................... ±1 Count Max
■ Guaranteed Nonlinearity Error ........ ±1 Count Max
■ Guaranteed Zero Reading for 0V Input
■ True Polarity Indication at Zero for Null Detection
■ Multiplexed BCD Data Output
■ TTL-Compatible Outputs
■ Differential Input
■ Control Signals Permit Interface to UARTs and
µProcessors
■ Auto-Ranging Supported With Overrange and
Underrange Signals
■ Blinking Display Visually Indicates Overrange
Condition
■ Low Input Current............................................. 1 pA
■ Low Zero Reading Drift ............................... 2 µV/°C
■ Interfaces to TC7211A (LCD) and TC7212A (LED)
Display Drivers
The TC7135 4-1/2 digit analog-to-digital converter (ADC)
offers 50 ppm (1 part in 20,000) resolution with a maximum
nonlinearity error of 1 count. An auto-zero cycle reduces zero
error to below 10 µV and zero drift to 0.5 µV/°C. Source
impedance errors are minimized by a 10 pA maximum input
current. Roll-over error is limited to ±1 count.
By combining the TC7135 with a TC7211A (LCD) or
TC7212A (LED) driver, a 4-1/2 digit display DVM or DPM can
be constructed. Overrange and underrange signals support
automatic range switching and special display blanking/flash-
ing applications.
Microprocessor-based measurement systems are sup-
ported by BUSY, STROBE, and RUN/HOLD control signals.
Remote data acquisition systems with data transfer via UARTs
are also possible. The additional control pins and multiplexed
BCD outputs make the TC7135 the ideal converter for dis-
play or microprocessor-based measurement systems.
■ Available in DIP and Surface-Mount Packages
ORDERING INFORMATION
Temperature
Part No.
Package
Range
TC7135CBU
64-Pin Plastic
Flat Package
28-Pin PLCC
0°C to +70°C
TC7135CLI
TC7135CPI
0°C to +70°C
0°C to +70°C
28-Pin Plastic DIP
TYPICAL 4-1/2 DIGIT DVM WITH LCD
4-1/2 DIGIT LCD
+5V
6.8 kΩ
SEGMENT
+5V
D
R
I
V
E
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
11615 1412 5 3 4
CD4054A
7 8 13 1110 9 2 6
–5V
V
UR
OR
0.1 µF
REF IN
100 kΩ
0.47 µF
1 µF
3
TC04
ANALOG
COMMON
INT OUT
BACKPLANE
+5V
STROBE
RUN/HOLD
DGND
POL
4
5
ANALOG
GROUND
AZ IN
120 Hz = 3 READING/SEC
CLOCK IN
1
+
6
BUFF OUT
5
V
7
BP
100 kΩ
–
CD4081
C
CLOCK
BUSY
D1
REF
1/4 CD4030
1 µF
31
8
+
REF
1
2
3
4
D
D
D
D
C
+5V
9
32
33
34
–INPUT
SEG
OUT
0.1
µF
10
11
12
13
14
INPUT
+INPUT
D2
+
+5V
V
D3
2,3,4
6–26
37–40
100 kΩ
D5
D4
TC7135
30
29
TC7211A
B1
B2
B3
B2
B1
B0
B8
15
36
B4
+5V
OSC
28
27
OPTIONAL
CAP
35
GND
TC7135-10 11/6/96
TELCOM SEMICONDUCTOR, INC.
3-113
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
ABSOLUTE MAXIMUM RATINGS* (Note 1)
Lead Temperature (Soldering, 10 sec) ................. +300°C
Package Power Dissipation (TA ≤ 70°C)
Positive Supply Voltage ............................................. +6V
Negative Supply Voltage .............................................–9V
Analog Input Voltage (Pin 9 or 10) ......... V+ to V– (Note 2)
Reference Input Voltage (Pin 2) ........................... V+ to V–
Clock Input Voltage ..............................................0V to V+
Operating Temperature Range .................... 0°C to +70°C
Storage Temperature Range ................. –65°C to +160°C
Plastic DIP ........................................................1.14W
PLCC ................................................................1.00W
Plastic Flat Package .........................................1.14W
*Static-sensitive device. Unused devices must be stored in conductive
material to protect them from static discharge and static fields. Stresses
above those listed under "Absolute Maximum Ratings" may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
ELECTRICAL CHARACTERISTICS: TA = +25°C, fCLOCK = 120 kHz, V+ = +5V, V– = –5V (Figure 1)
Symbol
Analog
Parameter
Test Conditions
Min
Typ
Max
Unit
Display Reading With
Zero Volt Input
Notes 2 and 3
–0.0000
±0.0000
0.5
+0.0000
Display
Reading
TCZ
Zero Reading Temperature
Coefficient
VIN = 0V
Note 4
—
—
2
5
µV/°C
TCFS
Full-Scale Temperature
Coefficient
VIN = 2V
Notes 4 and 5
—
ppm/°C
NL
Nonlinearity Error
Note 6
Note 6
—
—
0.5
0.01
1
—
Count
LSB
DNL
Differential Linearity Error
Display Reading in
Ratiometric Operation
VIN = VREF
Note 2
+0.9996
+0.9999
+1.0000
Display
Reading
±FSE
± Full-Scale Symmetry
Error (Roll-Over Error)
–VIN = +VIN
Note 7
—
0.5
1
Count
IIN
Input Leakage Current
Noise
Note 3
—
—
1
10
—
pA
VN
Peak-to-Peak Value Not
Exceeded 95% of Time
15
µVP-P
Digital
IIL
Input Low Current
Input High Current
Output Low Voltage
VIN = 0V
—
—
—
10
0.08
0.2
100
10
µA
µA
V
IIH
VIN = +5V
IOL = 1.6 mA
VOL
VOH
0.4
Output High Voltage
B1, B2, B4, B8, D1–D5
Busy, Polarity, Overrange,
Underrange, Strobe
IOH = 1 mA
IOH = 10 µA
2.4
4.9
4.4
4.99
5
5
V
V
fCLK
Clock Frequency
Note 8
0
120
1200
kHz
Power Supply
V+
V–
I+
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
4
5
6
–8
3
V
–3
—
—
—
–5
1
V
fCLK = 0 Hz
fCLK = 0 Hz
fCLK = 0 Hz
mA
mA
mW
I–
0.7
8.5
3
PD
30
5. External reference temperature coefficient less than 0.01 ppm/°C.
6. –2V ≤ VIN ≤ +2V. Error of reading from best fit straight line.
7. |VIN| = 1.9959.
NOTES: 1. Limit input current to under 100µA if input
voltages exceed supply voltage.
2. Full-scale voltage = 2V.
8. Specification related to clock frequency range over which the
TC7135 correctly performs its various functions. Increased errors
result at higher operating frequencies.
3. VIN = 0V.
4. 0°C ≤ TA ≤ +70°C.
3-114
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3
TC7135
PIN CONFIGURATIONS
–
UNDERRANGE
28
V
1
2
27 OVERRANGE
REF IN
ANALOG
COM
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
26
25
24
23
22
21
20
19
18
17
16
STROBE
RUN/HOLD
DIGTAL GND
POLARITY
CLOCK IN
BUSY
3
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
●
NC
NC
NC
INT OUT
4
NC
5
AZ IN
3
NC
BUFF OUT
–
6
4
NC
D3
D4
C
7
REF
TC7135CPI
(PDIP)
5
NC
NC
+
C
8
REF
6
B8
B4
B2
NC
–
9
D1 (LSD)
D2
INPUT
7
OVERRANGE
UNDERRANGE
NC
+
10
11
12
13
14
INPUT
8
+
D3
V
9
D4
(MSD) D5
(LSB) B1
B2
–
10
11
12
13
14
15
16
V
B1
D5
NC
NC
NC
NC
NC
TC7135CBU
(PFP)
(NOTES 1)
B8 (MSB)
B4
REF IN
15
ANALOG COM
NC
NC
NC
NC
4
3
2
1
28 27 26
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AZ IN
5
25
RUN/HOLD
BUFF OUT
6
7
8
9
24 DIGTAL GND
–
REF CAP
23
22
21
20
19
POLARITY
CLOCK IN
BUSY
+
REF CAP
TC7135CLI
(PLCC)
–
INPUT
+
INPUT 10
+
D1 (LSD)
D2
NOTES: 1. NC = No internal connection.
11
V
12 13 14 15 16 17 18
TELCOM SEMICONDUCTOR, INC.
3-115
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
–5V
ANALOG
SET V
= 1V
INPUT BUFFER
REF
IN
SW
I
C
R
INT
+
+
–
INT
1
2
3
4
IN
V
REF
–
V
28
UNDERRANGE
OVERRANGE
STROBE
–
+
SW
SW
RI
RI
100 kΩ
REF IN
27
26
25
24
23
22
21
20
19
C
SZ
ANALOG
COMMON
SW
SW
Z
IZ
–
+
C
COMPARATOR
SW
REF
R
ANALOG GND
+
REF
IN
RUN/HOLD
INT OUT
0.47
µF
1 µF
–
TO
5
6
DIGTAL GND
POLARITY
CLOCK IN
BUSY
DIGITAL
SECTION
INTEGRATOR
AZ IN
SW
SW
Z
Z
+
RI
–
BUFF OUT
SW
SW
RI
100 kΩ
100
kΩ
7
8
9
ANALOG
COM
–
CLOCK
INPUT
120 kHz
C
REF
SIGNAL
INPUT
1 µF
+
C
SW
REF
1
SW
I
SWITCH OPEN
–
INPUT
(LSD) D1
D2
–
IN
SWITCH CLOSED
0.1 µF
10
11
12
13
14
+
INPUT
+
TC7135
18
D3
+
5V
V
Figure 3B. System Zero Phase
17
16
15
D5 (MSD)
D4
(MSB) B8
B4
B1 (LSB)
B2
ANALOG
INPUT BUFFER
SW
SW
Figure 1. Test Circuit
I
C
R
INT
+
INT
+
–
IN
–
+
SW
SW
RI
+
RI
C
V
SZ
SW
SW
Z
IZ
–
+
C
COMPARATOR
REF
R
+
REF
IN
–
TO
DIGITAL
SECTION
INTEGRATOR
SW
SW
Z
Z
+
RI
–
SW
SW
RI
BUFFER
ANALOG
COM
LOGIC
INPUT
SW
1
SW
I
SWITCH OPEN
–
IN
SWITCH CLOSED
Figure 3C. Input Signal Integration Phase
Figure 2. Digital Logic Input
ANALOG
ANALOG
INPUT BUFFER
SW
I
INPUT BUFFER
SW
I
C
R
INT
+
C
+
–
IN
INT
R
INT
+
+
–
INT
IN
–
+
RI
SW
–
SW
+
RI
RI
SW
SW
RI
C
SZ
C
SZ
SW
SW
Z
IZ
SW
SW
Z
IZ
–
+
COMPARATOR
C
SW
–
+
REF
COMPARATOR
R
C
SW
+
REF
R
REF
IN
+
REF
IN
–
TO
–
TO
DIGITAL
SECTION
INTEGRATOR
DIGITAL
SECTION
INTEGRATOR
SW
SW
Z
Z
SW
SW
Z
Z
+
RI
–
SW
+
RI
SW
–
RI
SW
SW
RI
ANALOG
COM
ANALOG
COM
SW
1
SW
SW
1
I
SW
I
SWITCH OPEN
–
IN
–
IN
SWITCH CLOSED
Figure 3A. Internal Analog Switches
Figure 3D. Reference Voltage Integration Phase
3-116
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3
TC7135
For a constant VIN:
ANALOG
INPUT BUFFER
SW
I
tRI
C
R
Z
INT
+
VIN = VR
.
+
INT
IN
[t ]
SI
–
–
+
SW
SW
C
RI
RI
C
SZ
The dual-slope converter accuracy is unrelated to the
integratingresistorandcapacitorvalues, aslongastheyare
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
(See Figure 4.)
SW
IZ
SW
–
+
COMPARATOR
SW
REF
R
+
REF
IN
–
TO
DIGITAL
SECTION
INTEGRATOR
SW
SW
Z
Z
+
RI
–
SW
SW
RI
ANALOG
COM
SW
1
SW
I
SWITCH OPEN
–
IN
SWITCH CLOSED
TC7135 Operational Theory
Figure 3E. Integrator Output Zero Phase
The TC7135 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase dual-slope measurement cycle. Reduced system
errors, fewer calibration steps, and a shorter overrange
recovery time result.
GENERAL THEORY OF OPERATION
(All Pin Designations Refer to 28-Pin DIP)
The TC7135 measurement cycle contains four phases:
(1) System zero
Dual-Slope Conversion Principles
(2) Analog input signal integration
(3) Reference voltage integration
(4) Integrator output zero
The TC7135 is a dual-slope, integrating analog-to-
digital converter. An understanding of the dual-slope con-
version technique will aid in following detailed TC7135
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
Internal analog gate status for each phase is shown in
Table 1.
(1) Input signal integration
ANALOG
INPUT
(2) Reference voltage integration (deintegration)
INTEGRATOR
SIGNAL
–
COMPARATOR
The input signal being converted is integrated for a fixed
time period, measured by counting clock pulses. An oppo-
site polarity constant reference voltage is then integrated
until the integrator output voltage returns to zero. The
referenceintegrationtimeisdirectlyproportionaltotheinput
signal.
Inasimpledual-slopeconverter,acompleteconversion
requires the integrator output to "ramp-up" and "ramp-
down."
–
+
+
SWITCH
DRIVER
CLOCK
PHASE
CONTROL
REF
VOLTAGE
CONTROL
LOGIC
POLARITY CONTROL
Asimplemathematicalequationrelatestheinputsignal,
reference voltage, and integration time:
COUNTER
DISPLAY
tSI
1
VR tRI
RC
V
V
Ϸ V
Ϸ
VIN(t) dt =
,
IN
IN
FULL SCALE
1/2 V
∫
RC
FULL SCALE
0
where:
FIXED VARIABLE
SIGNAL REFERENCE
INTEGRATE INTEGRATE
TIME TIME
VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
Figure 4. Basic Dual-Slope Converter
TELCOM SEMICONDUCTOR, INC.
3-117
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
Table 1. Internal Analog Gate Status
Conversion
Internal Analog Gate Status
Reference
Schematic
Cycle Phase
SWI
SWR+
SWR–
SWZ
SWR
SW1
SWIZ
System Zero
Closed
Closed
Closed
3B
3C
Input Signal
Integration
Closed
Reference Voltage
Integration
Closed*
Closed
Closed
3D
3E
Integrator
Closed
Output Zero
*NOTE: Assumes a positive polarity input signal. SWR– would be closed for a negative input signal.
System Zero Phase
Analog Section Functional Description
During this phase, errors due to buffer, integrator, and
comparator offset voltages are compensated for by charg-
ing CAZ (auto-zero capacitor) with a compensating error
voltage. With zero input voltage, the integrator output re-
mains at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to analog common. The refer-
ence capacitor charges to the reference voltage potential
throughSWR. Afeedbackloop, closedaroundtheintegrator
and comparator, charges the CAZ with a voltage to compen-
sate for buffer amplifier, integrator, and comparator offset
voltages. (See Figure 3B.)
Differential Inputs
The TC7135 operates with differential voltages (+IN-
PUT, pin 10 and –INPUT, pin 9) within the input amplifier
common-mode range which extends from 1V below the
positive supply to 1V above the negative supply. Within this
common-mode voltage range, an 86 dB common-mode
rejection ratio is typical.
The integrator output also follows the common-mode
voltage and must not be allowed to saturate. A worst-case
condition exists, for example, when a large positive com-
mon-modevoltagewithanearfull-scalenegativedifferential
input voltage is applied. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common-mode voltage. For these critical
applications, the integrator swing can be reduced to less
than the recommended 4V full-scale swing, with some loss
of accuracy. The integrator output can swing within 0.3V of
either supply without loss of linearity.
Analog Input Signal Integration Phase
The TC7135 integrates the differential voltage between
the +INPUT and –INPUT. The differential voltage must be
within the device's common-mode range; –1V from either
supply rail, typically.
The input signal polarity is determined at the end of this
phase. (See Figure 3C.)
Analog Common
ANALOG COMMON (pin 3) is used as the –INPUT
return during the auto-zero and deintegrate phases. If
–INPUTisdifferentfromanalogcommon, acommon-mode
voltage exists in the system. This signal is rejected by the
excellent CMRR of the converter. In most applications,
– INPUT will be set at a fixed known voltage (power supply
common, for instance). In this application, analog common
shouldbetiedtothesamepoint,thusremovingthecommon-
mode voltage from the converter. The reference voltage is
referenced to analog common.
Reference Voltage Integration Phase
The previously-charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero. (See Figure 3D.) The digital reading
displayed is:
Differential Input
Reading = 10,000
.
[ ]
VREF
Integrator Output Zero Phase
Reference Voltage
This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the true
system offset voltages are compensated for. This phase
normally lasts 100 to 200 clock cycles. If an overrange
conditionexists, thephaseisextendedto6200clockcycles.
(See Figure 3E.)
The reference voltage input (REF IN, pin 2) must be a
positive voltage with respect to analog common. Two refer-
ence voltage circuits are shown in Figure 5.
3-118
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3
TC7135
Digital Section Functional Description
+
V
The major digital subsystems within the TC7135 are
illustrated in Figure 6, with timing relationships shown in
Figure7. ThemultiplexedBCDoutputdatacanbedisplayed
on an LCD with the TC7211A.
The digital section is best described through a discus-
sion of the control signals and data outputs.
+
V
TC05
REF
IN
2.5V
REF
TC7135
I
REF
ANALOG
COMMON
RUN/HOLD Input
When left open, the RUN/HOLD (R/H) input (pin 25)
assumes a logic "1" level. With R/H = 1, the TC7135
performs conversions continuously, with a new measure-
ment cycle beginning every 40,002 clock pulses.
When R/H changes to logic "0," the measurement cycle
in progress will be completed, and data held and displayed,
as long as the logic "0" condition exists.
A positive pulse (>300nsec) at R/H initiates a new
measurement cycle. The measurement cycle in progress
when R/H initially assumed logic "0" must be completed
before the positive pulse can be recognized as a single
conversion run command.
–
V
+
V
6.8 kΩ
+
V
TC04
1.25V REF
REF
IN
20
kΩ
TC7135
ANALOG
COMMON
The new measurement cycle begins with a 10,001-
count auto-zero phase. At the end of this phase, the busy
signal goes high.
ANALOG
GROUND
Figure 5. Using an External Reference Voltage
POLARITY
D5
MSB
D4
D3
D2
D1
LSB
13 B1
14 B2
DIGIT
DRIVE
SIGNAL
DATA
OUTPUT
MULTIPLEXER
15 B4
16 B8
FROM
ANALOG
SECTION
LATCH
LATCH
LATCH
LATCH
LATCH
POLARITY
FF
COUNTERS
ZERO
CROSS
DETECT
CONTROL LOGIC
27
24
22
25
28
26
21
BUSY
DIGITAL CLOCK
GND IN
RUN/
HOLD
OVER–
RANGE
UNDER–
RANGE
STROBE
Figure 6. Digital Section Functional Diagram
TELCOM SEMICONDUCTOR, INC.
3-119
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
TC7135
OUTPUTS
INTEGRATOR
OUTPUT
BUSY
END OF CONVERSION
SIGNAL
INTE
SYSTEM
ZERO
REFERENCE
INTEGRATE
20,001
*
10,000
B1–B8
COUNTS
(FIXED)
10,001
COUNTS
D3
D2
DATA
D1 (LSD)
DATA
D5
DATA
D5 (MSD)
DATA
D4
DATA
COUNTS (MAX)
DATA
FULL MEASUREMENT CYCLE
40,002 COUNTS
STROBE
NOTE ABSENCE
OF STROBE
200
COUNTS
BUSY
OVERRANGE
WHEN
201
COUNTS
200
COUNTS
APPLICABLE
D5
D4
D3
UNDERRANGE
WHEN
APPLICABLE
200
COUNTS
EXPANDED SCALE
BELOW
200
COUNTS
DIGIT SCAN
D5
D4
200
COUNTS
D2
D3
D2
D1
200
COUNTS
D1
100
COUNTS
FIRST D5 OF SYSTEM ZERO
AND REFERENCE INTEGRATE
ONE COUNT LONGER.
*
*
DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
STROBE
AUTO ZERO
REFERENCE
INTEGRATE
SIGNAL
INTEGRATE
Figure 8. Strobe Signal Pulses Low Five Times per Conversion
*
DIGIT SCAN
FOR
OVERRANGE
D5
D4
D3
D2
*
The active-low STROBE pulses aid BCD data transfer
to UARTs, microprocessors, and external latches. (See
Application Note AN-16.)
BUSY Output
At the beginning of the signal-integration phase, BUSY
(pin21)goeshighandremainshighuntilthefirstclockpulse
after the integrator zero crossing. BUSY returns to logic "0"
after the measurement cycle ends in an overrange condi-
tion. The internal display latches are loaded during the first
clock pulse after BUSY and are latched at the clock pulse
end. The BUSY signal does not go high at the beginning of
the measurement cycle, which starts with the auto-zero
phase.
D1
Figure 7. Timing Diagrams for Outputs
STROBE Output
During the measurement cycle, the STROBE output
(pin 26) control line is pulsed low five times. The five low
pulses occur in the center of the digit drive signals (D1, D2,
D3, D4 and D5; see Figure 8).
OVERRANGE Output
D5 goes high for 201 counts when the measurement
cycles end. In the center of D5 pulse, 101 clock pulses after
the end of the measurement cycle, the first STROBE occurs
forone-halfclockpulse.AfterD5 strobe,D4 goeshighfor200
clock pulses. STROBE goes low 100 clock pulses after D4
goes high. This continues through the D1 drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVERRANGE
output (pin 27) is set to logic "1." The OVERRANGE output
register is set when BUSY goes low and reset at the
beginning of the next reference-integration phase.
UNDERRANGE Output
If the output count is 9% of full scale or less (≤1800
counts), the UNDERRANGE output (pin 28) register bit is
set at the end of BUSY. The bit is set low at the next signal-
integration phase.
3-120
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3
TC7135
POLARITY Output
adequate. A0.10µFto0.47µFisrecommended. Ingeneral,
Apositiveinputisregisteredbyalogic"1"polaritysignal.
The POLARITY output (pin 23) is valid at the beginning of
reference integrate and remains valid until determined dur-
ing the next conversion.
The POLARITY bit is valid even for a zero reading.
Signals less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null applica-
tions.
the value of CINT is given by:
[10,000 x clock period] x IINT
CINT
=
=
Integrator output voltage swing
(10,000) (clock period) (20 µA)
.
Integrator output voltage swing
A very important characteristic of the CINT is that it has
low dielectric absorption to prevent roll-over or ratiometric
errors. A good test for dielectric absorption is to use the
capacitorwiththeinputtiedtothereference.Thisratiometric
condition should read half-scale 0.9999. Any deviation is
probably due to dielectric absorption. Polypropylene
capacitors give undetectable errors at reasonable cost.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
Digit Drive Outputs
Digitdriveoutputsarepositive-goingsignals.Theirscan
sequence is D5, D4, D3, D2 and D1 (pins 12, 17, 18, 19 and
20, respectively). All positive signals are 200 clock pulses
wide, except D5, which is 201 clock pulses.
All five digits are continuously scanned, unless an
overrange condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse until
the beginning of the next reference-integrate phase. The
scanning sequence is then repeated, providing a blinking
visual display.
Auto-Zero and Reference Capacitors
The size of the auto-zero capacitor (CAZ) has some
influence on system noise. A large capacitor reduces noise.
The reference capacitor (CREF) should be large enough
such that stray capacitance from its nodes to ground is
negligible.
The dielectric absorption of CREF and CAZ is only impor-
tant at power-on, or when the circuit is recovering from an
overload. Smaller or cheaper capacitors can be used if
accurate readings are not required during the first few
seconds of recovery.
BCD Data Outputs
Thebinarycodeddecimal(BCD)outputs, B8, B4, B2 and
B1 (pins 16, 15, 14 and 13, respectively) are positive true-
logic signals. They become active simultaneously with digit
drive signals. In an overrange condition, all data bits are
logic "0".
APPLICATIONS INFORMATION
Component Value Selection
Reference Voltage
Theanaloginputrequiredtogenerateafull-scaleoutput
Integrating Resistor
is VIN = 2 VREF
.
The integrating resistor (RINT) is determined by the full-
scale input voltage and output current of the buffer used to
chargetheintegratorcapacitor(CINT). Boththebufferampli-
fier and the integrator have a Class A output stage, with 100
µA of quiescent current. A 20 µA drive current gives negli-
gible linearity errors. Values of 5 µA to 40 µA give good
results. The exact value of RINT for a 20 µA current is easily
calculated:
The stability of the reference voltage is a major factor in
overall absolute accuracy of the converter. Therefore, it is
recommended that high-quality references be used where
high-accuracy, absolute measurements are being made.
Suitable references are:
Part Type
Manufacturer
TC04
TC05
TelCom Semiconductor
TelCom Semiconductor
Full-scale voltage
RINT
=
.
20 µA
Conversion Timing
Integrating Capacitor
Line Frequency Rejection
The product of RINT and CINT should be selected to give
themaximumvoltageswingtoensuretolerancebuild-upwill
not saturate integrator swing (approximately 0.3V from
eithersupply). For±5Vsupplies, andanalogcommontiedto
supply ground, a ±3.5V to ±4V full-scale integrator swing is
A signal-integration period at a multiple of the 60 Hz line
frequency will maximize 60 Hz "line noise" rejection.
A 100 kHz clock frequency will reject 50 Hz, 60 Hz and
400 Hz noise, corresponding to 2.5 readings per second.
TELCOM SEMICONDUCTOR, INC.
3-121
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
Table 2. Line Frequency Rejection
High-Speed Operation
Oscillator Frequency
(kHz)
Frequency Rejected
Themaximumconversionrateofmostdual-slopeADCs
is limited by frequency response of the comparator. The
comparator in this circuit follows the integrator ramp with a
3µsdelay, andataclockfrequencyof160kHz(6µsperiod),
half of the first reference integrate clock period is lost in
delay. This means the meter reading will change from 0 to
1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 with 250 µV,
etc. This transition at midpoint is considered desirable by
most users; however, if clock frequency is increased appre-
ciably above 160 kHz, the instrument will flash "1" on noise
peaks even when the input is shorted.
(Hz)
300, 200, 150, 120,
100, 40, 33-1/3
60
250, 166-2/3,
125, 100
50
100
50, 60, 400
Table 3. Conversion Rate vs Clock Frequency
Formanydedicatedapplications, wheretheinputsignal
is always of one polarity, comparator delay need not be a
limitation. Since nonlinearity and noise do not increase
substantially with frequency, clock rates up to ~1 MHz may
be used. For a fixed clock frequency, the extra count (or
counts) caused by comparator delay will be constant and
can be digitally subtracted.
The clock frequency may be extended above 160 kHz
without this error, however, by using a low value resistor in
series with the integrating capacitor. The effect of the
resistor is to introduce a small pedestal voltage onto the
integrator output at the beginning of reference-integrate
phase. By careful selection of the ratio between this resis-
tor and the integrating resistor (a few tens of ohms in the
recommended circuit), the comparator delay can be com-
pensated for and maximum clock frequency extended
by approximately a factor of 3. At higher frequencies, ring-
ing and second-order breaks will cause significant
nonlinearities during the first few counts of the instrument.
Theminimumclockfrequencyisestablishedbyleakage
on the auto-zero and reference capacitors. With most de-
vices, measurement cycles as long as 10 seconds give no
measurable leakage error.
Conversion Rate
(Conv/Sec)
Clock
Frequency (kHz)
2.5
3.0
5.0
100
120
200
300
400
800
1200
7.5
10.0
20.0
30.0
Displays and Driver Circuits
TelComSemiconductormanufacturesthreedisplayde-
coder/drivercircuitstointerfacetheTC7135toLCDsorLED
displays. Each driver has 28 outputs for driving four 7-
segment digit displays.
Device
Package
Description
TC7211AIPL
40-Pin Epoxy
4-Digit LCD Driver/Encoder
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the applications section. The multiplexed output
means if the display takes significant current from the logic
supply, the clock should have good PSRR.
Several sources exist for LCDs and LED displays.
Display
Type
Manufacturer
Address
Hewlett Packard
Components
640 Page Mill Road
Palo Alto, CA 94304
LED
Zero-Crossing Flip-Flop
AND
720 Palomar Ave.
Sunnyvale, CA 94086
LCD and
LED
The flip-flop interrogates data once every clock pulse
after transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by
clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
Epson America, Inc.
3415 Kanhi Kawa St.
Torrance, CA 90505
LCD
3-122
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3
TC7135
is disabled for one clock pulse at the beginning of the
reference integrate (deintegrate) phase. This one-count
delay compensates for the delay of the zero-crossing flip-
flop, and allows the correct number to be latched into the
display. Similarly, a one-count delay at the beginning of
auto-zerogivesanoverloaddisplayof0000insteadof0001.
No delay occurs during signal integrate, so true ratiometric
readings result.
+5V
11
1
+
–
V
V
8
(–5V)
10 µF
5
TC7660
+
TC7135
Generating a Negative Supply
4
2
3
+
24
A negative voltage can be generated from the positive
supply by using a TC7660. (See Figure 9.)
10 µF
Figure 9. Negative Supply Voltage Generator
TYPICAL APPLICATIONS
Comparator Clock Circuit
RC Oscillator Circuit
+5V
R
R
1
2
C
16 kΩ
1 kΩ
f
O
56 kΩ
2
3
GATES ARE 74C04
8
+
V
OUT
0.22 µF
7
LM311
–
1
R1 R2
1
1. fO ≈
, RP =
30 kΩ
4
2 C[0.41 RP + 0.70 R1]
R1 + R2
16 kΩ
a. If R = R1 = R2, f 0.55/RC
b. If R2 >> R1, f 0.45/R1C
c. If R2 << R1, f 0.72/R1C
390 pF
+5V
R2
100 kΩ
R4
2 kΩ
2. Examples:
a. f = 120 kHz, C = 420 pF
R1 = R2 ≈ 10.9 kΩ
C2
10 pF
2
3
b. f = 120 kHz, C = 420 pF, R2 = 50 kΩ
R1 = 8.93 kΩ
+
6
7
R2
100 kΩ
V
LM311
–
OUT
c. f = 120 kHz, C = 220 pF, R2 = 5 kΩ
R1 = 27.3 kΩ
4
R3
50 kΩ
1
C1
0.1 µF
TELCOM SEMICONDUCTOR, INC.
3-123
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
TYPICAL APPLICATIONS (Cont.)
4-1/2 Digit ADC With Multiplexed Common Anode LED Display
+5V
20 19
18 17 12
D1 D2 D3 D4 D5
INT OUT
4
5
0.47 µF
120 kHz
1 µF
AZ IN
4.7 kΩ
23
7
POL
6
BUFF
b
c
7
7
7
7
OUT
–
C
100 kΩ
REF
22
10
TC7135
f
1 µF
IN
+
X7
8
C
BLANK MSD ON ZERO
6
REF
100 kΩ
+
+INPUT
–INPUT
9–15
5
ANALOG
INPUT
16
15
14
13
1 µF
D
B8
9
3
RBI
7447
2
1
7
–
C
B
A
B4
B2
B1
16
+5V
ANALOG
COMMON
REF
–
+
V
IN
V
1
2
11
6.8 kΩ
–5V
100 kΩ
TC04
4-1/2 Digit ADC Interfaced to LCD With Digit Blanking on Overrange
+5V
4-1/2 DIGIT LCD
SEGMENT
DRIVE
1/2 CD4030
–5V
5
1
23
BP
D1
–
20
V
POL
CD4081
1/4 CD4030
31
D1
D2
D3
D4
4
INT OUT
19
18
17
32
33
34
0.47 µF
1 µF
D2
D3
D4
5
6
AZ IN
BUFF OUT
100 kΩ
16
CD4071
TC7211A
22
30
29
28
27
B8
120 kHz
+
f
B3
B2
B1
B0
IN
TC7135
15
14
B4
B2
B1
100 kΩ
1
+
10
9
V
+INPUT
–INPUT
35
GND
ANALOG
INPUT
–
13
12
D
D5
Q
1/2
CD4013
CLK
1/4 CD4081
26
27
3
ANALOG
COMMON
STROBE
OR
+5V
S
R
1/4 CD4030
REF
IN
+
V
2
6.8 kΩ
+5V
100 kΩ
TC04
3-124
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
3
TC7135
TYPICAL APPLICATIONS (Cont.)
4-1/2 Digit ADC With Multiplexed Common Cathode LED Display
+5V
+5V
SET V
= 1V
REF
–5V
6.8V
28
27
26
1
–
V
UR
OR
100
kΩ
2
3
TC04
1.22V
REF IN
150Ω
ANALOG
GND
STROBE
47
kΩ
10
11
9
8
7
6
5
4
3
2
1
ANALOG
GND
150Ω
25
24
23
22
21
20
4
5
6
7
8
9
INT
RUN/HOLD
DGND
OUT
1 µF
0.47 µF
12
13
14
15
AZ IN
BUFF
OUT
CD4513
BE
POLARITY
100 kΩ
+
C
CLK IN
BUSY
(LSD) D1
D2
REF
1 µF
100
kΩ
–
C
REF
+5V
16
17
+
–INPUT
+INPUT
SIG
0.1
µF
10
11
12
19
18
17
IN
–
18
+
+5V
D3
V
TC7135
D4
D5 (MSD)
13
14
16
15
(MSB) B8
B4
B1 (LSB)
B2
f
= 120 kHz
O
4-Channel Data Acquisition System
ADDRESS BUS
CONTROL
+
5V
+
DATA BUS
V
REF
CAP
GAIN: 10, 20, 50, 100
+15V –15V
DG529
BUF
AZ
POL
OR
UR
D5
B8
B4
PA0
PA1
PA2
1Y
2Y
3Y
1B
2B
3B
SEL
1A
2A
INT
11
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
+
8
3
TC7135
+
D
A
157
10
LH0084
9
INPUT
3A
B2
D
B
14
–
16
6522
-VIA-
PA3
PA4
PA5
PA6
PA7
CA1
CA2
B1
D1
D2
D3
D4
STB
R/H
f
WR
15
V
R
REF
VOLTAGE
A
A
EN
0
1
–
INPUT
DIFFERENTIAL
MULTIPLEXER
ANALOG
COMMON
DGND
IN
f
IN
GAIN SELECTION
–
5V
PB5
PB4
PB0 PB1 PB2 PB3
CHANNEL SELECTION
TELCOM SEMICONDUCTOR, INC.
3-125
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