STPCC0175BTI3 [STMICROELECTRONICS]
32-BIT, 75MHz, MICROPROCESSOR, PBGA388, PLASTIC, BGA-388;
| 型号： | STPCC0175BTI3 |
| 厂家： | 
ST |
| 描述： | 32-BIT, 75MHz, MICROPROCESSOR, PBGA388, PLASTIC, BGA-388 时钟 外围集成电路 |
| 文件： | 总47页 (文件大小：747K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STPC CLIENT
PC Compatible Embeded Microprocessor
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POWERFUL X86 PROCESSOR
64-BIT 66MHz BUS INTERFACE
64-BIT DRAM CONTROLLER
SVGA GRAPHICS CONTROLLER
UMA ARCHITECTURE
VIDEO SCALER
VIDEO OUTPUT PORT
VIDEO INPUT PORT
CRT CONTROLLER
135MHz RAMDAC
PBGA388
2 OR 3 LINE FLICKER FILTER
SCAN CONVERTER
Figure 1. Logic Diagram
PCI MASTER / SLAVE / ARBITER
ISA MASTER/SLAVE
ISABUS
IDE CONTROLLER
x86
Core
DMA CONTROLLER
ISA
PCI
IPC
EID
INTERRUPT CONTROLLER
TIMER / COUNTERS
Host I/F
POWER MANAGEMENT
EIDE
PCI BUS
CCIR Input
STPC CLIENT OVERVIEW
PCI
VIP
The STPC Client integrates a standard 5th
generation x86 core, a DRAM controller, a
graphics subsystem, a video pipeline, and
support logic including PCI, ISA, and IDE
controllers to provide
orientated PC compatible subsystem on a single
device.
TV Output
a
single Consumer
Anti-
Color
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
colour space conversion of the video intput
stream and mixing of the video stream with non-
video data from the frame buffer. The chip also
includes anti-flicker filters to provide a stable,
high-quality Digital TV output.
Vi-
2D
Co-
lor
Monitor
HW
CRT
SYNC Output
DRAM
The STPC Client is packaged in a 388 Plastic Ball
Grid Array (PBGA).
26/10/99
1/47
Issue 1.6
STPC CLIENT
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X86 Processor core
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Video Pipeline
Fully static 32-bit 5-stage pipeline, x86
processor with DOS, Windows and UNIX
compatibility.
Can access up to 4GB of external memory.
KBytes unified instruction and data cache
with write back and write through capability.
Parallel processing integral floating point unit,
with automatic power down.
Clock core speeds up to of 75 MHz.
Fully static design for dynamic clock control.
Low power and system management modes.
Optimized design for 3.3V operation.
Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Color space conversion (RGB to YUV and
YUV to RGB).
Programmable window size.
Chroma and color keying allowing video
overlay.
Programmable two tap filter with gamma
correction or three tap flicker filter.
Progressive to interlaced scan converter.
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Video Input port
Deodes video inputs in ITU-R 601/656
compatible formats.
Optional 2:1 decimator
Stores captured video in off setting area of
the onboard frame buffer.
Video pass through to the onboard PAL/
NTSC encoder for full screen video images.
HSYNC and B/T generation or lock onto
external video timing source.
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DRAM Controller
Integrated system memory andgraphic frame
memory.
Supports up to 128 MBytes system memory
in 4 banks and as little as MBytes.
Supports 4MBites, 8MBites, 16MBites,
32MBites single-sided and double-sided
DRAM SIMMs.
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Four quad-word write buffers for CPU to
DRAM and PCI to DRAM cycles.
Four 4-word read buffers for PCI masters.
Supports Fast Page Mode & EDO DRAMs.
Programmable timing for DRAM parameters
including CAS pulse width, CAS pre-charge
time, and RAS to CAS delay.
60, 70, 80 & 100ns DRAM speeds.
Memory hole size of of 1 MByte to 8 MBytes
supported for PCI/ISA busses.
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PCI Controller
Integrated PCI arbitration interface able to
directly manage up to 3 PCI masters at a
time.
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
PCI.
Support for burst read/write from PCI master.
The PCI clock runs at a third or half CPU
clock speed.
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Hidden refresh.
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ISA master/slave
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Graphics Controller
64-bit windows accelerator.
The ISA clock generated from either
14.318MHz oscillator clock or PCI clock
Supports programmable extra wait state for
ISA cycles
Supports I/O recovery time for back to back I/
O cycles.
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
Supports flash ROM.
Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.
Backward compatibility to SVGA standards.
Hardware acceleration for text, bitblts,
transparent blts and fills.
Up to 64 x 64 bit graphics hardware cursor.
Up to 4MB long linear frame buffer.
8-, 16-, and 24-bit pixels.
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CRT Controller
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Integrated 135MHz triple RAMDAC allowing
upto 1024 x 768 x 75Hz display.
8-, 16-, 24-bit per pixels.
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Interlaced or non-interlaced output.
2/47
Issue 1.6
STPC CLIENT
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IDE Interface
Supports PIO
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Integrated peripheral controller
2X8237/AT compatible 7-channel DMA
controller.
2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
Three 8254 compatible Timer/Counters.
Supports up to Mode 5 Timings
Supports up to 4 IDE devices
Individual drive timing for all four IDE devices
Concurrent channel operation (PIO modes) -
4 x 32-Bit Buffer FIFO per channel
Support for PIO mode 3 & 4
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Power Management
Four power saving modes: On, Doze,
Standby, Suspend.
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Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers.
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Programmable system activity detector
Supports SMM.
Supports STOPCLK.
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Supports both legacy & native IDE modes
Supports hard drives larger than 528MB
Support for CD-ROM and tape peripherals
Backward compatibility with IDE (ATA-1).
Supports IO trap & restart.
Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.
Supports RTC, interrupts and DMAs wake-up
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3/47
Issue 1.6
STPC CLIENT
4/47
Issue 1.6
GENERAL DESCRIPTION
1.GENERAL DESCRIPTION
At the heart of the STPC Client is an advanced
processor block, dubbed the ST X86. The ST X86
includes a powerful x86 processor core along with
a 64-bit DRAM controller, advanced 64bit acceler-
ated graphics and video controller, a high speed
PCI local-bus controller and Industry standard PC
chip set functions (Interrupt controller, DMA Con-
troller, Interval timer and ISA bus) and EIDE con-
troller.
complies with PCI specification 2.1. The chip-set
also implements the PCI mandatory header regis-
ters in Type 0 PCI configuration space for easy
porting of PCI aware system BIOS. The device
contains a PCI arbitration function for three exter-
nal PCI devices.
The STPC Client integrates an ISA bus controller.
Peripheral modules such as parallel and serial
communications ports, keyboard controllers and
additional ISA devices can be accessed by the
STPC Client chip set through this bus.
The STPC Client has in addition to the 5ST86 a
Video subsystem and high quality digital Televi-
sion output.
An industry standard EIDE (ATA 2) controller is
built into the STPC Client and connected internally
via the PCI bus.
The STMicroelectronics x86 processor core is em-
bedded with standard and application specific pe-
ripheral modules on the same silicon die. The core
has all the functionality of the ST Microelectronics
standard x86 processor products, including the
low power System Management Mode (SMM).
Graphics functions are controlled by the on-chip
SVGA controller and the monitor display is man-
aged by the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations, which include hard-
ware acceleration of text, bitblts, transparent blts
and fills. These operations can operate on off-
screen or on-screen areas. The frame buffer size
is up to 4 MBytes anywhere in the physical main
memory.
System Management Mode (SMM) provides an
additional interrupt and address space that can be
used for system power management or software
transparent emulation of peripherals. While run-
ning in isolated SMM address space, the SMM in-
terrupt routine can execute without interfering with
the operating system or application programs.
Further power management facilities include a
suspend mode that can be initiated from either
hardware or software. Because of the static nature
of the core, no internal data is lost.
The graphics resolution supported is a maximum
of 1280x1024 in 65536 colours at 75Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
The STPC Client makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main memo-
ry and graphics frame-buffer. This significantly re-
duces total system memory with system perform-
ances equal to that of a comparable solution with
separate frame buffer and system memory. In ad-
dition, memory bandwidth is improved by attach-
ing the graphics engine directly to the 64-bit proc-
essor host interface running at the speed of the
processor bus rather than the traditional PCI bus.
STPC Client provides several additional functions
to handle MPEG or similar video streams. The
Video Input Port accepts an encoded digital video
stream in one of a number of industry standard
formats, decodes it, optionally decimates it by a
factor of 2:1, and depositsit into an off screen area
of the frame buffer. An interrupt request can be
generated when an entire field or frame has been
captured.
The 64-bit wide memory array provides the sys-
tem with 320MB/s peak bandwidth, double that of
an equivalent system using 32 bits. This allows for
higher screen resolutions and greater color depth.
The processor bus runs at the speed of the proc-
essor (DX devices) or half the speed (DX2 devic-
es).
The video output pipeline incorporates a video-
scaler and color space converter function and pro-
visions in the CRT controller to display a video
window. While repainting the screen the CRT con-
troller fetches both the video as well as the normal
non-video frame buffer in two separate internal
FIFOs (256-Bytes each). The video stream can be
color-space converted (optionally) and smooth
scaled. Smooth interpolative scaling in both hori-
zontal and vertical direction are implemented.
Color and Chroma key functions are also imple-
mented to allow mixing video stream with non-vid-
eo frame buffer.
The ‘standard’ PC chipset functions (DMA, inter-
rupt controller, timers, power management logic)
are integrated with the x86 processor core.
The PCI bus is the main data communication link
to the STPC Client chip. The STPC Client trans-
lates appropriate host bus I/O and Memory cycles
onto the PCI bus. It also supports the generation
of Configuration cycles on the PCI bus. The STPC
Client, as a PCI bus agent (host bridge class), fully
The video output passes directly to the RAMDAC
for monitor output or through another optional
5/47
Issue 1.6
GENERAL DESCRIPTION
color space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
or a 3 line flicker filter (primarily designed for Win-
dows type displays). The flicker filter is optional
and can be software disabled for use with large
screen area’s of video.
down states: Doze state, Stand-by state and Sus-
pend mode. These correspond to decreasing lev-
els of power savings.
Power down puts the STPC Client into suspend
mode. The processor completes execution of the
current instruction, any pending decoded instruc-
tions and associated bus cycles. During the sus-
pend mode, internal clocks are stopped. remov-
ing power down, the processor resumes instruc-
tion fetching and begins execution in the instruc-
tion stream at the point it had stopped.
The Video output pipeline of the STPC Client in-
terfaces directly to the external digital TV encoder
(STV0119). It takes a 24 bit RGB non-interlaced
pixel stream and converts to a multiplexed 4:2:2
YCrCb 8 bit output stream, the logic includes a
progressive to interlaced scan converter and logic
to insert appropriate CCIR656 timing reference
codes into the output stream. It facilitates the high
quality display of VGA or full screen video streams
received via the Video input port to standard
NTSC or PAL televisions.
A reference design for the STPC Client is availa-
ble including the schematics and layout files, the
design is a PC ATX motherboard design. The de-
sign is available as a demonstration board for ap-
plication and system development.
The STPC Client is supported by several BIOS
vendors, including the super I/O device used in
the reference design. Drivers for 2D accelerator,
video features and EIDE are availaible on various
operating systems.
The STPC Client core is compliant with the Ad-
vanced Power Management (APM) specification
to provide a standard method by which the BIOS
can control the power used by personal comput-
ers. The Power Management Unit module (PMU)
controls the power consumption by providing a
comprehensive set of features that control the
power usage and supports compliance with the
United States Environmental Protection Agency’s
Energy Star Computer Program. The PMU pro-
vides following hardware structures to assist the
software in managing the power consumption by
the system.
The STPC Client has been designed using mod-
ern reusable modular design techniques, it is pos-
sible to add to or remove the standard features of
the STPC Client or other variants of the 5ST86
family. Contact your local STMicroelectonics sales
office for further information.
- System Activity Detection.
- 3 power-down timers detecting system inactivity:
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
- House-keeping activity detection.
- House-keeping timer to cope with short bursts
of house-keeping activity while dozing or in stand-
by state.
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system per-
formance in various power down states of the sys-
tem including full power on state.
- Power control outputs to disable power from dif-
ferent planes of the board.
Lack of system activity for progressively longer
period of times is detected by the three power
down timers. These timers can generate SMI in-
terrupts to CPU so that the SMM software can put
the system in decreasing states of power con-
sumption. Alternatively, system activity in a power
down state can generate SMI interrupt to allow the
software to bring the system back up to full power
on state. The chip-set supports up to three power
6/47
Issue 1.6
GENERAL DESCRIPTION
Figure 1-1. Functionnal description.
x86
Core
ISA BUS
Host I/F
ISA
m/s
IPC
82C206
EIDE
EIDE
PCI m/s
PCI BUS
PCI m/s
VIP
CCIR Input
TV Output
Anti-Flicker
Color Space
Converter
Video
pipeline
Color
Key
Chroma
Key
Monitor
2D
SVGA
HW Cursor
CRTC
SYNC Output
DRAM
I/F
7/47
Issue 1.6
GENERAL DESCRIPTION
Figure 1-2. Pictorial Block DiagramTypical Application
Keyboard / Mouse
Serial Ports
Parallel Port
Floppy
Super I/O
RTC
Flash
2x EIDE
ISA
DMUX
MUX
IRQ
Monitor
SVGA
MUX
DMA.REQ
TV
S-VHS
RGB
PAL
STPC Client
DMA.ACK
NTSC
STV0119
DMUX
Video
CCIR601
CCIR656
PCI
4x 16-bit EDO DRAMs
8/47
Issue 1.6
STRAP OPTION
2. STRAP OPTION
This chapter defines the STPC Client Strap Options and their location
Memory
Data
Lines
Actual
Settings
Refer to
Designation
Reserved
Location
Set to ’0’
Set to ’1’
MD0
MD1
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-
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-
-
-
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-
Reserved
Speed
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-
MD2
DRAM Bank 1
Index 4A, bit 2
Index 4A, bit 3
Index 4A, bit 4
Index 4A, bit 5
Index 4A, bit 6
Index 4A, bit 7
Index 4B, bit 0
Index 4B, bit 1
Index 4B, bit 2
Index 4B, bit 3
Index 4B, bit 4
Index 4B, bit 5
Index 4B, bit 6
Index 4B, bit 7
Index 4C, bit 0
Index 4C, bit 1
Index 4C, bit 2-
Index 4C, bit 3
Index 4C, bit 4
Index 5F, bit 0
Index 5F, bit 1
Index 5F, bit 2
Index 5F, bit 3
Index 5F, bit 4
Index 5F, bit 5
User defined
Pull up
70 ns
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60 ns
-
MD3
Speed
MD4
Type
User defined
User defined
Pull up
EDO
70 ns
FPM
60 ns
MD5
DRAM Bank 0
Speed
MD6
Speed
MD7
Type
User defined
Pull up
EDO
FPM
MD8
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Reserved
Reserved
Speed
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-
MD9
-
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-
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
DRAM Bank 3
User defined
Pull up
70 ns
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60 ns
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Speed
Type
User defined
User defined
Pull up
EDO
70 ns
FPM
60 ns
DRAM Bank 2
Speed
Speed
Type
User defined
Pull up
EDO
FPM
-
Reserved
PCI_CLKO Divisor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HCLK PLL Speed
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-
PCI Clock
User defined
Pull up
HCLK /2
HCLK /3
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-
-
-
Pull up
-
-
-
Pull up
-
-
-
Pull up
-
-
-
-
Pull up
-
-
Pull up
-
-
HCLK
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
Pull up
000
Reserved
001
Reserved
010
Reserved
011
25 MHz
100
50 MHz
101
60 MHz
110
66 MHz
111
75 MHz
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pull up
Pull up
Pull up
Pull down
Pull up
Pull up
Pull down
Pull up
-
-
-
9/47
Issue 1.6
STRAP OPTION
Memory
Data
Lines
Actual
Settings
Refer to
Designation
Reserved
Location
Set to ’0’
Set to ’1’
MD39
MD40
MD41
MD42
MD43
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Note; Setting of StrapOptionsMD [15:2] havenoeffect ontheDRAM Controller but arepurely meant for software
issues. i.e. Readable in aregister.
2.1 Power on strap registers description
2.1.1 Strap register 0 Index 4Ah (Strap0)
Bits 7-0; This register reflect the status of pinsMD[ 7:0] respectively. They are expected to be connected on the sys-
tem board to theSIMM configuration pins asfollows:
Bit Sampled
Bit 7
Description
SIMM 0 DRAM type
SIMM 0 speed
SIMM 1 DRAM type:
SIMM 1 speed
Reserved
Bits 6-5
Bit 4
Bits 3-2
Bit 1
Bit 0
Reserved
Notethat theSIMM speed and typeinformation read hereis meant only for the
softwareand isnot used by thehardware. Thesoftwaremust program theHost and
graphics dram controller configuration registersappropriately basedon these
bits.
This register defaults to thevalues sampled onMD[7:0] pinsafter reset.
2.1.2 Strap register 1 Index 4Bh (Strap1)
Bits7-0; This register reflect thestatusof pinsMD[15:8] respectively. They areexpected tobeconnected onthesys-
tem board to theSIMM configuration pins asfollows:
Bit Sampled
Bit 7
Description
SIMM 2 DRAM type
SIMM 2 speed
SIMM 3 dram type
SIMM 3 speed
Reserved
Bits 6-5
Bit 4
Bits 3-2
Bit 1
Bit 0
Reserved
10/47
Issue 1.6
STRAP OPTION
Notethat theSIMM speedand typeinformation read hereismeant only for thesoftwareand isnot used by thehard-
ware. Thesoftwaremust program theHost andgraphics dram controller configuration registers appropriately based
on thesebits.
This register defaults to thevalues sampled onMD[15:8] pinsafter reset.
2.1.3 Strap register 2 Index 4Ch (Strap2)
Bits4-0; This register reflect thestatusof pinsMD[20:16] respectively.They areuseby thechip asfollows:
Bit 4-2; Reserved.
Bit 1; This bit reflectsthevaluesampled on MD[17] pin and controls thePCI clock output asfollows:
0: PCI clock output = HCLK / 3
1: PCI clock output = HCLK / 2.
Bi t 0; Reserved.
This register defaults to thevalues sampled onMD[20:16] pinsafter reset.
2.1.4 HCLK PLL Strap register Index 5Fh (HCLK_Strap)
Bits5-0 of thisregister reflect thestatusof theMD[26:21] & areused asfollows:
Bit 5-3 Thesepinsreflect thevaluesampled onMD[26:24] pinsrespectively and control the Host clock frequency
synthesizer
Bit 2- 0 Reserved
This register defaults to thevalues sampled onabove pinsafter reset.
These pin must not bepulled low for normal system operation.
Strap Registers [43:27] arereserved.
11/47
Issue 1.6
PIN DESCRIPTION
3.PIN DESCRIPTION
3.1. INTRODUCTION
The STPC Client integrates most of the
functionalities of the PC architecture. As a
result,
many
of
the
traditional
Table 3-1. Signal Description
interconnections between the host PC
microprocessor and the peripheral devices
are totally assimilated to the STPC Client.
This offers improved performance due to
the tight coupling of the processor core and
its peripherals. As a result many of the
external pin connections are made directly
to the on-chip peripheralfunctions.
Group name
Basic Clocks reset & Xtal (SYS)
Memory Interface (DRAM)
PCI interface (excluding VDD5)
ISA / IDE / IPC combined interface
Video Input (VIP)
Qty
14
89
54
83
9
TV Output (TV)
10
10
69
26
14
10
388
VGA Monitor interface (VGA)
Grounds
Figure 3-1 shows the STPC Client’s
external interfaces. It defines the main
busses and their function. Table 3-1
describes the physical implementation
listing signals type and their functionality.
Table 3-2 provides a full pin listing and
description of the pins. Table 3-3 provides a
full listing of pin locations of the STPC
Client package by physical connection.
Please refer to the pin allocation drawing for
reference.
V
DD
Analog specific V /V
CC DD
Reserved/Test/ Misc/ Speaker
Total Pin Count
Note:
Several
interface
pins
are
multiplexed with other functions, refer to the
Pin Description section for further details
Figure 3-1. STPC Client External Interfaces
STPC CLIENT
X86
EAST
PCI
WEST
VIP
TV
10
SYS
14
DRAM VGA
ISA/IDE
IPC
10
10
9
89
54
73
12/47
Issue 1.6
PIN DESCRIPTION
Table 3-2. Definition of Signal Pins
Signal Name
Dir
Description
System Reset / Power good
Qty
BASIC CLOCKS RESETS & XTAL
SYSRSTI#
SYSRSTO#
XTALI
I
O
I
1
1
1
1
1
1
1
Reset Output to System
14.3MHz External Oscilator Input
14.3MHz External Oscillator Input
33MHz PCI Input Clock
XTALO
I/O
I
PCI_CLKI
PCI_CLKO
ISA_CLK
ISA_CLK2X
OSC14M
HCLK
O
O
O
O
O
O
I/O
I/O
I
33MHz PCI Output Clock (from internal PLL)
ISA Clock Output - Multiplexer Select Line For IPC
ISA Clock x 2 Output - Multiplexer Select Line For IPC
ISA bus synchronisation clock
Host Clock (Test)
1
1
1
1
1
1
1
DEV_CLK
GCLK2X
DCLK
24MHz Peripheral Clock (floppy drive)
80MHz Graphics Clock
135MHz Dot Clock
DCLK _DIR
Dot Clock Direction
V
_xxx_PLL
Power Supply for PLL Clocks
DD
MEMORY INTERFACE
MA[11:0]
I/O
O
Memory Address
Row Address Strobe
Column Address Strobe
Write Enable
12
4
RAS#[3:0]
CAS#[7:0]
O
8
MWE#
O
1
MD[63:0]
I/O
Memory Data
64
PCI INTERFACE
AD[31:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
32
4
1
1
1
1
1
1
1
1
3
3
4
4
CBE[3:0]
FRAME#
TRDY#
Target Ready
IRDY#
Initiator Ready
STOP#
Stop Transaction
Device Select
DEVSEL#
PAR
Parity Signal Transactions
System Error
SERR#
LOCK#
I
PCI Lock
PCI_REQ#[2:0]
PCI_GNT#[2:0]
PCI_INT[3:0]
VDD5
I
PCI Request
O
PCI Grant
I
PCI Interrupt Request
5V Power Supply for PCI ESD protection
I
ISA AND IDE COMBINED ADDRESS/DATA
LA[23:22] / SCS3#,SCS1#
LA[21:20] / PCS3#,PCS1#
LA[19:17] / DA[2:0]
I/O
I/O
O
Unlatched Address (ISA) / Secondary Chip Select (IDE)
Unlatched Address (ISA) / Primary Chip Select (IDE)
Unlatched Address (ISA) / Address (IDE)
2
2
3
1
1
1
RMRTCCS# / DD[15]
KBCS# / DD[14]
I/O
I/O
I/O
ROM/RTC Chip Select / Data Bus bit 15 (IDE)
Keyboard Chip Select / Data Bus bit 14 (IDE)
RTC Read/Write / Data Bus bit 13 (IDE)
RTCRW# / DD[13]
13/47
Issue 1.6
PIN DESCRIPTION
Table 3-2. Definition of Signal Pins
Signal Name
RTCDS# / DD[12]
SA[19:8] / DD[11:0]
SA[7:0]
Dir
I/O
I/O
I/O
I/O
Description
RTC Data Strobe / Data Bus bit 12 (IDE)
Latched Address (ISA) / Data Bus (IDE)
Latched Address (IDE)
Qty
1
16
4
SD[15:0]
Data Bus (ISA)
16
ISA/IDE COMBINED CONTROL
IOCHRDY / DIORDY
ISA CONTROL
ALE
I/O
I/O Channel Ready (ISA) - Busy/Ready (IDE)
1
O
I/O
I/O
O
Address Latch Enable
1
1
2
2
2
1
2
1
1
1
1
1
BHE#
System Bus High Enable
Memory Read and Memory Write
System Memory Read and Memory Write
I/O Read and Write
MEMR#, MEMW#
SMEMR#, SMEMW#
IOR#, IOW#
MASTER#
I/O
I
Add On Card Owns Bus
Memory/IO Chip Select16
Refresh Cycle.
MCS16#, IOCS16#
REF#
I
O
AEN
O
Address Enable
IOCHCK#
I
I/O Channel Check.
ISAOE#
O
Bidirectional OE Control
General Purpose Chip Select
GPIOCS#
I/O
IDE CONTROL
PIRQ
I
I
Primary Interrupt Request
Secondary Interrupt Request
Primary DMA Request
Secondary DMA Request
Primary DMA Acknowledge
Secondary DMA Acknowledge
Primary I/O Read
1
1
1
1
1
1
1
1
1
1
SIRQ
PDRQ
I
SDRQ
I
PDACK#
SDACK#
PIOR#
O
O
I/O
O
I/O
O
PIOW#
Primary I/O Write
SIOR#
Secondary I/O Read
SIOW#
Secondary I/O Write
IPC
IRQ_MUX[3:0]
DREQ_MUX[1:0]
DACK_ENC[2:0]
TC
I
Multiplexed Interrupt Request
Multiplexed DMA Request
DMA Acknowledge
4
2
3
1
I
O
O
ISA Terminal Count
MONITOR INTERFACE
RED, GREEN, BLUE
VSYNC
O
O
O
I
Red, Green, Blue
3
1
1
1
1
1
1
1
Vertical Synchronization
HSYNC
Horizontal Synchronization
DAC Voltage reference
VREF_DAC
RSET
I
Resistor Set
COMP
I
Compensation
SCL / DDC[1]
SDA / DDC[0]
I/O
I/O
I C Interface - Clock / Can be used for VGA DDC[1] signal
I C Interface - Data / Can be used for VGA DDC[0] signal
14/47
Issue 1.6
PIN DESCRIPTION
Table 3-2. Definition of Signal Pins
Signal Name
VIDEO INPUT
Dir
Description
Qty
VCLK
I
I
Pixel Clock
1
8
VIDEO_D[7:0]
YUV Video Data Input CCIR 601 or 656
DIGITAL TV OUTPUT
TV_YUV[7:0]
O
O
O
Digital Video Outputs
8
1
1
VTV_BT#
Frame Synchronisation
VTV_HSYNC
Horizontal Line Synchronisation
MISCELLANEOUS
ST[6:0]
I/O
I/O
Test/Misc pins
7
3
CLKDEL[2:0]
Reserved (Test/Misc pins)
15/47
Issue 1.6
PIN DESCRIPTION
3.2.SIGNAL DESCRIPTIONS
transactions. In normal mode, this output
clock is generated by the internal pll.
3.2.1. BASIC CLOCKS RESETS & XTAL
PWGD System Reset/Power good. This
input is low when the the reset switch is
depressed. Otherwise, it reflects the
power supply’s power good signal.
PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset
circuit initiates a hard reset on the rising
edge of PWGD.
GCLK2X 80MHz Graphics Clock. This is
the Graphics 2X clock, which drives the
graphics engine and the the DRAM
controller to execute the graphics and
display cycles.
Normally GCLK2X is generated by the
internal frequency synthesizer, and this
pin is an output. By setting a bit in Strap
Register 2, this pin can be made an input
so that an external clock can replace the
internal frequency synthesizer.
XTALI 14.3MHz Pull Down (10 kOhm)
XTALO 14.3MHz External Oscillator
Input These pins are the 14.318 MHz
external oscilator input; This clock is
used as the reference clock for the
DCLK 135MHz Dot Clock. This is the dot
clock, which drives graphics display
cycles. Its frequency can be as high as
135 MHz, and it is required to have a
worst case duty cycle of 60-40.
internal
frequency
synthesizer to
generate the HCLK, CLK24M, GCLK2X
and DCLK clocks.
This signal is either driven by the internal
pll (VGA) or either by an external 27MHz
oscillator (TV).
HCLK Host Clock. This is the host 1X
clock. Its frequency can vary from 25 to
75 MHz. All host transactions and PCI
transactions are synchronized to this
clock. This clock drives the DRAM
DCLK_DIR
Dot
Clock
Direction.
Specifies if DCLK is an input (0) or an
output (1).
controller
to
execute
the
host
16/47
Issue 1.6
PIN DESCRIPTION
DEV_CLK 24MHz Peripheral Clock
Output. This 24MHZ signal is provided as
a convenience for the system integration
of a Floppy Disk driver function in an
external chip.
These pins are always outputs, but they
can also simultaneously be inputs, to
allow the memory controller to monitor
the value of the CAS# signals at the pins.
MWE# Write Enable Output. Write
enable specifies whether the memory
access is a read (MWE# = H) or a write
(MWE# = L). This single write enable
controls all DRAMs. It can be externally
buffered to boost the maximum number
of loads (DRAM chips) supported.
3.2.2. MEMORY INTERFACE
MA[11:0] Memory Address Output.
These 12 multiplexed memory address
pins support external DRAM with up to
4K refresh. These include all 16M x N
and some 4M x N DRAM modules. The
address signals must be externally
buffered to support more than 16 DRAM
chips. The timing of these signals can be
adjusted by software to match the timings
of most DRAM modules.
The MWE# signals drive the SIMMs
directly without any external buffering.
3.2.3. VIDEO INPUT
VCLK Pixel Clock Input.
MD[63:0] Memory Data I/O. This is the
64-bit memory data bus. If only half of a
bank is populated, MD63-32 is pulled
high, data is on MD31-0.
MD[40-0] are read by the device strap
option registers during rising edge of
PWGD.
VIDEO_D[7:0] YUV Video Data Input
CCIR 601 or 656. Time multiplexed 4:2:2
luminance and chrominance data as
defined in ITU-R Rec601-2 and Rec656
(except for TTL input levels). This bus
interfaces with an MPEG video decoder
output port and typically carries a stream
of Cb,Y,Cr,Y digital video at VCLK
frequency, clocked on the rising edge (by
default) of VCLK. A 54-Mbit/s ‘double’
Cb, Y, Cr, Y input multiplex is supported
for double encoding applications (rising
and falling edge of CKREF are
operating).
RAS#[3:0] Row Address Strobe Output.
There are 4 active low row address
strobe outputs, one for each bank of the
memory. Each bank contains 4 or 8-
Bytes of data. The memory controller
allows half of a bank (4-Bytes) to be
populated to enable memory upgrade at
finer granularity.
The RAS# signals drive the SIMMs
directly without any external buffering.
These pins are always outputs, but they
can also simultaneously be inputs, to
allow the memory controller to monitor
the value of the RAS# signals at the pins.
3.2.4. TV OUTPUT
TV_YUV[7:0] Digital video outputs.
VTV_BT# Frame Synchronization.
VTV_HSYNC
Horizontal
Line
Synchronization.
CAS#[7:0] Column Address Strobe
Output. There are 8 active low column
address strobe outputs, one for each
Byte of the memory.
3.2.5. PCI INTERFACE
PCI_CLKI 33MHz PCI Input Clock
The CAS# signals drive the SIMMs either
directly or through external buffers.
This signal is the PCI bus clock input and
should be driven from the PCI_CLKO pin.
17/47
Issue 1.6
PIN DESCRIPTION
abort protocol of the PCI bus. It is used
as an input for the bus cycles initiated by
the STPC Client and is used as an output
when a PCI master cycle is targeted to
the STPC Client.
PCI_CLKO 33MHz PCI Output Clock.
This is the master PCI bus clock output.
AD[31:0] PCI Address/Data. This is the
32-bit PCI multiplexed address and data
bus. This bus is driven by the master
during the address phase and data
phase of write transactions. It is driven by
the target during data phase of read
transactions.
DEVSEL# I/O Device Select. This signal
is used as an input when the STPC Client
initiates a bus cycle on the PCI bus to
determine if a PCI slave device has
decoded itself to be the target of the
current transaction. It is asserted as an
output either when the STPC Client is the
target of the current PCI transaction or
when no other device asserts DEVSEL#
prior to the subtractive decode phase of
the current PCI transaction.
CBE#[3:0]
Bus
Commands/Byte
Enables. These are the multiplexed
command and Byte enable signals of the
PCI bus. During the address phase they
define the command and during the data
phase they carry the Byte enable
information. These pins are inputs when
a PCI master other than the STPC Client
owns the bus and outputs when the
STPC Client owns the bus.
PAR Parity Signal Transactions. This is
the parity signal of the PCI bus. This
signal is used to guarantee even parity
across AD[31:0], CBE#[3:0], and PAR.
This signal is driven by the master during
the address phase and data phase of
write transactions. It is driven by the
target during data phase of read
transactions. (Its assertion is identical to
that of the AD bus delayed by one PCI
clock cycle)
FRAME# Cycle Frame. This is the frame
signal of the PCI bus. It is an input when
a PCI master owns the bus and is an
output when STPC Client owns the PCI
bus.
TRDY# Target Ready. This is the target
ready signal of the PCI bus. It is driven as
an output when the STPC Client is the
target of the current bus transaction. It is
used as an input when STPC Client
initiates a cycle on the PCI bus.
SERR# System Error. This is the system
error signal of the PCI bus. It may, if
enabled, be asserted for one PCI clock
cycle if the target aborts an STPC Client
initiated PCI transaction. Its assertion by
either the STPC Client or by another PCI
bus agent will trigger the assertion of NMI
to the host CPU. This is an open drain
output.
IRDY# Initiator Ready. This is the initiator
ready signal of the PCI bus. It is used as
an output when the STPC Client initiates
a bus cycle on the PCI bus. It is used as
an input during the PCI cycles targeted to
the STPC Client to determine when the
current PCI master is ready to complete
the current transaction.
LOCK# PCI Lock. This is the lock signal
of the PCI bus and is used to implement
the exclusive bus operations when acting
as a PCI target agent.
PCI_REQ#[2:0] PCI Request. These
pins are the three external PCI master
STOP# Stop Transaction. Stop is used to
implement the disconnect, retry and
18/47
Issue 1.6
PIN DESCRIPTION
request pins. They indicate to the PCI
arbiter that the external agents require
use of the bus.
signal before driving the IDE devices to
guarantee it is active only when ISA bus
is idle.
PCI_GNT#[2:0] PCI Grant. These pins
indicate that the PCI bus has been
granted master, requesting it on its
PCI_REQ#.
LA[22]/SCS1# Unlatched Address (ISA)/
Secondary Chip Select (IDE)
This pin has two functions, depending on
whether the ISA bus is active or the IDE
bus is active.
When the ISA bus is active, this pins is
ISA Bus unlatched address bit 22 for 16-
bit devices. When ISA bus is accessed
by any cycle initiated from PCI bus, this
pin is in output mode. When an ISA bus
master owns the bus, this pins is in input
mode.
When the IDE bus is active, this signals is
used as the active high secondary slave
IDE chip select signal. This signal is to be
externally ANDed with the ISAOE# signal
before driving the IDE devices to
guarantee it is active only when ISA bus
is idle.
3.2.6. ISA/IDE COMBINED ADDRESS/DATA
LA[23]/SCS3# Unlatched Address (ISA)/
Secondary Chip Select (IDE). This pin
has two functions, depending on whether
the ISA bus is active or the IDE bus is
active.
When the ISA bus is active, this pins is
ISA Bus unlatched address bit 23 for 16-
bit devices. When ISA bus is accessed
by any cycle initiated from PCI bus, this
pin is in output mode. When an ISA bus
master owns the bus, this pins is in input
mode.
When the IDE bus is active, this signals is
used as the active high secondary slave
IDE chip select signal. Thissignal is to be
externally NANDed with the ISAOE#
19/47
Issue 1.6
PIN DESCRIPTION
LA[21]/PCS3# Unlatched Address (ISA)/
mode. When an ISA bus master owns the
bus, these pins are tristated.
Primary Chip Select (IDE). This pin has
two functions, depending on whether the
ISA bus is active or the IDE bus is active.
When the ISA bus is active, this pins is
ISA Bus unlatched address bit 21 for 16-
bit devices. When ISA bus is accessed
by any cycle initiated from PCI bus, this
pin is in output mode. When an ISAbus
master owns the bus, this pins is in input
mode.
For IDE devices, these signals are used
as the DA[2:0] and are connected directly
or through a buffer to DA[2:0] of the IDE
devices. If the toggling of signals are to
be masked during ISA bus cycles, they
can be externally ORed before being
connected to the IDE devices.
SA[19:8]/DD[11:0] Unlatched Address
(ISA)/Data Bus (IDE). These are
multifunction pins. When the ISA bus is
active, they are used as the ISA bus
system address bits 19-8. When the IDE
bus is active, they serve as IDE signals
DD[11:0].
When the IDE bus is active, this signals is
used as the active high primary slave IDE
chip select signal. This signal is to be
externally NANDed with the ISAOE#
signal before driving the IDE devices to
guarantee it is active only when ISA bus
is idle.
These pins are used as an input when an
ISA bus master owns the bus and are
outputs at all other times.
IDE devices are connected to SA[19:8]
directly and the ISA bus is connected to
LA[20]/PCS1# Unlatched Address (ISA)/
Primary Chip Select (IDE). This pin has
two functions, depending on whether the
ISA bus is active or the IDE bus is active.
When the ISA bus is active, this pins is
ISA Bus unlatched address bit 20 for 16-
bit devices. When the ISA bus is
accessed by any cycle initiated from PCI
bus, this pin is in output mode. When an
ISA bus master owns the bus, this pins is
in input mode.
these pins through
two LS245
transceivers. The tranceiver OEs are
connected to ISAOE# and the DIR is
connected to MASTER#. The tranceiver
bus signals are connected to the CPC
and IDE DD busses and B bus signals
are connected to ISA SA bus.
When the IDE bus is active, this signals is
used as the active high primary slave IDE
chip select signal. This signal is to be
externally NANDed with the ISAOE#
signal before driving the IDE devices to
guarantee it is active only when ISA bus
is idle.
DD[15:12] Databus (IDE). The high 4 bits
of the IDE databus are combined with
several of the X-bus lines. Refer to the
following section for X-bus pins for further
information.
SA[7:0] ISA Bus address bits [7:0].
These are the 8 low bits of the system
address bus of ISA on 8-bit slot. These
pins are used as an input when an ISA
bus master owns the bus and are outputs
at all other times.
LA[19:17]/DA[2:0] Unlatched Address
(ISA)/Address (IDE). These pins are
multi-function pins. They are used as the
ISA bus unlatched address bits [19:17]
for ISA bus or the three address bits for
the IDE bus devices.
When used by the ISA bus, these pins
are ISA Bus unlatched address bits 19-
17 on 16-bit devices. When the ISA bus
is accessed by any cycle initiated from
the PCI bus, these pins are in output
SD[15:0] I/O Data Bus (ISA). These pins
are the external databus to the ISA bus.
20/47
Issue 1.6
PIN DESCRIPTION
3.2.7. ISA/IDE COMBINED CONTROL
IOCHRDY/DIORDY Channel Ready
(ISA)/Busy/Ready (IDE). This is a multi-
function pin. When the ISA bus is active,
this pin is IOCHRDY. When the IDE bus
is active, this serves as IDE signal
DIORDY.
IOCHRDY is the IO channel ready signal
of the ISA bus and is driven as an output
in response to an ISA master cycle
targeted to the host bus or an internal
register of the STPC Client. The STPC
Client monitors this signal as an input
when performing an ISA cycle on behalf
of the host CPU, DMA master or refresh.
ISA masters which do not monitor
IOCHRDY are not guaranteed to work
with the STPC Client since the access to
the system memory can be considerably
delayed due to CRT refresh or a write
back cycle.
OSC14M ISA bus synchronisation clock
Output. This is the buffered 14.318 Mhz
clock to the ISA bus.
ALE Address Latch Enable. This is the
address latch enable output of the ISA
bus and is asserted by the STPC Client
to indicate that LA23-17, SA19-0, AEN
and SBHE# signals are valid. The ALE is
driven high during refresh, DMA master
or ISA master cycles by the STPC Client.
ALE is driven low after reset.
BHE# System Bus High Enable. This
signal, when asserted, indicates that a
data Byte is being transferred on SD15-8
lines. It is used as an input when an ISA
master owns the bus and is an output at
all other times.
MEMR# Memory Read. This is the
memory read command signal of the ISA
bus. It is used as an input when an ISA
master owns the bus and is an output at
all other times.
3.2.8. ISA CONTROL
SYSRSTO# Reset Output to System.
This is the system reset signal and is
used to reset the rest of the components
(not on Host bus) in the system. The ISA
bus reset is an externally inverted
buffered version of this output and the
PCI bus reset is an externally buffered
version of this output.
The MEMR# signal is active during
refresh.
MEMW# Memory Write. This is the
memory write command signal of the ISA
bus. It is used as an input when an ISA
master owns the bus and is an output at
all other times.
ISA_CLK ISA Clock Output (also
Multiplexer Select Line For IPC). This pin
produces the Clock signal for the ISA
bus. It is also used with ISA_CLK2X as
the multiplexor control lines for the
Interrupt Controller Interrupt input lines.
This is a divided down version of either
the PCICLK or OSC14M.
SMEMR# System Memory Read. The
STPC Client generates SMEMR# signal
of the ISA bus only when the address is
below 1MByte or the cycle is a refresh
cycle.
ISA_CLKX2 ISA Clock Output (also
Multiplexer Select Line For IPC). This pin
produces a signal at twice the frequency
of the Clock signal for the ISA bus. It is
also used with ISA_CLK as the
multiplexor control lines for the Interrupt
Controller Interrupt input lines.
SMEMW# System Memory Write. The
STPC Client generates SMEMW# signal
of the ISA bus only when the address is
below one MByte.
21/47
Issue 1.6
PIN DESCRIPTION
IOR# I/O Read. This is the IO read
AEN Address Enable. Address Enable is
enabled when the DMA controller is the
bus owner to indicate that a DMA transfer
will occur. The enabling of the signal
indicates to IO devices to ignore the
IOR#/IOW# signal during DMA transfers.
command signal of the ISA bus. It is an
input when an ISA master owns the bus
and is an output at all other times.
IOW# I/O Write. This is the IO write
command signal of the ISA bus. It is an
input when an ISA master owns the bus
and is an output at all other times.
IOCHCK# IO Channel Check. IO
Channel Check is enabled by any ISA
device to signal an error condition that
can not be corrected. NMI signal
becomes active upon seeing IOCHCK#
active if the corresponding bit in Port B is
enabled.
MASTER# Add On Card Owns Bus. This
signal is active when an ISA device has
been granted bus ownership.
MCS16# Memory Chip Select 16. This is
the decode of LA23-17 address pins of
the ISA address bus without any
qualification of the command signal lines.
MCS16# is always an input. The STPC
Client ignores this signal during IO and
refresh cycles.
ISAOE# Bidirectional OE Control. This
signal controls the OE signal of the
external transceiver that connects the
IDE DD bus and ISA SA bus.
GPIOCS# I/O General Purpose Chip
Select 1. This output signal is used by the
external latch on ISA bus to latch the data
on the SD[7:0] bus. The latch can be use
by the PMU unit to control the external
peripheral devices to power down or any
other desired function.
IOCS16# IO Chip Select16. This signal is
the decode of SA15-0 address pins of the
ISA address bus without any qualification
of the command signals. The STPC
Client does not drive IOCS16# (similar to
PC-AT design). An ISA master access to
an internal register of the STPC Client is
executed as an extended 8-bit IO cycle.
This pin is also serves as a strap input
during reset.
3.2.9. IDE CONTROL
PIRQ Primary Interrupt Request.
Interrupt request from primary IDE
channel.
REF# Refresh Cycle. This is the refresh
command signal of the ISA bus. It is
driven as an output when the STPC
Client performs a refresh cycle on the
ISA bus. It is used as an input when an
ISA master owns the bus and is used to
trigger a refresh cycle.
SIRQ Secondary Interrupt Request.
Interrupt request from secondary IDE
channel.
The STPC Client performs a pseudo
hidden refresh. It requests the host bus
for two host clocks to drive the refresh
address and capture it in external buffers.
The host bus is then relinquished while
the refresh cycle continues on the ISA
bus.
PDRQ Primary DMA Request. DMA
request from primary IDE channel.
SDRQ Secondary DMA Request. DMA
request from secondary IDE channel.
22/47
Issue 1.6
PIN DESCRIPTION
PDACK# Primary DMA Acknowledge.
DMA acknoledgeto primary IDE channel.
keyboard access is decoded during a I/O
cycle.
When ISAOE# is inactive, this signal is
used as IDE DD[14] signal.
SDACK# Secondary DMA Acknowledge.
DMA acknoledge to secondary IDE
channel.
This signal must be ORed externally with
ISAOE# and is then connected to the
keyboard. An LS244 or equivalent
function can be used if OE# is connected
to ISAOE# and the output is provided
with a weak pull-up resistor.
PIOR# Primary I/O Read. Primary
channel read. Active low output.
RTCRW# / DD[13] Real Time Clock RW.
This pin is a multi-function pin. When
ISAOE# is active, this signal is used as
RTCRW#. This signal is asserted for any
I/O write to port 71H.
PIOW# Primary I/O Write. Primary
channel write. Active low output.
SIOR# Secondary I/O Read Secondary
channel read. Active low output.
When ISAOE# is inactive, this signal is
used as IDE DD[13] signal.
This signal must be ORed externally with
ISAOE# and then connected to the RTC.
An LS244 or equivalent function can be
used if OE is connected to ISAOE# and
the output is provided with a weak pull-up
resistor.
SIOW# Secondary I/O Write Secondary
channel write. Active low output.
3.2.10. X-BUS INTERFACE PINS / IDE DATA
RMRTCCS# / DD[15] ROM/Real Time
clock chip select. This pin is a multi-
function pin. When ISAOE# is active, this
signal is used as RMRTCCS#. This
signal is asserted if a ROM access is
decoded during a memory cycle. It
should be combined with MEMR# or
MEMW# signals to properly access the
ROM. During an IO cycle, this signal is
asserted if access to the Real Time Clock
(RTC) is decoded. It should be combined
with IOR or IOW# signals to properly
access the real time clock.
RTCDS# / DD[12] Real Time Clock DS.
This pin is a multi-function pin. When
ISAOE# is active, this signal is used as
RTCDS. This signal is asserted for any I/
O read to port 71H.
When ISAOE# is inactive, this signal is
used as IDE DD[12] signal.
This signal must be ORed externally with
ISAOE# and is then connected to RTC.
An LS244 or equivalent function can be
used if OE# is connected to ISAOE# and
the output is provided with a weak pull-up
resistor.
When ISAOE# is inactive, this signal is
used as IDE DD[15] signal.
This signal must be ORed externally with
ISAOE# and is then connected to ROM
and RTC. An LS244 or equivalent
function can be used if OE# is connected
to ISAOE# and the output is provided
with a weak pull-up resistor.
3.2.11. IPC
IRQ_MUX[3:0] Multiplexed Interrupt
Request. These are the ISA bus interrupt
signals. They are to be encoded before
connection to the STPC Client using
ISACLK and ISACLKX2 as the input
selection strobes.
KBCS# / DD[14] Keyboard Chip Select.
This pin is a multi-function pin. When
ISAOE# is active, this signal is used as
KBCS#. This signal is asserted if a
Note that IRQ8B, which by convention is
connected to the RTC, is inverted before
23/47
Issue 1.6
PIN DESCRIPTION
being sent to the interrupt controller, so
that it may be connected directly to the
IRQ pin of the RTC.
synchronization signal from the VGA
controller.
VREF_DAC DAC Voltage reference. An
external voltage reference is connected
to this pin to bias the DAC.
PCI_INT[3:0] PCI Interrupt Request.
These are the PCI bus interrupt signals.
They are to be encoded before
connection to the STPC Client using
ISACLK and ISACLKX2 as the input
selection strobes.
RSET Resistor Current Set. This
reference current input to the RAMDAC
is used to set the full-scale output of the
RAMDAC.
DREQ_MUX[1:0] ISA Bus Multiplexed
DMA Request. These are the ISA bus
DMA request signals. They are to be
encoded before connection to the STPC
Client using ISACLK and ISACLKX2 as
the input selection strobes.
COMP Compensation. This is the
RAMDAC compensation pin. Normally,
an external capacitor (typically 10nF) is
connected between this pin and V
damp oscillations.
to
DD
DACK_ENC[2:0] DMA Acknowledge.
These are the ISA bus DMA
acknowledge signals. They are encoded
by the STPC Client before output and
should be decoded externally using
ISACLK and ISACLKX2 as the control
strobes.
DDC[1:0] Direct Data Channel Serial
Link. These bidirectional pins are
connected to CRTC register 3Fh to
implement DDC capabilities. They
conform to I C electrical specifications,
they have open-collector output drivers
2
which are internally connected to V
through pull-up resistors.
DD
TC ISA Terminal Count. This is the
terminal count output of the DMA
controller and is connected to the TC line
of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count
expires.
They can instead be used for accessing
I C devices on board. DDC1 and DDC0
correspond
to
SCL
and
SDA
respectively.
3.2.13. MISCELLANEOUS
ST[6], Reserved.
ST[5] This is used for speaker output.
ST[4] Reserved.
3.2.12. MONITOR INTERFACE
RED, GREEN, BLUE RGB Video
Outputs. These are the 3 analog color
outputs from the RAMDACs
ST[3:0] The pins are for testing the
STPC. The default settings on these pins
should be 1111 for the STPC to function
correctly. By setting the ST[3:0] to 0111,
the STPC is tristated.
VSYNC Vertical Synchronization Pulse.
This is the vertical synchronization signal
from the VGA controller.
CLKDEL[2:0] Reserved. The pins are
reserved for Test and Miscellaneous
functions)
HSYNC
Pulse.
Horizontal
This is
Synchronization
the horizontal
24/47
Issue 1.6
PIN DESCRIPTION
Table 3-3. Pinout.
Pin #
U23
Pin name
MD[15]
Pin #
F24
Pin name
PCI_CLKI
PCI_CLKO
AD[0]
Pin #
AF3
Pin name
U24
R26
P25
P26
N25
N26
M25
M26
M24
M23
L24
MD[16]
MD[17]
MD[18]
MD[19]
MD[20]
MD[21]
MD[22]
MD[23]
MD[24]
MD[25]
MD[26]
MD[27]
MD[28]
MD[29]
MD[30]
MD[31]
MD[32]
MD[33]
MD[34]
MD[35]
MD[36]
MD[37]
MD[38]
MD[39]
MD[40]
MD[41]
MD[42]
MD[43]
MD[44]
MD[45]
MD[46]
MD[47]
MD[48]
MD[49]
MD[50]
MD[51]
MD[52]
MD[53]
MD[54]
MD[55]
MD[56]
MD[57]
MD[58]
MD[59]
MD[60]
MD[61]
MD[62]
MD[63]
D25
A20
C20
B19
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
B15
A15
C16
D15
A14
C15
B13
D13
A13
C14
C13
A12
B11
C12
A11
D12
B10
C11
A10
D10
C10
A9
PWGD
XTALI
AF15
AE16
G23
AD[1]
XTALO
HCLK
AD[2]
AD[3]
F25
DEV_CLK
GCLK2X
DCLK
AD[4]
AC5
AD[5]
AD5
AD[6]
AF5
DCLK_DIR
MA[0]
AD[7]
AD15
AF16
AC15
AE17
AD16
AF17
AC17
AE18
AD17
AF18
AE19
AF19
AD18
AE20
AC19
AF20
AE21
AC20
AF21
AD20
AE22
AF22
AD21
AE23
AC22
AF23
AE24
AF24
AD25
AC25
AC26
AB24
AA25
AA24
Y25
AD[8]
MA[1]
AD[9]
MA[2]
J25
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
CBE[0]
CBE[1]
CBE[2]
CBE[3]
FRAME#
TRDY#
IRDY#
MA[3]
J26
MA[4]
H26
G25
G26
AD22
AD23
AE26
AD26
AC24
AB25
AB26
Y23
AA26
Y26
W25
W26
V25
U25
U26
T25
MA[5]
MA[6]
MA[7]
MA[8]
MA[9]
MA[10]
MA[11]
RAS#[0]
RAS#[1]
RAS#[2]
RAS#[3]
CAS#[0]
CAS#[1]
CAS#[2]
CAS#[3]
CAS#[4]
CAS#[5]
CAS#[6]
CAS#[7]
MWE#
MD[0]
R25
T24
R23
R24
N23
P24
N24
L25
MD[1]
MD[2]
B8
MD[3]
A8
MD[4]
B7
MD[5]
D8
MD[6]
L26
A7
STOP#
DEVSEL#
PAR
MD[7]
K25
K26
K24
H25
J24
C8
MD[8]
B6
MD[9]
D7
SERR#
LOCK#
PCI_REQ#[0]
PCI_REQ#[1]
PCI_REQ#[2]
Y24
MD[10]
MD[11]
MD[12]
MD[13]
MD[14]
A6
V23
C21
A21
B20
W24
H23
H24
V26
V24
25/47
Issue 1.6
PIN DESCRIPTION
Pin #
C22
Pin name
Pin #
U3
Pin name
SD[10]
Pin #
AE6
Pin name
PCI_GNT#[0]
PCI_GNT#[1]
PCI_GNT#[2]
PCI_INT[0]
PCI_INT[1]
PCI_INT[2]
PCI_INT[3]
RED
B21
D20
D24
C26
A25
B24
V1
SD[11]
AD6
AF6
AE9
AF9
AD7
AE8
AC9
AF8
AD8
GREEN
W2
SD[12]
BLUE
W1
SD[13]
VSYNC
V3
SD[14]
HSYNC
Y2
SD[15]
VREF_DAC
RSET
AE4
AD4
AE5
C6
SYSRSTO#
ISA_CLK
ISA_CLK2X
OSC14M
ALE
COMP
F2
G4
F3
F1
G2
G3
H2
J4
LA[17]/DA[0]
LA[18]/DA[1]
LA[19]/DA[2]
LA[20]/PCS1#
LA[21]/PCS3#
LA[22]/SCS1#
LA[23]/SCS3#
SA[0]
DDC[1] / SCL
DDC[0] / SDA
W3
AA2
Y4
BHE#
AD14
AE13
AC12
AD12
AE14
AC14
AF14
AD13
AE15
VIDEO_CLK
VIDEO_D[0]
VIDEO_D[1]
VIDEO_D[2]
VIDEO_D[3]
VIDEO_D[4]
VIDEO_D[5]
VIDEO_D[6]
VIDEO_D[7]
MEMR#
MEMW#
SMEMR#
SMEMW#
IOR#
AA1
Y3
AB2
AA3
AC2
AB4
AC1
AB3
AD2
AC3
AD1
AF2
AE3
Y1
H1
H3
J2
SA[1]
SA[2]
IOW#
SA[3]
MASTER#
MCS16#
IOCS16#
REF#
J1
SA[4]
K2
J3
SA[5]
SA[6]
AF10
AC10
AE11
AD10
AF11
AE12
AF12
AD11
AE10
AD9
VTV_YUV[0]
VTV_YUV[1]
VTV_YUV[2]
VTV_YUV[3]
VTV_YUV[4]
VTV_YUV[5]
VTV_YUV[6]
VTV_YUV[7]
VTV_HSYNC
VTV_BT#
K1
K4
L2
SA[7]
AEN
SA[8]/DD[0]
SA[9]/DD[1]
SA[10]/DD[2]
SA[11]/DD[3]
SA[12] / DD[4]
SA[13] / DD[5]
SA[14] / DD[6]
SA[15] / DD[7]
SA[16] / DD[8]
SA[17] / DD[9]
SA[18] / DD[10]
SA[19] / DD[11]
RTCDS / DD[12]
RTCRW# / DD[13]
KBCS# / DD[14]
RMRTCCS# / DD[15]
SD[0]
IOCHCK#
ISAOE#
GPIOCS#
IOCHRDY
K3
L1
M2
M1
L3
B1
C2
C1
D2
D3
D1
E2
E4
E3
E1
PIRQ
SIRQ
N2
M4
N1
M3
P4
P3
R2
N3
P1
R1
T2
R3
T1
R4
U2
T3
U1
U4
V2
PDRQ
SDRQ
PDACK#
SDACK#
PIOR#
PIOW#
SIOR#
SIOW#
B4
D5
A4
C5
B3
C4
A3
C7
B5
A5
ST[0]
ST[1]
ST[2]
ST[3]
ST[4]
ST[5]
ST[6]
E23
D26
E24
C25
A24
B23
C23
A23
B22
D22
IRQ_MUX[0]
IRQ_MUX[1]
IRQ_MUX[2]
IRQ_MUX[3]
DREQ_MUX[0]
DREQ_MUX[1]
DACK_ENC[0]
DACK_ENC[1]
DACK_ENC[2]
TC
CLKDEL[0]
CLKDEL[1]
CLKDEL[2]
SD[1]
SD[2]
SD[3]
SD[4]
AC7
AF4
W4
VDD_DAC1
SD[5]
VDD_DAC2
SD[6]
VDD_GCLK_PLL
VDD_DCLK_PLL
VDD_HCLK_PLL
VDD_DEVCLK_PLL
SD[7]
AB1
F26
G24
SD[8]
SD[9]
26/47
Issue 1.6
PIN DESCRIPTION
Pin #
A16
Pin name
Pin #
M11:16
N4
Pin name
VDD5
VDD5
VDD5
VDD5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B12
B9
N11:16
P11:16
P23
D18
A22
B14
C9
R11:16
T11:16
V4
D6
D11
D16
D21
F4
W23
AC4
AC8
AC13
AC18
AC23
AD3
F23
G1
K23
L4
AD24
AE1:2
AE25
AF1
L23
P2
T4
T23
T26
AA4
AA23
AB23
AC6
AC11
AC16
AC21
AD19
AF13
AF25
AF26
AE7
AF7
E25
E26
A1:2
A26
B2
VSS_DAC1
VSS_DAC2
VSS_DLL
VSS_DLL
VSS
VSS
VSS
B25:26
C3
VSS
VSS
C24
D4
VSS
VSS
D9
VSS
D14
D19
D23
H4
VSS
VSS
VSS
VSS
J23
VSS
L11:16
VSS
27/47
Issue 1.6
ELECTRICAL SPECIFICATIONS
4. ELECTRICAL SPECIFICATIONS
4.1 INTRODUCTION
The electrical specifications in this chapter are val-
id for the STPC Client.
4.2 ELECTRICAL CONNECTIONS
4.2.1 POWER/GROUND CONNECTIONS/
DECOUPLING
be connected either to VDD or to VSS. Connect
active-high inputs to VDD through a 20 kWW
(±10%) pull-down resistor and active-low inputs to
VSS and connect active-low inputs to VCC
through a 20 kWW (±10%) pull-up resistor to pre-
vent spurious operation.
Due to the high frequency of operation of the
STPC Client, it is necessary to install and test this
device using standard high frequency techniques.
The high clock frequencies used in the STPC Cli-
ent and its output buffer circuits can cause tran-
sient power surges when several output buffers
switch output levels simultaneously. These effects
can be minimized by filtering the DC power leads
with low-inductance decoupling capacitors, using
low impedance wiring, and by utilizing all of the
VSS and VDD pins.
4.2.3 RESERVED DESIGNATED PINS
Pins designated reserved should be left discon-
nected. Connecting a reserved pin to a pull-up re-
sistor, pull-down resistor, or an active signal could
cause unexpected results and possible circuit
malfunctions.
4.2.2 UNUSED INPUT PINS
All inputs not used by the designer and not listed
in the table of pin connections in Chapter 3 should
4.3 ABSOLUTE MAXIMUM RATINGS
The following table lists the absolute maximum
ratings for the STPC Client device. Stresses be-
yond those listed under Table 4-1 limits may
cause permanent damage to the device. These
are stress ratings only and do not imply that oper-
ation under any conditions other than those spec-
ified in section ”Operating Conditions”.
Exposure to conditions beyond Table 4-1 may (1)
reduce device reliability and (2) result in prema-
ture failure even when there is no immediately ap-
parent sign of failure. Prolonged exposure to con-
ditions at or near the absolute maximum ratings
(Table 4-1) may also result in reduced useful life
and reliability.
Table 4-1. Absolute Maximum Ratings
Symbol
Parameter
Value
-0.3, 4.0
Units
V
V
DC Supply Voltage
DDx
V , V
Digital Input and Output Voltage
Storage Temperature
-0.3, VDD + 0.3
-40, +150
-40, +100
4.8
V
I
O
T
°C
°C
W
STG
T
Operating Case Temperature (Note 1)
Total Power Dissipation
CASE
P
TOT
Note 1 : -40°C limit of T
(extended temperature
range) is given a s a preliminary specification and so as
CASE
all the -40°C related data.
28/47
Issue 1.6
ELECTRICAL SPECIFICATIONS
4.4 DC CHARACTERISTICS
Table 4-2. DC Characteristics
Recommended Operating conditions : VDD = 3.3V ±0.3V, Tcase = 0 to 100°C (Commercial Range) or -40 to
100°C (Industrial Range) unless otherwise specified
Symbol
Parameter
Operating Voltage
Supply Power
Test conditions
Min
Typ
3.3
3.2
Max
3.6
Unit
V
V
P
3.0
DD
DD
V
= 3.3V, H = 66Mhz
3.9
W
MHz
V
DD
CLK
H
Internal Clock
(Note 1)
75
CLK
V
DAC Voltage Reference
Output Low Voltage
Output High Voltage
Input Low Voltage
1.215
1.235
1.255
0.5
REF
V
I
=1.5 to 8mA depending of the pin
=-0.5 to -8mA depending of thepin
Load
V
OL
Load
V
I
2.4
-0.3
-0.3
2.1
V
OH
V
Except XTALI
XTALI
0.8
0.9
V
IL
V
V
Input High Voltage
Except XTALI
XTALI
V
V
+0.3
V
IH
DD
2.35
-5
+0.3
V
DD
I
Input Leakage Current
Input Capacitance
Output Capacitance
Clock Capacitance
Input, I/O
(Note 2)
5
µA
pF
pF
pF
LK
C
IN
C
(Note 2)
OUT
C
(Note 2)
CLK
Notes:
1. MHz ratings refer to CPU clock frequency.
2. Not 100% tested.
4.5 AC CHARACTERISTICS
Table 4-4 through Table 4-8 list the AC character-
istics including output delays, input setup require-
ments, input hold requirements and output float
delays. These measurements are based on the
measurement points identified in Figure 4-1 and
Figure 4-2. The rising clock edge reference level
VREF , and other reference levels are shown in
Table 4-3 below for the STPC Client. Input or out-
put signals must cross these levels during testing.
Figure 4-1 shows output delay (A and B) and input
setup and hold times (C and D). Input setup and
hold times (C and D) are specified minimums, de-
fining the smallest acceptable sampling window a
synchronous input signal must be stable for cor-
rect operation.
Table 4-3. Drive Level and Measurement Points for Switching Characteristics
Symbol
Value
1.5
Units
V
V
V
V
REF
V
3.0
IHD
V
0.0
ILD
Note: Refer to Figure 4-1.
29/47
Issue 1.6
ELECTRICAL SPECIFICATIONS
Figure 4-1 Drive Level and Measurement Points for Switching Characteristics
Tx
V
V
IHD
CLK:
Ref
ILD
V
A
MAX
B
MIN
Valid
Output n
Valid
Output n+1
V
OUTPUTS:
Ref
C
D
V
V
IHD
Valid
Input
INPUTS:
LEGEND:
Ref
ILD
V
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
Figure 4-2 CLK Timing Measurement Points
T1
T2
V
IH (MIN)
V
V
Ref
IL (MAX)
CLK
T5
T3
T4
30/47
Issue 1.6
ELECTRICAL SPECIFICATIONS
Table 4-4. PCI Bus AC Timing
Name
t1
Parameter
Min
2
Max
13
11
12
12
13
11
14
11
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCI_CLKI to AD[31:0] valid
PCI_CLKI to FRAME# valid
PCI_CLKI to CBE#[3:0] valid
PCI_CLKI to PAR valid
t2
2
t3
2
t4
2
t5
PCI_CLKI to TRDY# valid
PCI_CLKI to IRDY# valid
2
T6
T7
T8
T9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
2
PCI_CLKI to STOP# valid
PCI_CLKI to DEVSEL# valid
PCI_CLKI to PCI_GNT# valid
AD[31:0] bus setup to PCI_CLKI
AD[31:0] bus hold from PCI_CLKI
PCI_REQ#[2:0] setup to PCI_CLKI
PCI_REQ#[2:0] hold from PCI_CLKI
CBE#[3:0] setup to PCI_CLKI
CBE#[3:0] hold to PCI_CLKI
IRDY# setup to PCI_CLKI
IRDY# hold to PCI_CLKI
2
2
2
7
3
10
1
7
5
7
4
FRAME# setup to PCI_CLKI
FRAME# hold from PCI_CLKI
7
3
Table 4-5. DRAM Bus AC Timing
Name
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
Parameter
Min
Max
17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HCLK to RAS#[3:0] valid
HCLK to CAS#[7:0] bus valid
HCLK to MA[11:0] bus valid
HCLK to MWE# valid
17
17
17
HCLK to MD[63:0] bus valid
MD[63:0] Generic setup
GCLK2X to RAS#[3:0] valid
GCLK2X to CAS#[7:0] valid
GCLK2X to MA[11:0] bus valid
GCLK2X to MWE# valid
GCLK2X to MD[63:0] bus valid
MD[63:0] Generic hold
25
7
17
17
17
17
23
0
Table 4-6. Video Input/TV Output AC Timing
Name
t34
Parameter
Min
Max
Unit
ns
DCLK to TV_YUV[7:0] bus valid
VIDEO_D[7:0] setup to VCLK
VIDEO_D[7:0] hold from VCLK
VCLK to VTV_BT# valid
VCLK to VTV_HSYNC valid
VTV_BT# setup to VCLK
VTV_BT# hold from VCLK
18
t35
5
3
ns
t36
ns
t37
21
21
ns
t38
ns
t39
10
5
ns
t40
ns
31/47
Issue 1.6
ELECTRICAL SPECIFICATIONS
Table 4-6. Video Input/TV Output AC Timing
t41
t42
VTV_HSYNC setup to VCLK
VTV_HSYNC hold from VCLK
10
5
ns
ns
Table 4-7. Graphics Adapter (VGA) AC Timing
Name
t43
Parameter
Min
Min
Max
45
Unit
ns
DCLK to VSYNC valid
DCLK to HSYNC valid
t44
45
ns
Table 4-8. ISA Bus AC Timing
Name
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
Parameter
Max
60
60
62
35
28
60
62
50
50
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XTALO to LA[23:17] bus active
XTALO to SA[19:0] bus active
XTALO to BHE# valid
XTALO to SD[15:0] bus active
PCI_CLKI to ISAOE# valid
XTALO to GPIOCS# valid
XTALO to ALE valid
XTALO to MEMW# valid
XTALO to MEMR# valid
XTALO to SMEMW# valid
XTALO to SMEMR# valid
XTALO to IOR# valid
XTALO to IOW# valid
32/47
Issue 1.6
MECHANICAL DATA
5. MECHANICAL DATA
5.1 388-PIN PACKAGE DIMENSION
The pin numbering for the STPC 388-pin Plastic
BGA package is shown in Figure 5-1.
Dimensions are shown in Figure 5-2, Table 5-1
and Figure 5-3, Table 5-2.
Figure 5-1. 388-Pin PBGA Package - Top View
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
A
A
B
B
C
C
D
D
E
E
F
F
G
H
G
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
33/47
Issue 1.6
MECHANICAL DATA
Figure 5-2. 388-pin PBGA Package - PCB Dimensions
A1 Ball Pad Corner
A
B
A
D
E
F
Detail
G
C
Table 5-1. 388-pin PBGA Package - PCB Dimensions
mm
inches
Typ
Symbols
Min
34.95
1.22
0.58
1.57
0.15
0.05
0.75
Typ
35.00
1.27
0.63
1.62
0.20
0.10
0.80
Max
35.05
1.32
0.68
1.67
0.25
0.15
0.85
Min
Max
A
B
C
D
E
F
1.375
0.048
0.023
0.062
0.006
0.002
0.030
1.378
0.050
0.025
0.064
0.008
0.004
0.032
1.380
0.052
0.027
0.066
0.001
0.006
0.034
G
34/47
Issue 1.6
MECHANICAL DATA
Figure 5-3. 388-pin PBGA Package - Dimensions
C
F
D
E
Solderball
Solderball after collapse
B
G
A
Table 5-2. 388-pin PBGA Package - Dimensions
mm
inches
Symbols
Min
0.50
1.12
0.60
0.52
0.63
0.60
Typ
0.56
1.17
0.76
0.53
0.78
0.63
30.0
Max
0.62
1.22
0.92
0.54
0.93
0.66
Min
Typ
Max
A
B
C
D
E
F
0.020
0.044
0.024
0.020
0.025
0.024
0.022
0.046
0.030
0.021
0.031
0.025
11.8
0.024
0.048
0.036
0.022
0.037
0.026
G
35/47
Issue 1.6
MECHANICAL DATA
5.2 388-PIN PACKAGE THERMAL DATA
388-pin PBGA package has a Power Dissipation
Capability of 4.5W which increases to 6W when
used with a Heatsink.
Structure in shown in Figure 5-4.
Thermal dissipation options are illustrated in Fig-
ure 5-5 and Figure 5-6.
Figure 5-4. 388-Pin PBGA structure
Signal layers
Power & Ground layers
Thermal balls
Figure 5-5. Thermal dissipation without heatsink
Board
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Ambient
Case
Junction
Rca
Rjc
6
6
The PBGA is centered on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
Board
8.5
Case
125
Junction
Board
Rjb
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Ambient
Rba
Ambient
Airflow = 0
Rja = 13 °C/W
Board temperature taken at the center balls
36/47
Issue 1.6
MECHANICAL DATA
Figure 5-6. Thermal dissipation with heatsink
Board
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Ambient
Case
Junction
Rca
Rjc
The PBGA is centered on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
3
6
Board
8.5
Case
50
Junction
Board
Rjb
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Ambient
Rba
Airflow = 0
Ambient
Board temperature taken at the center balls
Heat sink is 11.1°C/W
Rja = 9.5 °C/W
37/47
Issue 1.6
MECHANICAL DATA
38/47
Issue 1.6
BOARD LAYOUT
6. BOARD LAYOUT
6.1 THERMAL DISSIPATION
Thermal dissipation of the STPC depends mainly
on supply voltage. As a result, when the system
does not need to work at 3.3V, it may be to reduce
the voltage to 3.15V for example. This may save
few 100’s of mW.
With such configuration the Plastic BGA 388 pack-
age dissipates 90% of the heat through theground
balls, and especially the central thermal balls
which are directly connected to the die, the re-
maining 10% is dissipated through the case. Add-
ing a heat sink reduces this value to 85%.
The second area that can be concidered is un-
used interfaces and functions. Depending on the
application, some input signals can be grounded,
and some blocks not powered or shutdown. Clock
speed dynamic adjustment is also a solution that
can be used along with the integrated power man-
agement unit.
As a result, some basic rules have to be applied
when routing the STPC in order to avoid thermal
problems.
First of all, the whole ground layer acts as a heat
sink and ground balls must be directly connected
to it as illustrated in Figure 6-1.
The standard way to route thermal balls to internal
ground layer implements only one via pad for each
ball pad, connected using a 8-mil wire.
If one ground layer is not enough, a second
ground plane may be added on the solder side.
Figure 6-1. Ground routing
Pad for ground ball
Thru hole to ground layer
Note: For better visibility, ground balls are not all routed.
39/47
Issue 1.6
BOARD LAYOUT
When considering thermal dissipation, the most
important - and not the more obvious - part of the
layout is the connection between the ground balls
and the ground layer.
To avoid solder wicking over to the via pads during
soldering, it is important to have a solder mask of
4 mil around the pad (NSMD pad), this gives a di-
ameter of 33 mil for a 25 mil ground pad.
A 1-wire connection is shown in Figure 6-2. The
use of a 8-mil wire results in a thermal resistance
of 105°C/W assuming copper is used (418 W/
m.°K). This high value is due to the thickness (34
µm) of the copper on the external side of the PCB.
To obtain the optimum ground layout, place the
vias directly under the ball pads. In this case no lo-
cal boar d distortion is tolerated.
The thickness of the copper on PCB layers is typ-
ically 34 µm for external layers and 17 µm for inter-
nal layers. This means thermal dissipation is not
good and temperature of the board is concentrat-
ed around the devices and falls quickly with in-
creased distance.
Considering only the central matrix of 36 thermal
balls and one via for each ball, the global thermal
resistance is 2.9°C/W. This can be easily im-
proved by using four 10 mil wires to connect to the
four vias around the ground pad link as in Figure
6-3. This gives a total of 49 vias and a global re-
sistance for the 36 thermal balls of 0.6°C/W.
When it is possible to place a metal layer inside
the PCB, this improves dramatically the heat
spreading and hence thermal dissipation of the
board.
The use of a ground plane like in Figure 6-4 is
even better.
Figure 6-2. Recommended 1-wire ground pad layout
Pad for ground ball (diameter = 25 mil)
Solder Mask (4 mil)
Connection Wire (width = 10 mil)
Via (diameter = 24 mil)
Hole to ground layer (diameter = 12 mil)
1 mil = 0.0254 mm
Figure 6-3. Recommended 4-wire ground pad layout
4 via pads for each ground ball
40/47
Issue 1.6
BOARD LAYOUT
Figure 6-4. Optimum layout for central ground ball
Clearance = 6mil
External diameter = 37 mil
Via to Ground layer
hole diameter = 14 mil
Solder mask
diameter = 33 mil
Pad for ground ball
diameter = 25 mil
connections = 10 mil
The PBGA Package also dissipates heat through
peripheral ground balls. When a heat sink is
placed on the device, heat is more uniformely
spread throughout the moulding increasing heat
dissipation through the peripheral ground balls.
The more via pads are connected to each ground
ball, the more heat is dissipated . The only limita-
tion is the risk of lossing routing channels.
Figure 6-5 shows a routing with a good trade off
between thermal dissipation and number of rout-
ing channels.
Figure 6-5. Global ground layout for good thermal dissipation
Via to ground layer
Ground pad
41/47
Issue 1.6
BOARD LAYOUT
Figure 6-6. Bottom side layout and decoupling
Ground plane for thermal dissipation
Via to ground layer
A local ground plane on opposite side of the board
as shown in Figure 6-6 improves thermal dissipa-
tion. It is used to connect decoupling capacitances
but can also be used for connection to a heat sink
or to the system’s metal box for better dissipation.
This possibility of using the whole system’s box for
thermal dissipation is very usefull in case of high
temperature inside the system and low tempera-
ture outside. In that case, both sides of the PBGA
should be thermally connected to the metal chas-
sis in order to propagate the heat through the met-
al. Figure 6-7 illustrates such an implementation.
Figure 6-7. Use of metal plate for thermal dissipation
Die
Board
Metal planes
Thermal conductor
42/47
Issue 1.6
BOARD LAYOUT
6.2 HIGH SPEED SIGNALS
Some Interfaces of the STPC run at high speed
and have to be carefully routed or even shielded.
All the clocks have to be routed first and shielded
for speeds of 27MHz or more. The high speed sig-
nals have the same contrainsts as some of the
memory interface control signals.
Here is the list of these interfaces, in decreasing
speed order:
The next interfaces to be routed are Memory, Vid-
eo/graphics, and PCI.
- Memory Interface.
- Graphics and video interfaces
- PCI bus
All the analog noise sensitive signals have to be
routed in a separate area and hence can be rout-
ed indepedently.
- 14MHz oscillator stage
Figure 6-8. Shielding signals
ground ring
shielded signal line
ground pad
ground pad
shielded signal lines
43/47
Issue 1.6
BOARD LAYOUT
44/47
Issue 1.6
ORDERING DATA
7. ORDERING DATA
7.1 ORDERING CODES
ST
PC
D01
66
BT
C
3
STMicroelectronics
Prefix
Product Family
PC: PC Compatible
Product ID
D01: Client
Core Speed
66: 66MHz
75: 75MHz
Package
BT: 388 Overmoulded BGA
Temperature Range
C: Commercial
Case Temperature (Tcase) = 0°C to +100°C
I: Industrial
Case Temperature (Tcase) = -40°C to +100°C
Operating Voltage
3 : 3.3V ± 0.3V
45/47
Issue 1.6
ORDERING DATA
7.2 AVAILABLE PART NUMBERS
Core Frequency
CPU Mode
( DX / DX2 )
Tcase Range
Operating Voltage
( V )
Part Number
( MHz )
( °C )
STPCC0166BTC3
STPCC0175BTC3
STPCC0166BTI3
STPCC0175BTI3
66
DX
DX
DX
DX
0°C to +100°C
75
3.3V ± 0.3V
66
-40°C to +100°C
75
7.3 CUSTOMER SERVICE
More
information is
available
on
the
http://
STMicroelectronics
www.ST.com/STPC.
internet
site
Any specific questions are to be addressed direct-
ly to the local ST Sales Office.
46/47
Release A
Issue 1.6
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
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The ST logo is a registered trademark of STMicroelectronics.
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Issue 1.6
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