STPCC0180BTC3_技术文档

STPC CONSUMER

PC Compatible Embeded Microprocessor

■

POWERFUL X86 PROCESSOR

64-BIT BUS ARCHITECTURE

64-BIT DRAM CONTROLLER

SVGA GRAPHICS CONTROLLER

UMA ARCHITECTURE

VIDEO SCALER

DIGITAL PAL/NTSC ENCODER

VIDEO INPUT PORT

CRT CONTROLLER

135MHz RAMDAC

PBGA388

3 LINE FLICKER FILTER

SCAN CONVERTER

PCI MASTER / SLAVE / ARBITER CTRL

ISA MASTER/SLAVE INTERFACE

IDE CONTROLLER

Figure 1. Logic Diagram

ISABUS

DMA CONTROLLER

x86

Core

INTERRUPT CONTROLLER

TIMER / COUNTERS

ISA

m/s

IPC

Host I/F

POWER MANAGEMENT

EIDE

PCI

m/s

EIDE

STPC CONSUMER OVERVIEW

PCI BUS

The STPC Consumer integrates a standard 5th

generation x86 core, a DRAM controller, a graph-

ics subsystem, a video pipeline and support logic

including PCI, ISA and IDE controllers to provide a

single Consumer orientated PC compatible sub-

system on a single device.

PCI

m/s

CCIRInput

TV Output

VIP

Digital

PAL/

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing the same

memory array between the CPU main memory

and the graphics and video frame buffers.

Extra facilities are implemented to handle video

streams. Features include smooth scaling and

color space conversion of the video input stream

and mixing with graphics data. The chip also in-

cludes a built-in digital TV encoder and anti-flicker

filters that allow stable, high-quality display on

standard PAL or NTSC television sets without ad-

ditional components.

NTSC

AntiFlicker

Color Space

Converter

Video

pipeline

Color

Key

Chroma

Key

Monitor

2D

SVGA

HW Cursor

CRTC

SYNCOutput

DRAM

CTRL

The STPC Consumer is packaged in a 388 Plastic

Ball Grid Array (PBGA).

8/2/00

1/51

Issue 1.2

STPC CONSUMER

■

X86 Processor core

Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

Can access up to 4GBytes of external

memory.

8KByte unified instruction and data cache

with write back and write through capability.

Parallel processing integral floating point unit,

with automatic power down.

Clock core speeds up to of 100 MHz.

Fully static design for dynamic clock control.

Low power and system management modes.

Optimized design for 3.3V operation.

■

VGA Controller

Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

Requires external frequency synthesizer and

reference sources.

8-, 16-, 24-bit pixels.

Interlaced or non-interlaced output.

Video Input port

Accepts video inputs in CCIR 601/656 or

ITU-R 601/656, and stream decoding.

Optional 2:1 decimator

Stores captured video in off setting area of

the onboard frame buffer.

■

Video pass through to the onboard PAL/

NTSC encoder for full screen video images.

HSYNC and B/T generation or lock onto

external video timing source.

■

DRAM Controller

Integrated system memory andgraphic frame

memory.

■

Supports up to 128 MBytes system memory

in 4 banks and down to as little as 2Mbytes.

Supports 4MB, 8MB, 16MB, 32MB single-

sided and double-sided DRAM SIMMs.

Four quad-word write buffers for CPU to

DRAM and PCI to DRAM cycles.

Four 4-word read buffers for PCI masters.

Supports Fast Page Mode & EDO DRAM.

Programmable timing for DRAM parameters

including CAS pulse width, CAS pre-charge

time and RAS to CAS delay.

■

Video Pipeline

Two-tap interpolative horizontal filter.

Two-tap interpolative vertical filter.

Color space conversion (RGB to YUV and

YUV to RGB).

Programmable window size.

Chroma and color keying for integrated video

overlay.

Programmable two tap filter with gamma

correction or three tap flicker filter.

Progressive to interlaced scan converter.

■

60, 70, 80 & 100ns DRAM speeds.

Memory hole between 1 MByte & 8 MByte

supported for PCI/ISA busses.

■

Digital NTSC/PAL encoder

NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy

programmable video outputs.

■

Hidden refresh.

■

CCIR601 encoding with programmable color

subcarrier frequencies.

Line skip/insert capability

Interlaced or non-interlaced operation mode.

625 lines/50Hz or 525 lines/60Hz 8 bit

multiplexed CB-Y-CR digital input.

CVBS and R,G,B simultaneous analog

outputs through 10-bit DACs.

To check if your memory device is supported by

the STPC, please refer to Table 9-3 in the

Programming Manual.

■

Graphics Engine

64-bit windows accelerator.

Backward compatibility to SVGA standards.

Hardware acceleration for text, bitblts,

transparent blts and fills.

■

Cross color reduction by specific trap filtering

on luma within CVBS flow.

Power down mode available on each DAC.

■

Up to 64 x 64 bit graphics hardware cursor.

Up to 4MB long linear frame buffer.

8-, 16-, and 24-bit pixels.

Drivers for Windows and other operating

systems.

2/51

Issue 1.2

STPC CONSUMER

■

PCI Controller

■

Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

Support for PIO mode 3 & 4.

Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

Individual drive timing for all four IDE devices

Supports both legacy & native IDE modes

Supports hard drives larger than 528MB

Support for CD-ROM and tape peripherals

Backward compatibility with IDE (ATA-1).

Drivers for Windows and other Operating

Systems

Fully compliant with PCI 2.1 specification.

Integrated PCI arbitration interface. Up to 3

masters can connect directly. External PAL

allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to

PCI.

■

Support forburst read/write from PCI master.

0.33X and 0.5X CPU clock PCI clock.

■

ISA master/slave Interface

Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

Supports programmable extra wait state for

ISA cycles

Supports I/O recovery time for back to back

I/O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

Supports flash ROM.

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host bus.

NSP compliant.

■

Integrated peripheral controller

2X8237/AT compatible 7-channel DMA

controller.

2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

■

Power Management

Four power saving modes: On, Doze,

Standby, Suspend.

Programmable system activity detector

Supports SMM and APM.

Supports STOPCLK.

■

Supports IO trap & restart.

■

IDE Interface

Supports PIO

Supports up to Mode 5 Timings

Transfer Rates to 22 MBytes/sec

Supports up to 4 IDE devices

Independent peripheral time-out timer to

monitor hard disk, serial & parallel ports.

Supports RTC, interrupts and DMAs wake-up

■

3/51

Issue 1.2

STPC CONSUMER

4/51

Issue 1.2

UPDATE HISTORY FOR OVERVIEW.

0.1 UPDATE HISTORY FOR OVERVIEW.

The following changes have been made to the Electrical Specification Chapter on the 02/02/2000.

Section

Change

Added

Text

To check if your memory device is supported by the STPC, please refer to

Table 9-3 Host Address to MA Bus Mappingin the Programming Manual.

5/51

Issue 1.2

GENERAL DESCRIPTION

1. GENERAL DESCRIPTION

At the heart of the STPC Consumer is an ad-

vanced processor block, dubbed the 5ST86. The

5ST86 includes a powerful x86 processor core

along with a 64-bit DRAM controller, advanced

64bit accelerated graphics and video controller, a

high speed PCI local-bus controller and Industry

standard PC chip set functions (Interrupt control-

ler, DMA Controller, Interval timer and ISA bus)

and EIDE controller.

The ‘standard’ PC chipset functions (DMA, inter-

rupt controller, timers, power management logic)

are integrated with the x86 processor core.

The PCI bus is the main data communication link

to the STPC Consumer chip. The STPC Consum-

er translates appropriate host bus I/O and Memory

cycles onto the PCI bus. It also supports the gen-

eration of Configuration cycles on the PCI bus.

The STPC Consumer, as a PCI bus agent (host

bridge class), fully complies with PCI specification

2.1. The chip-set also implements the PCI manda-

tory header registers in Type 0 PCI configuration

space for easy porting of PCI aware system BI-

OS. The device contains a PCI arbitration function

for three external PCI devices.

The STPC Consumer has in addition to the

5ST86, a Video subsystem and high quality digital

Television output.

The STMicroelectronics x86 processor core is em-

bedded with standard and application specific pe-

ripheral modules on the same silicon die. The core

has all the functionality of the STMicroelectronics

standard x86 processor products, including the

low power System Management Mode (SMM).

The STPC Consumer integrates an ISA bus con-

troller. Peripheral modules such as parallel and

serial communications ports, keyboard controllers

and additional ISA devices can be accessed by

the STPC Consumer chip set through this bus.

System Management Mode (SMM) provides an

additional interrupt and address space that can be

used for system power management or software

transparent emulation of peripherals. While run-

ning in isolated SMM address space, the SMM in-

terrupt routine can execute without interfering with

the operating system or application programs.

An industry standard EIDE (ATA 2) controller is

built in to the STPC Consumer and connected in-

ternally via the PCI bus.

Graphics functions are controlled by the on-chip

SVGA controller and the monitor display is man-

aged by the 2D graphics display engine.

Further power management facilities include a

suspend mode that can be initiated from either

hardware or software. Because of the static nature

of the core, no internal data is lost.

This Graphics Engine is tuned to work with the

host CPU to provide a balanced graphics system

with a low silicon area cost. It performs limited

graphics drawing operations, which include hard-

ware acceleration of text, bitblts, transparent blts

and fills. These operations can act on off-screen

or on-screen areas. The frame buffer size ranges

up to 4 Mbytes anywhere in the physical main

memory.

The STPC Consumer makes use of a tightly cou-

pled Unified Memory Architecture (UMA), where

the same memory array is used for CPU main

memory and graphics frame-buffer. This signifi-

cantly reduces total system memory with system

performances equal to that of a comparable solu-

tion with separate frame buffer and system mem-

ory. In addition, memory bandwidth is improved by

attaching the graphics engine directly to the 64-bit

processor host interface running at the speed of

the processor bus rather than the traditional PCI

bus.

The graphics resolution supported is a maximum

of 1280x1024 in 65536 colours at 75Hz refresh

rate and is VGA and SVGA compatible. Horizontal

timing fields are VGA compatible while the vertical

fields are extended by one bit to accommodate the

above display resolution.

The 64-bit wide memory array provides the sys-

tem with 320MB/s peak bandwidth, double that of

an equivalent system using 32 bits. This allows for

higher screen resolutions and greater color depth.

The processor bus runs at the speed of the proc-

essor (DX devices) or half the speed (DX2 devic-

es).

STPC Consumer provides several additional func-

tions to handle MPEG or similar video streams.

The Video Input Port accepts an encoded digital

video stream in one of a number of industry stand-

ard formats, decodes it, optionally decimates it by

a factor of 2:1, and deposits it into an off screen

area of the frame buffer. An interrupt request can

be generated when an entire field or frame has

been captured.

6/51

Issue 1.2

GENERAL DESCRIPTION

The video output pipeline incorporates a video-

scaler and color space converter function and pro-

visions in the CRT controller to display a video

window. While repainting the screen the CRT con-

troller fetches both the video as well as the normal

non-video frame buffer in two separate internal

FIFOs (256-Bytes each). The video stream can be

color-space converted (optionally) and smooth

scaled. Smooth interpolative scaling in both hori-

zontal and vertical directions are implemented.

Color and Chroma key functions are also imple-

mented to allow mixing video stream with non-vid-

eo frame buffer.

- House-keeping timer to cope with short bursts of

house-keeping activity while dozing or in stand-by

state.

- Peripheral activity detection.

- Peripheral timer detecting peripheral inactivity

- SUSP# modulation to adjust the system perform-

ance in various power down states of the system

including full power on state.

- Power control outputs to disable power from dif-

ferent planes of the board.

Lack of system activity for progressively longer

period of times is detected by the three power

down timers. These timers can generate SMI in-

terrupts to CPU so that the SMM software can put

the system in decreasing states of power con-

sumption. Alternatively, system activity in a power

down state can generate SMI interrupt to allow the

software to bring the system back up to full power

on state. The chip-set supports up to three power

down states: Doze state, Stand-by state and Sus-

pend mode. These correspond to decreasing lev-

els of power savings.

The video output passes directly to the RAMDAC

for monitor output or through another optional

color space converter (RGB to 4:2:2 YCrCb) to the

programmable anti-flicker filter. The flicker filter is

configured as either a two line filter with gamma

correction (primarily designed for DOS type text)

or a 3 line flicker filter (primarily designed for Win-

dows type displays). The flicker filter is optional

and can be software disabled for use with video on

large screen areas.

The Video output pipeline of the STPC Consumer

interfaces directly to the internal digital TV encod-

er. It takes a 24 bit RGB non-interlaced pixel

stream and converts to a multiplexed 4:2:2 YCrCb

8 bit output stream, the logic includes a progres-

sive to interlaced scan converter and logic to in-

sert appropriate CCIR656 timing reference codes

into the output stream. It facilitates the high quality

display of VGA or full screen video streams re-

ceived via the Video input port to standard NTSC

or PAL televisions.

Power down puts the STPC Consumer into sus-

pend mode. The processor completes execution

of the current instruction, any pending decoded in-

structions and associated bus cycles. During the

suspend mode, internal clocks are stopped. Re-

moving power down, the processor resumes in-

struction fetching and begins execution in the in-

struction stream at the point it had stopped.

A reference design for the STPC Consumer is

available including the schematics and layout

files, the design is a PC ATX motherboard design.

The design is available as a demonstration board

for application and system development.

The STPC Consumer core is compliant with the

Advanced Power Management (APM) specifica-

tion to provide a standard method by which the

BIOS can control the power used by personal

computers. The Power Management Unit module

(PMU) controls the power consumption by provid-

ing a comprehensive set of features that control

the power usage and supports compliance with

the United States Environmental Protection Agen-

cy’s Energy Star Computer Program. The PMU

provides following hardware structures to assist

the software in managing the power consumption

by the system.

The STPC Consumer is supported by several

BIOS vendors, including the super I/O device

used in the reference design. Drivers for 2D accel-

erator, video features and EIDE are availaible on

various operating systems.

The STPC Consumer has been designed using

modern reusable modular design techniques, it is

possible to add or remove the standard features of

the STPC Consumer or other variants of the

5ST86 family. Contact your local STMicroelecton-

ics sales office for further information.

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

- Doze timer (short durations).

- Stand-by timer (medium durations).

- Suspend timer (long durations).

- House-keeping activity detection.

7/51

Issue 1.2

GENERAL DESCRIPTION

Figure 1-1 Functionnal description

x86

Core

ISA BUS

Host I/F

ISA

IPC

EIDE

PCI m/s

PCI BUS

PCI m/s

CCIR Input

VIP

TV Output

Digital

PAL/

Anti-Flicker

Color Space

Video

pipeline

Color

Key

Monitor

2D

SVGA

Chroma

HW Cursor

CRTC

SYNC Output

DRAM

8/51

Issue 1.2

GENERAL DESCRIPTION

Figure 1-2 Typical Application

Keyboard / Mouse

Serial Ports

Parallel Port

Floppy

Super I/O

RTC

Flash

2x EIDE

ISA

DMUX

MUX

IRQ

Monitor

SVGA

DMA.REQ

TV

S-VHS

RGB

PAL

STPC Consumer

DMA.ACK

NTSC

DMUX

Video

CCIR601

CCIR656

PCI

4x 16-bit EDO DRAMs

9/51

Issue 1.2

PIN DESCRIPTION

2. PIN DESCRIPTION

2.1 INTRODUCTION

The STPC Consumer integrates most of the func-

tionalities of the PC architecture. As aresult, many

of the traditional interconnections between the

host PC microprocessor and the peripheral devic-

es are totally internal to the STPC Consumer. This

offers improved performance due to the tight cou-

pling of the processor core and these peripherals.

As a result many of the external pin connections

are made directly to the on-chip peripheral func-

tions.

Table 2-1. Signal Description

Group name

Basic Clocks reset & Xtal(SYS)

DRAM Controller

Qty

12

89

58

88

9

PCI interface (PCI)

ISA / IDE / IPC combined interface

Video Input (VIP)

TV Output

10

69

26

12

5

VGA Monitor interface

Grounds

Figure 2-1 shows the STPC Consumer’s external

interfaces. It defines the main busses and their

function. Table 2-1 describes the physical imple-

mentation listing signal types and their functional-

ities. Table 2-2 provides a full pin listing and de-

scription. Table 2-3 provides a full listing of the

STPC Consumer pin locations of package by

physical connection. Please refer to the pin alloca-

tion drawing for reference.

V

DD

Analog specific V /V

CC DD

Reserved

Total Pin Count

388

Note: Several interface pins are multiplexed with

other functions, refer to the Pin Description sec-

tion for further details

Figure 2-1. STPC Consumer External Interfaces

STPC Consumer

x86

NORTH

PCI

SOUTH

DRAM VGA VIP

TV

10

SYS

13

ISA/IDE

IPC

11

89

10

9

58

77

10/51

Issue 1.2

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name

BASIC CLOCKS AND RESETS

SYSRSTI#

XTALI

Dir

Description

Qty

I

System Reset / Power good

14.3MHz Crystal Input

1

XTALO

I/O

O

I/O

I

14.3MHz Crystal Output - External Oscillator Input

Host Clock (Test)

1

HCLK

DEV_CLK

24MHz Peripheral Clock (floppy drive)

80MHz Graphics Clock

GCLK2X

DCLK

135MHz Dot Clock

PCI_CLKI

33MHz PCI Input Clock

PCI_CLKO

SYSRSTO#

ISA_CLK

O

33MHz PCI Output Clock (from internal PLL)

Reset Output to System

ISA Clock Output - Multiplexer Select Line For IPC

ISA Clock x 2 Output - Multiplexer Select Line For IPC

ISA_CLK2X

MEMORY INTERFACE

MA[11:0]

I/O

O

Memory Address

Row Address Strobe

Column Address Strobe

Write Enable

12

4

RAS#[3:0]

CAS#[7:0]

O

8

MWE#

O

1

MD[63:0]

I/O

Memory Data

64

PCI INTERFACE

AD[31:0]

CBE[3:0]

FRAME#

TRDY#

I/O

O

PCI Address / Data

Bus Commands / Byte Enables

Cycle Frame

32

4

1

3

4

Target Ready

IRDY#

Initiator Ready

STOP#

Stop Transaction

Device Select

DEVSEL#

PAR

Parity Signal Transactions

System Error

SERR#

LOCK#

I

PCI Lock

PCIREQ#[2:0]

PCIGNT#[2:0]

PCI_INT[3:0]

VDD5

I

PCI Request

O

PCI Grant

I

PCI Interrupt Request

5V Power Supply for PCI ESD protection

I

ISA AND IDE COMBINED ADDRESS/DATA

LA[23:22] / SCS3#,SCS1#

LA[21:20] / PCS3#,PCS1#

LA[19:17] / DA[2:0]

RMRTCCS# / DD[15]

KBCS# / DD[14]

I/O

O

Unlatched Address (ISA) / Secondary Chip Select (IDE)

Unlatched Address (ISA) / Primary Chip Select (IDE)

Unlatched Address (ISA) / Address (IDE)

ROM/RTC Chip Select / Data Bus bit 15 (IDE)

Keyboard Chip Select / Data Bus bit 14 (IDE)

RTC Read/Write / Data Bus bit 13 (IDE)

RTC Data Strobe / Data Bus bit 12 (IDE)

Latched Address (ISA) / Data Bus (IDE)

Latched Address (IDE)

2

3

I/O

1

RTCRW# / DD[13]

RTCDS# / DD[12]

SA[19:8] / DD[11:0]

SA[7:0]

1

16

4

SD[15:0]

Data Bus (ISA)

16

11/51

Issue 1.2

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name

Dir

Description

Qty

ISA/IDE COMBINED CONTROL

IOCHRDY / DIORDY

I/O

I/O Channel Ready (ISA) - Busy/Ready (IDE)

1

ISA CONTROL

OSC14M

O

I/O

O

I/O

I

ISA bus synchronisation clock

Address Latch Enable

1

2

1

2

1

ALE

BHE#

System Bus High Enable

Memory Read and Memory Write

System Memory Read and Memory Write

I/O Read and Write

MEMR#, MEMW#

SMEMR#, SMEMW#

IOR#, IOW#

MASTER#

MCS16#, IOCS16#

REF#

Add On Card Owns Bus

Memory/IO Chip Select16

Refresh Cycle.

I

O

I

AEN

Address Enable

ZWS#

Zero Wait State

IOCHCK#

ISAOE#

I

I/O Channel Check.

O

I/O

Bidirectional OE Control

Real Time Clock Address Strobe

General Purpose Chip Select

RTCAS#

GPIOCS#

IDE CONTROL

PIRQ

I

Primary Interrupt Request

Secondary Interrupt Request

Primary DMA Request

Secondary DMA Request

Primary DMA Acknowledge

Secondary DMA Acknowledge

Primary I/O Read

1

SIRQ

PDRQ

I

SDRQ

I

PDACK#

SDACK#

PIOR#

O

I/O

O

I/O

O

PIOW#

SIOR#

Primary I/O Write

Secondary I/O Read

SIOW#

Secondary I/O Write

IPC

IRQ_MUX[3:0]

DREQ_MUX[1:0]

DACK_ENC[2:0]

TC

I

Multiplexed Interrupt Request

Multiplexed DMA Request

DMA Acknowledge

4

2

3

1

O

ISA Terminal Count

MONITOR INTERFACE

RED, GREEN, BLUE

VSYNC

O

I

Red, Green, Blue

3

1

2

1

Vertical Sync

HSYNC

Horizontal Sync

VREF_DAC

RSET

DAC Voltage reference

Resistor Set

I

COMP

I

Compensation

DDC[1:0]

I/O

Display Data Channel Serial Link

I C Interface - Clock / Can be used for VGA DDC[1] signal

SCL / DDC[1]

12/51

Issue 1.2

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name

SDA / DDC[0]

Dir

I/O

O

Description

Qty

I C Interface - Data / Can be used for VGA DDC[0] signal

Color Compare Output.

1

COL_CMP

VIDEO INPUT

VCLK

I

Pixel Clock

1

8

VIN

YUV Video Data Input CCIR 601 or 656

DIGITAL TV OUTPUT

RED_TV, GREEN_TV, BLUE_TV

VCS

O

I

Analog video outputs synchronized with CVBS

Composite Synch or Horizontal line SYNC output

Frame Synchronisation

3

1

ODD_EVEN

CVBS

Analog video composite output (luminance / chrominance)

Reference current of 9bit DAC for CVBS

Reference voltage of 9bit DAC for CVBS

Reference current of 8bit DAC for R,G,B

Reference voltage of 8bit DAC for R,G,B

Analog Vss for DAC

IREF1_TV

VREF1_TV

I

IREF2_TV

I

VREF2_TV

I

VSSA_TV

I

VDDA_TV

I

Analog Vdd for DAC

MISCELLANEOUS

SPKRD

O

I

Speaker Device Output

Reserved (Test pin)

1

SCAN_ENABLE

13/51

Issue 1.2

PIN DESCRIPTION

2.2 SIGNAL DESCRIPTIONS

2.2.1 BASIC CLOCKS AND RESETS

DCLK 135MHz Dot Clock. This is the dot clock,

which drives graphics display cycles. Its frequency

can go from 8MHz (using internal PLL) up to 135

MHz, and it is required to have a worst case duty

cycle of 60-40.

This signal is either driven by the internal pll (VGA)

or an external 27MHz oscillator (when the com-

posite video output is enabled). The direction can

be controlled by a strap option or an internal regis-

ter bit.

SYSRSTI System Reset/Power good. This input is

low when the reset switch is depressed. Other-

wise, it reflects the power supply’s power good

signal. SYSRSTI is asynchronous to all clocks,

and acts as a negative active reset. The reset cir-

cuit initiates a hard reset on the rising edge of

SYSRSTI.

SYSRSTO# Reset Output to System. This is the

system reset signal and is used to reset the rest of

the components (not on Host bus) in the system.

The ISA bus reset is an externally inverted buff-

ered version of this output and the PCI bus reset is

an externally buffered version of this output.

ISA_CLK ISA Clock Output (also Multiplexer Se-

lect Line For IPC). This pin produces the Clock

signal for the ISA bus. It is also used with

ISA_CLK2X as the multiplexor control lines for the

Interrupt Controller Interrupt input lines. This is a

divided down version of either the PCICLK or

OSC14M.

XTALI 14.3MHz Crystal Input

XTALO 14.3MHz Crystal Output. These pins are

the 14.318MHz crystal input; This clock isused as

the reference clock for the internal frequency syn-

thesizer to generate the HCLK, CLK24M,

GCLK2X and DCLK clocks.

A 14.318 MHz Series Cut Quartz Crystal should

be connected between these two pins. Balance

capacitors of 15 pF should also be added. In the

event of an external oscillator providing the master

clock signal to the STPC Consumer device, the

TTL signal should be provided on XTALO.

ISA_CLKX2 ISA Clock Output (also Multiplexer

Select Line For IPC). This pin produces a signal

that is twice the frequency of the ISA bus Clock

signal. It is also used with ISA_CLK as the multi-

plexor control lines for the Interrupt Controller in-

put lines.

DEV_CLK 24MHz Peripheral Clock Output. This

24MHZ signal is provided as a convenience for

the system integration of a Floppy Disk driver

function in an external chip.

HCLK Host Clock. This is the host 1X clock. Its

frequency can vary from 25 to 75 MHz. All host

transactions and PCI transactions are synchro-

nized to this clock. The DRAM controller to exe-

cute the host transactions is also driven by this

clock. In normal mode, this output clock is gener-

ated by the internal pll.

OSC14M ISA bus synchronisation clock Output.

This is the buffered 14.318 Mhz clock to the ISA

bus.

2.2.2 MEMORY INTERFACE

MA[11:0] Memory Address Output. These 12 mul-

tiplexed memory address pins support external

DRAM with up to 4K refresh. These include all

16M x N and some 4M x N DRAM modules. The

address signals must be externally buffered to

support more than 16 DRAM chips. The timing of

these signals can be adjusted by software to

match the timings of most DRAM modules.

GCLK2X 80MHz Graphics Clock. This is the

Graphics 2X clock, which drives the graphics en-

gine and the DRAM controller to execute the

graphics and display cycles.

Normally GCLK2X is generated by the internal fre-

quency synthesizer, and this pin is an output. By

setting a bit in Strap Register 2, this pin can be

made an input so that an external clock can re-

place the internal frequency synthesizer.

PCI_CLKI 33MHz PCI Input Clock

This signal is the PCI bus clock input and should

be driven from the PCI_CLKO pin.

PCI_CLKO 33MHz PCI Output Clock. This is the

master PCI bus clock output.

14/51

Issue 1.2

PIN DESCRIPTION

MD[63:0] Memory Data I/O. This is the 64-bit

memory data bus. If only half of a bank is populat-

ed, MD63-32 is pulled high, data is on MD31-0.

MD[40-0] are read by the device strap option reg-

isters during rising edge of SYSRSTI.

simple analog low pass filter is recommended. In

S-VHS mode, this is the Chrominance Output.

GREEN_TV / Y_TV Analog video outputs syn-

chronized with CVBS. This output is current-driv-

en and must be connected to analog ground over

RAS#[3:0] Row Address Strobe Output. There

are 4 active low row address strobe outputs, one

for each bank of the memory. Each bank contains

4 or 8-Bytes of data. The memory controller allows

half of a bank (4-bytes) to be populated to enable

memory upgrade at finer granularity.

The RAS# signals drive the SIMMs directly with-

out any external buffering. These pins are always

outputs, but they can also simultaneously be in-

puts, to allow the memory controller to monitor the

value of the RAS# signals at the pins.

a load resistor (R

tor, a simple analog low pass filter is recommend-

ed. In S-VHS mode, this is the Luminance Output.

). Following the load resis-

LOAD

BLUE_TV / CVBSAnalog video outputs synchro-

nized with CVBS. This output is current-driven and

must be connected to analog ground over a load

resistor (R

). Following the load resistor, a

LOAD

simple analog low pass filter is recommended. In

S-VHS mode, this is a second composite output.

VCS Line synchronisation Output. This pin is an

input in ODDEV+HSYNC or VSYNC + HSYNC or

VSYNC slave modes and an output in all other

modes (master/slave)

The signal is synchronous to rising edge of CK-

REF. The default polarity uses a negative pulse

CAS#[7:0] Column Address Strobe Output. There

are 8 active low column address strobe outputs,

one each for each byte of the memory.

The CAS# signals drive the SIMMs either directly

or through external buffers.

These pins are always outputs, but they can also

simultaneously be inputs, to allow the memory

controller to monitor the value of the CAS# signals

at the pins.

ODD_EVEN Frame Synchronisation Ourput. This

pin supports the Frame synchronisation signal. It

is an input in slave modes, except when sync is

extracted from YCrCb data, and an output in mas-

ter mode and when sync is extracted from YCrCb

data

The signal is synchronous to rising edge of DCLK.

The default polarity for this pin is:

- odd (not-top) field : LOW level

MWE# Write Enable Output. Write enable speci-

fies whether the memory access is a read (MWE#

= H) or a write (MWE# = L). This single write ena-

ble controls all the DRAM. It can be externally

buffered to boost the maximum number of loads

(DRAM chips) supported.

- even (bottom) field : HIGH level

The MWE# signals drive the SIMMs directly with-

out any external buffering.

IREF1_TV Ref. current for CVBS 10-bit DAC.

VREF1_TV Ref. voltage for CVBS 10-bit DAC.

IREF2_TV Reference current for RGB 9-bit DAC.

VREF2_TV Reference voltage for RGB 9-bit DAC.

2.2.3 VIDEO INTERFACE

VCLK Pixel Clock Input.

VIN[7:0] YUV Video Data Input CCIR 601 or 656.

Time multiplexed 4:2:2 luminance and chromi-

nance data as defined in ITU-R Rec601-2 and

Rec656 (except for TTL input levels). This bus in-

terfaces with an MPEG video decoder output port

and typically carries a stream of Cb,Y,Cr,Y digital

video at VCLK frequency, clocked on the rising

edge (by default) of VCLK. A 54-Mbit/s ‘double’

Cb, Y, Cr, Y input multiplex is supported for double

encoding application (rising and falling edge of

CKREF are operating).

VSSA_TV Analog V for DAC

SS

VDDA_TV Analog V for DAC

DD

CVBS Analog video composite output (luminance/

chrominance). CVBS is current-driven and must

be connected to analog ground over a load resis-

tor (R

). Following the load resistor, a simple

LOAD

analog low pass filter is recommended.

2.2.5 PCI INTERFACE

2.2.4 TV OUTPUT

AD[31:0] PCI Address/Data. This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and data phase of write transactions. It is

RED_TV / C_TV Analog video outputs synchro-

nized with CVBS. This output is current-driven and

must be connected to analog ground over a load

resistor (R

). Following the load resistor, a

LOAD

15/51

Issue 1.2

PIN DESCRIPTION

driven by the target during data phase of read

transactions.

SERR# System Error. This is the system error sig-

nal of the PCI bus. It may, if enabled, be asserted

for one PCI clock cycle if target aborts a STPC

Consumer initiated PCI transaction. Its assertion

by either the STPC Consumer or by another PCI

bus agent will trigger the assertion of NMI to the

host CPU. This is an open drain output.

CBE#[3:0] Bus Commands/Byte Enables. These

are the multiplexed command and byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

phase they carry the byte enable information.

These pins are inputs when a PCI master other

than the STPC Consumer owns the bus and out-

puts when the STPC Consumer owns the bus.

LOCK# PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

FRAME# Cycle Frame. This is the frame signal of

the PCI bus. It is an input when aPCI master owns

the bus and is an output when STPC Consumer

owns the PCI bus.

PCIREQ#[2:0] PCI Request. This pin are the

three external PCI master request pins. They indi-

cates to the PCI arbiter that the external agents

desire use of the bus.

TRDY# Target Ready. This is the target ready sig-

nal of the PCI bus. It is driven as an output when

the STPC Consumer is the target of the current

bus transaction. It is used as an input when STPC

Consumer initiates a cycle on the PCI bus.

PCIGNT#[2:0] PCI Grant. These pins indicate that

the PCI bus has been granted to the master re-

questing it on its PCIREQ#.

2.2.6 ISA/IDE COMBINED ADDRESS/DATA

IRDY# Initiator Ready. This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Consumer initiates a bus cycle on the

PCI bus. It is used as an input during the PCI cy-

cles targeted to the STPC Consumer to determine

when the current PCI master is ready to complete

the current transaction.

LA[23]/SCS3# Unlatched Address (ISA)/Second-

ary Chip Select (IDE). This pin has two functions,

depending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 23 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally NANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

STOP# Stop Transaction. Stop is used to imple-

ment the disconnect, retry and abort protocol of

the PCI bus. It is used as an input for the bus cy-

cles initiated by the STPC Consumer and is used

as an output when a PCI master cycle is targeted

to the STPC Consumer.

DEVSEL# I/O Device Select. This signal is used

as an input when the STPC Consumer initiates a

bus cycle on the PCI bus to determine if a PCI

slave device has decoded itself to be the target of

the current transaction. It is asserted as an output

either when the STPC Consumer is the target of

the current PCI transaction or when no other de-

vice asserts DEVSEL# prior to the subtractive de-

code phase of the current PCI transaction.

PAR Parity Signal Transactions. This is the parity

signal of the PCI bus. This signal is used to guar-

antee even parity across AD[31:0], CBE#[3:0],

and PAR. This signal is driven by the master dur-

ing the address phase and data phase of write

transactions. It is driven by the target during data

phase of read transactions. (Its assertion is identi-

cal to that of the AD bus delayed by one PCI clock

cycle)

16/51

Issue 1.2

PIN DESCRIPTION

LA[22]/SCS1# Unlatched Address (ISA)/Second-

LA[19:17]/DA[2:0] Unlatched Address (ISA)/Ad-

dress (IDE). These pins are multi-function pins.

They are used as the ISA bus unlatched address

bits [19:17] for ISA bus or the three address bits

for the IDE bus devices.

When used by the ISA bus, these pins are ISA

Bus unlatched address bits 19-17 on 16-bit devic-

es. When ISA bus is accessed by any cycle initiat-

ed from the PCI bus, these pins are in output

mode. When an ISA bus master owns the bus,

these pins are tristated.

ary Chip Select (IDE)

This pin has two functions, depending on whether

the ISA bus is active or the IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 22 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally ANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

For IDE devices, these signals are used as the

DA[2:0] and are connected to DA[2:0] of IDE de-

vices directly or through a buffer. If the toggling of

signals are to be masked during ISA bus cycles,

they can be externally ORed before being con-

nected to the IDE devices.

LA[21]/PCS3# Unlatched Address (ISA)/Primary

Chip Select (IDE). This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 21 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA-

bus master owns the bus, this pins is in input

mode.

SA[19:8]/DD[11:0] Unlatched Address (ISA)/Data

Bus (IDE). These are multifunction pins. When the

ISA bus is active, they are used as the ISA bus

system address bits 19-8. When the IDE bus is ac-

tive, they serve as IDE signals DD[11:0].

These pins are used as an input when an ISA bus

master owns the bus and are outputs at all other

times.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip select sig-

nal. This signal is to be externally NANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

IDE devices are connected to SA[19:8] directlyand

ISA bus is connected to these pins through two

LS245 transceivers. The OE of the transceivers

are connected to ISAOE# and DIR is connected to

MASTER#. A bus signals of the transceivers are

connected to CPC and IDE DD bus and B bus sig-

nals are connected to ISA SA bus.

LA[20]/PCS1# Unlatched Address (ISA)/Primary

Chip Select (IDE). This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 20 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip select sig-

nal. This signal is to be externally NANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

DD[15:12] Databus (IDE). The high 4 bits of the

IDE databus are combined with several of the X-

bus lines. Refer to the following section for X-bus

pins for further information.

SA[7:0] ISA Bus address bits [7:0]. These are the

8 low bits of the system address bus of ISA on 8-

bit slot. These pins are used as an input when an

ISA bus master owns the bus and are outputs at

all other times.

SD[15:0] I/O Data Bus (ISA). These pins are the

external databus to the ISA bus.

17/51

Issue 1.2

PIN DESCRIPTION

2.2.7 ISA/IDE COMBINED CONTROL

IOR# I/O Read. This is the IO read command sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

IOCHRDY/DIORDY Channel Ready (ISA)/Busy/

Ready (IDE). This is a multi-function pin. When

the ISA bus is active, this pin is IOCHRDY. When

the IDE bus is active, this serves as IDE signal DI-

ORDY.

IOCHRDY is the IO channel ready signal of the

ISA bus and is driven as an output in response to

an ISA master cycle targeted to the host bus or an

internal register of the STPC Consumer. The

STPC Consumer monitors this signal as an input

when performing an ISA cycle on behalf of the

host CPU, DMA master or refresh.

IOW# I/O Write. This is the IO write command sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

MASTER# Add On Card Owns Bus. This signal is

active when an ISA device has been granted bus

ownership.

MCS16# Memory Chip Select16. This is the de-

code of LA23-17 address pins of the ISA address

bus without any qualification of the command sig-

nal lines. MCS16# is always an input. The STPC

Consumer ignores this signal during IO and re-

fresh cycles.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Consumer

since the access to the system memory can be

considerably delayed due to CRT refresh or a

write back cycle.

2.2.8 ISA CONTROL

IOCS16# IO Chip Select16. This signal is the de-

code of SA15-0 address pins of the ISA address

bus without any qualification of the command sig-

nals. The STPC Consumer does not drive

IOCS16# (similar to PC-AT design). An ISA mas-

ter access to an internal register of the STPC Con-

sumer is executed as an extended 8-bit IO cycle.

ALE Address Latch Enable. This is the address

latch enable output of the ISA bus and is asserted

by the STPC Consumer to indicate that LA23-17,

SA19-0, AEN and SBHE# signals are valid. The

ALE is driven high during refresh, DMA master or

an ISA master cycles by the STPC Consumer.

ALE is driven low after reset.

REF# Refresh Cycle. This is the refresh command

signal of the ISA bus. It is driven as an output

when the STPC Consumer performs a refresh cy-

cle on the ISA bus. It is used as an input when an

ISA master owns the bus and is used to trigger a

refresh cycle.

The STPC Consumer performs a pseudo hidden

refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

in external buffers. The host bus is then relin-

quished while the refresh cycle continues on the

ISA bus.

BHE# System Bus High Enable. This signal, when

asserted, indicates that a data byte is being trans-

ferred on SD15-8 lines. It is used as an input when

an ISA master owns the bus and is an output at all

other times.

MEMR# Memory Read. This is the memory read

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

AEN Address Enable. Address Enable is enabled

when the DMA controller is the bus owner to indi-

cate that a DMA transfer will occur. The enabling

of the signal indicates to IO devices to ignore the

IOR#/IOW# signal during DMA transfers.

MEMW# Memory Write. This is the memory write

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

SMEMR# System Memory Read. The STPC Con-

sumer generates SMEMR# signal of the ISA bus

only when the address is below one megabyte or

the cycle is a refresh cycle.

ZWS# Zero Wait State. This signal, when assert-

ed by addressed device, indicates that current cy-

cle can be shortened.

IOCHCK# IO Channel Check. IO Channel Check

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal be-

comes active upon seeing IOCHCK# active if the

corresponding bit in Port B is enabled.

SMEMW# System Memory Write. The STPC Con-

sumer generates SMEMW# signal of the ISA bus

only when the address is below one megabyte.

This signal is multiplexed with COL_CMP on the

VGA Interface. The signal is selected by setting

Strap Option MD[0] as described in Section 3.

18/51

Issue 1.2

PIN DESCRIPTION

ISAOE# Bidirectional OE Control. This signal con-

trols the OE signal of the external transceiver that

connects the IDE DD bus and ISA SA bus.

coded before connection to the STPC Consumer

using ISACLK and ISACLKX2 as the input selec-

tion strobes.

GPIOCS# I/O General Purpose Chip Select 1.

This output signal is used by the external latch on

ISA bus to latch the data on the SD[7:0] bus. The

latch can be use by PMU unit to control the exter-

nal peripheral devices to power down or any other

desired function.

DREQ_MUX[1:0] ISA Bus Multiplexed DMA Re-

quest. These are the ISA bus DMA request sig-

nals. They are to be encoded before connection to

the STPC Consumer using ISACLK and

ISACLKX2 as the input selection strobes.

This pin is also serves as a strap input during re-

set.

DACK_ENC[2:0] DMA Acknowledge. These are

the ISA bus DMA acknowledge signals. They are

encoded by the STPC Consumer before output

and should be decoded externally using ISACLK

and ISACLKX2 as the control strobes.

2.2.9 IDE CONTROL

PIRQ Primary Interrupt Request. Interrupt request

from primary IDE channel.

TC ISA Terminal Count. This is the terminal count

output of the DMA controller and is connected to

the TC line of the ISA bus. It is asserted during the

last DMA transfer, when the byte count expires.

SIRQ Secondary Interrupt Request. Interrupt re-

quest from secondary IDE channel.

SPKRD Speaker Drive. This the output to the

speaker and is AND of the counter 2 output with

bit 1 of Port 61, and drives an external speaker

driver. This output should be connected to 7407

type high voltage driver.

PDRQ Primary DMA Request. DMA request from

primary IDE channel.

SDRQ Secondary DMA Request. DMA request

from secondary IDE channel.

2.2.11 X-Bus Interface pins / IDE Data

PDACK# Primary DMA Acknowledge. DMA ack-

noledge to primary IDE channel.

RMRTCCS# / DD[15] ROM/Real Time clock chip

select. This pin is a multi-function pin. When

ISAOE# is active, this signal is used as RM-

RTCCS#. This signal is asserted if a ROM access

is decoded during a memory cycle. It should be

combined with MEMR# or MEMW# signals to

properly access the ROM. During a IO cycle, this

signal is asserted if access to the Real Time Clock

(RTC) is decoded. It should be combined with IOR

or IOW# signals to properly access the real time

clock.

SDACK# Secondary DMA Acknowledge. DMA

acknoledge to secondary IDE channel.

PIOR# Primary I/O Read. Primary channel read.

Active low output.

PIOW# Primary I/O Write. Primary channel write.

Active low output.

SIOR# Secondary I/O Read Secondary channel

read. Active low output.

When ISAOE# is inactive, this signal is used as

IDE DD[15] signal.

This signal must be ORed externally with ISAOE#

and is then connected to ROM and RTC. An

LS244 or equivalent function can be used if OE# is

connected to ISAOE# and the output is provided

with a weak pull-up resistor.

SIOW# Secondary I/O Write Secondary channel

write. Active low output.

2.2.10 IPC

IRQ_MUX[3:0] Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They are

to be encoded before connection to the STPC

Consumer using ISACLK and ISACLKX2 as the

input selection strobes.

Note that IRQ8B, which by convention is connect-

ed to the RTC, is inverted before being sent to the

interrupt controller, so that it may be connected di-

rectly to the IRQ pin of the RTC.

KBCS# / DD[14] Keyboard Chip Select. This pin

is a multi-function pin. When ISAOE# is active,

this signal is used as KBCS#. This signal is assert-

ed if a keyboard access is decoded during a I/O

cycle.

When ISAOE# is inactive, this signal is used as

IDE DD[14] signal.

This signal must be ORed externally with ISAOE#

and is then connected to keyboard. An LS244 or

equivalent function can be used if OE# is connect-

PCI_INT[3:0] PCI Interrupt Request. These are

the PCI bus interrupt signals. They are to be en-

19/51

Issue 1.2

PIN DESCRIPTION

ed to ISAOE# and the output is provided with a

weak pull-up resistor.

HSYNC Horizontal Synchronisation Pulse. This is

the horizontal synchronization signal from the

VGA controller.

RTCRW# / DD[13] Real Time Clock RW. This pin

is a multi-function pin. When ISAOE# is active,

this signal is used as RTCRW#. This signal is as-

serted for any I/O write to port 71H.

VREF_DAC DAC Voltage reference. An external

voltage reference is connected to this pin to bias

the DAC.

When ISAOE# is inactive, this signal is used as

IDE DD[13] signal.

This signal must be ORed externally with ISAOE#

and then connected to the RTC. An LS244 or

equivalent function can be used if OE is connect-

ed to ISAOE# and the output is provided with a

weak pull-up resistor.

RSET Resistor Current Set. This is reference cur-

rent input to the RAMDAC is used to set the full-

scale output of the RAMDAC.

COMP Compensation. This is the RAMDAC com-

pensation pin. Normally, an external capacitor

(typically 10nF) is connected between this pin and

RTCDS# / DD[12] Real Time Clock DS. This pin is

a multi-function pin. When ISAOE# is active, this

signal is used as RTCDS. This signal is asserted

for any I/O read to port 71H.

When ISAOE# is inactive, this signal is used as

IDE DD[12] signal.

V

to damp oscillations.

DD

DDC[1:0] Direct Data Channel Serial Link. These

bidirectional pins are connected to CRTC register

3Fh to implement DDC capabilities. They conform

2

to I C electrical specifications, they have open-

This signal must be ORed externally with ISAOE#

and is then connected to RTC. An LS244 or equiv-

alent function can be used if OE# is connected to

ISAOE# and the output is provided with a weak

pull-up resistor.

collector output drivers which are internally con-

nected to V through pull-up resistors.

DD

They can instead be used for accessing I C devic-

es on board. DDC1 and DDC0 correspond to SCL

and SDA respectively.

RTCAS# Real time clock address strobe. This sig-

nal is asserted for any I/O write to port 70H.

COL_CMP Color Compare Output. Allows access

to the video signal which flags when there is a

color compare hit. This signal is multiplexed with

SMEMEW# on the ISA Bus. The signal is selected

by setting Strap Option MD[0] as described in Sec-

tion3.

2.2.12 Monitor Interface

RED, GREEN, BLUE RGB Video Outputs. These

are the 3 analog color outputs from the RAMDACs

2.2.13 MISCELLANEOUS

VSYNC Vertical Synchronisation Pulse. This is

the vertical synchronization signal from the VGA

controller.

SCAN_ENABLE Reserved. The pins are re-

served for Test and Miscellaneous functions)

20/51

Issue 1.2

PIN DESCRIPTION

Table 2-3. Pinout.

Pin #

U24

Pin name

MD[16]

Pin #

D25

Pin name

PCI_CLKO

AD[0]

Pin #

AF3

Pin name

R26

P25

P26

N25

N26

M25

M26

M24

M23

L24

MD[17]

MD[18]

MD[19]

MD[20]

MD[21]

MD[22]

MD[23]

MD[24]

MD[25]

MD[26]

MD[27]

MD[28]

MD[29]

MD[30]

MD[31]

MD[32]

MD[33]

MD[34]

MD[35]

MD[36]

MD[37]

MD[38]

MD[39]

MD[40]

MD[41]

MD[42]

MD[43]

MD[44]

MD[45]

MD[46]

MD[47]

MD[48]

MD[49]

MD[50]

MD[51]

MD[52]

MD[53]

MD[54]

MD[55]

MD[56]

MD[57]

MD[58]

MD[59]

MD[60]

MD[61]

MD[62]

MD[63]

PCI_CLKI

A20

C20

B19

A19

C19

B18

A18

B17

C18

A17

D17

B16

C17

B15

A15

C16

D15

A14

C15

B13

D13

A13

C14

C13

A12

B11

C12

A11

D12

B10

C11

A10

D10

C10

A9

SYSRSTI

XTALI

AD[1]

A3

AD[2]

C4

XTALO

HCLK

AD[3]

G23

AD[4]

F25

DEV_CLK

GCLK2X

DCLK

AD[5]

AF15

AF9

AD[6]

AD[7]

AD15

AF16

AC15

AE17

AD16

AF17

AC17

AE18

AD17

AF18

AE19

AF19

AD18

AE20

AC19

AF20

AE21

AC20

AF21

AD20

AE22

AF22

AD21

AE23

AC22

AF23

AE24

AF24

AD25

AC25

AC26

AB24

AA25

AA24

Y25

MA[0]

AD[8]

MA[1]

AD[9]

MA[2]

J25

AD[10]

MA[3]

J26

AD[11]

MA[4]

H26

G25

G26

AD22

AD23

AE26

AD26

AC24

AB25

AB26

Y23

AA26

Y26

W25

W26

V25

U25

U26

T25

AD[12]

MA[5]

AD[13]

MA[6]

AD[14]

MA[7]

AD[15]

MA[8]

AD[16]

MA[9]

AD[17]

MA[10]

MA[11]

RAS#[0]

RAS#[1]

RAS#[2]

RAS#[3]

CAS#[0]

CAS#[1]

CAS#[2]

CAS#[3]

CAS#[4]

CAS#[5]

CAS#[6]

CAS#[7]

MWE#

MD[0]

AD[18]

AD[19]

AD[20]

AD[21]

AD[22]

AD[23]

AD[24]

AD[25]

AD[26]

AD[27]

AD[28]

AD[29]

AD[30]

R25

T24

AD[31]

CBE[0]

CBE[1]

CBE[2]

CBE[3]

FRAME#

TRDY#

IRDY#

R23

R24

N23

P24

N24

L25

MD[1]

MD[2]

B8

MD[3]

A8

MD[4]

B7

MD[5]

D8

MD[6]

L26

A7

STOP#

DEVSEL#

PAR

MD[7]

K25

K26

K24

H25

J24

C8

MD[8]

B6

MD[9]

D7

SERR#

LOCK#

PCI_REQ#[0]

PCI_REQ#[1]

PCI_REQ#[2]

PCI_GNT#[0]

Y24

MD[10]

MD[11]

MD[12]

MD[13]

MD[14]

MD[15]

A6

V23

C21

A21

B20

C22

W24

V26

H23

H24

F24

V24

U23

21/51

Issue 1.2

PIN DESCRIPTION

Pin #

B21

Pin name

Pin #

V1

Pin name

SD[11]

Pin #

A23

Pin name

DACK_ENC[1]

DACK_ENC[2]

TC

PCI_GNT#[1]

PCI_GNT#[2]

PCI_INT[0]

PCI_INT[1]

PCI_INT[2]

PCI_INT[3]

D20

A5

W2

W1

V3

SD[12]

SD[13]

SD[14]

SD[15]

B22

D22

C5

C6

B4

SPKRD

Y2

D5

AE6

AD6

AF6

AD5

AC5

AD7

AE8

AF5

C7

RED

Y1

IOCHRDY

GREEN

BLUE

F2

G4

F3

F1

G2

G3

H2

J4

LA[17]/DA[0]

LA[18]/DA[1]

LA[19]/DA[2]

LA[20]/PCS1#

LA[21]/PCS3#

LA[22]/SCS1#

LA[23]/SCS3#

SA[0]

AE4

AD4

AE5

AF8

W3

SYSRSTO#

ISA_CLK

ISA_CLK2X

OSC14M

ALE

VSYNC

HSYNC

VREF_DAC

RSET

COMP

AC9

AA2

Y4

ZWS#

SDA / DDC[0]

SCL / DDC[1]

BHE#

B5

H1

H3

J2

SA[1]

MEMR#

MEMW#

SMEMR#

SMEMW#/COL_CMP

IOR#

SA[2]

AA1

Y3

AC12

AE13

AD14

AD12

AE14

AC14

AF14

AD13

AE15

VCLK

VIN[0]

VIN[1]

VIN[2]

VIN[3]

VIN[4]

VIN[5]

VIN[6]

VIN[7]

SA[3]

J1

SA[4]

AB2

AA3

AC2

AB4

AC1

AB3

AD2

AC3

AD1

AF2

A4

K2

J3

SA[5]

SA[6]

IOW#

K1

K4

L2

SA[7]

MASTER#

MCS16#

IOCS16#

REF#

SA[8]/DD[0]

SA[9]/DD[1]

SA[10]/DD[2]

SA[11]/DD[3]

SA[12] / DD[4]

SA[13] / DD[5]

SA[14] / DD[6]

SA[15] / DD[7]

SA[16] / DD[8]

SA[17] / DD[9]

SA[18] / DD[10]

SA[19] / DD[11]

RTCDS / DD[12]

RTCRW# / DD[13]

KBCS# / DD[14]

RMRTCCS# / DD[15]

SD[0]

K3

L1

AEN

M2

M1

L3

IOCHCK#

ISAOE#

RTCAS#

GPIOCS#

AF10

AC10

AF11

AE10

AD9

RED_TV

GREEN_TV

BLUE_TV

VCS

N2

M4

N1

M3

P4

P3

R2

N3

P1

R1

T2

R3

T1

R4

U2

T3

U1

U4

V2

U3

AE3

ODD_EVEN

CVBS

B1

C2

C1

D2

D3

D1

E2

E4

E3

E1

PIRQ

AD11

AD8

SIRQ

IREF1_TV

VREF1_TV

IREF2_TV

VREF2_TV

PDRQ

SDRQ

PDACK#

SDACK#

PIOR#

PIOW#

SIOR#

SIOW#

AE9

AE11

AD10

B3

SCAN_ENABLE

SD[1]

AF12

AC7

AF4

AD19

AF13

F26

VDDA_TV

SD[2]

VDD_DAC1

VDD_DAC2

VDD_GCLK_PLL

VDD_DCLK_PLL

VDD_HCLK_PLL

VDD_DEVCLK_PLL

VDD5

SD[3]

SD[4]

E23

D26

E24

C25

A24

B23

C23

IRQ_MUX[0]

IRQ_MUX[1]

IRQ_MUX[2]

IRQ_MUX[3]

DREQ_MUX[0]

DREQ_MUX[1]

DACK_ENC[0]

SD[5]

SD[6]

SD[7]

G24

A16

B12

B9

SD[8]

SD[9]

VDD5

SD[10]

VDD5

22/51

Issue 1.2

PIN DESCRIPTION

Pin #

D18

Pin name

Pin #

N11:16

P11:16

P23

Pin name

VDD5

VDD

VSS

A22

B14

C9

R11:16

T11:16

V4

D6

D11

D16

D21

F4

W23

AC4

AC8

F23

G1

AC13

AC18

AC23

AD3

K23

L4

L23

P2

AD24

AE1:2

AE16

AE25

AF1

T4

T23

T26

W4

AF25

AF26

AA4

AA23

AB1

AB23

AC6

AC11

AC16

AC21

C26

D24

B24

A25

RESERVED

AE12

AE7

AF7

E25

E26

A1:2

A26

B2

VSSA_TV

VSS_DAC1

VSS_DAC2

VSS_DLL

VSS

B25:26

C3

VSS

C24

D4

VSS

D9

VSS

D14

D19

D23

H4

VSS

J23

VSS

L11:16

M11:16

N4

VSS

23/51

Issue 1.2

PIN DESCRIPTION

24/51

Issue 1.2

Update History for Pin Description chapter

2.4 Update History for Pin Description chapter

The following changes have been made to the Pin Description Chapter on 08/02/2000

Section

2.2

Change

Added

Text

Color Compare Signal

The following changes have been made to the Pin Description Chapter on 13/01/2000

Section

2.2

Change

Added

Text

“to a minimum of 8MHz”

25/51

Issue 1.2

Update History for Pin Description chapter

26/51

Issue 1.2

STRAP OPTION

3. STRAP OPTION

This chapter defines the STPC Consumer Strap

Options and their location

Memory

Data

Lines

Actual

Settings

Note

1

Refer to

Designation

Location

Set to ’0’

Set to ’1’

MD0

MD1

Index 4A, Bit 0 User defined COLOR_KEY SMEMW#

-

Reserved

-

MD2

2

DRAM Bank 1

Speed

Index 4A, bit 2 User defined

Index 4A, bit 3 Pull up

70 ns

60 ns

MD3

MD4

Type

Index 4A,bit 4 User defined

Index 4A,bit 5 User defined

EDO

FPM

MD5

DRAM Bank 0

Speed

70 ns

60 ns

MD6

Speed

Index 4A,bit 6

Pull up

-

MD7

Type

Index 4A, bit 7 User defined

EDO

FPM

MD8

-

Reserved

Speed

Index4B,bit0

Index4B,bit1

Pull up

-

MD9

-

70 ns

-

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD22

MD23

MD24

MD25

MD26

DRAM Bank 3

Index 4B,bit 2 User defined

Index 4B,bit 3 Pull up

60 ns

Speed

-

Type

Index 4B,bit 4 User defined

Index 4B,bit 5 User defined

EDO

70 ns

-

FPM

DRAM Bank 2

Speed

60 ns

Speed

Index 4B, bit 6

Index 4B,bit 7 User defined

Index 4C,bit 0 Pull up

Pull up

-

Type

EDO

-

FPM

-

Reserved

PCI_CLKO Divisor

Reserved

HCLK PLL Speed

-

PCI Clock

Index 4C,bit 1 User defined HCLK / 2

HCLK / 3

-

Index 4C,bit 2

Index 4C,bit 3

Index 4C, bit4

Index 5F, bit 0

Index 5F, bit 1

Index 5F,bit 2

Pull up

-

HCLK

Index 5F,bit 3 User defined

Index 5F,bit 4 User defined

Index 5F,bit 5 User defined

User defined

000

25 MHz

001

33 MHz

010

40 MHz

011

50 MHz

User defined

100

60 MHz

User defined

101

66 MHz

User defined

110

75 MHz

User defined

111

80 MHz

MD27

MD28

MD29

MD30

MD31

MD32

MD33

MD34

MD35

MD36

MD37

-

Reserved

-

Pull down

Pull up

-

Pull up

27/51

Issue 1.2

STRAP OPTION

Memory

Data

Lines

Actual

Settings

Note

Refer to

Designation

Reserved

Location

Set to ’0’

Set to ’1’

MD38

MD39

MD40

MD41

MD42

MD43

-

Pull up

-

Reserved

CPU Mode

Reserved

-

CPU

User defined

Pull down

Pull up

DX1

DX2

-

Pull down

Note;

3.1.2 STRAP REGISTER

(STRAP1)

1

INDEX 4BH

1) This Strap Option selects between two different

functional blocks, the first is the ISA (SMEMW#)

and the other is the VGA block (Color_Key).

Bits 7-0 of this register reflect the status of pins

MD[15:8] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

2) Setting of Strap Options MD [2:15] have no ef-

fect on the DRAM Controller but are purely meant

for software issues. i.e. Readable in a register.

3.1 STRAP REGISTER DESCRIPTION

Bit Sampled

Bit 7

Description

SIMM 2 dram type

SIMM 2 speed

3.1.1 STRAP REGISTER

(STRAP0)

0

INDEX 4AH

Bits 6-5

Bit 4

SIMM 3 dram type

SIMM 3 speed

Bits 3-2

Bits 7-0 of this register reflect the status of pins

MD[7:0] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Note that the SIMM speed and type information

read here is meant only for thesoftware and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

Bit Sampled

Bit 7

Description

SIMM 0 dram type

SIMM 0 speed

SIMM 1 dram type

SIMM 1 speed

Reserved

This register defaults to the values sampled on

MD[15:8] pins after reset.

Bits 6-5

Bit 4

3.1.3 STRAP REGISTER

(STRAP2)

2

INDEX 4CH

Bits 3-2

Bits 1-0

Bits 4-0 of this register reflect the status of pins

MD[20:16] respectively. Bit 5 of this register reflect

the status of pin MD[23]. Bit 4 is writeable, writes

to other bits in this register have no effect.

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

They are use by the chip as follows:

Bit 4-2; Reserved

This register defaults to the values sampled on

MD[7:0] pins after reset.

28/51

Issue 1.2

STRAP OPTION

Bit 1 This bit reflects the value sampled on

MD[17] pin and controls the PCI clock output as

follows:

Bits 5-3; These pins reflect the value sampled on

MD[26:24] pins respectively and control the Host

clock frequency synthesizer.

0: PCI clock output = HCLK / 2

1: PCI clock output = HCLK / 3

Bit 0; Reserved

Bit 2-0; Reserved

This register defaults to the values sampled on

above pins after reset.

Strap Options [39:27] are reserved.

This register defaults to the values sampled on

MD[23] & MD[20:16] pins after reset.

3.1.5 486 CLOCK PROGRAMMING (486_CLK)

3.1.4 HCLK PLL STRAP REGISTER 0 INDEX

5FH (HCLK_STRAP0)

The bit MD[40] is used to set the clock multiplica-

tion factor of the 486 core. With the MD[40] pin

pulled low the 486 will run in DX (x1) mode, while

with the MD[40] pin pulled high the 486 will run in

DX2 (x2) mode. The default value of the resistor

on this strap input should be a resister to ground

(DX mode).

Bits 5-0 of this register reflect the status of pins

MD[26:21] respectively. They are use by the chip

as follows:

Strap options MD[43:41] are reserved.

29/51

Issue 1.2

ELECTRICAL SPECIFICATIONS

4. ELECTRICAL SPECIFICATIONS

4.1 Introduction

20 kΩ (±10%) pull-up resistor to prevent spurious

operation.

The electrical specifications in this chapter are val-

id for the STPC Consumer.

4.2.3 Reserved Designated Pins

Pins designated reserved should be left discon-

nected. Connecting a reserved pin to a pull-up re-

sistor, pull-down resistor, or an active signal could

cause unexpected results and possible circuit

malfunctions.

4.2 Electrical Connections

4.2.1 Power/Ground Connections/Decoupling

Due to the high frequency of operation of the

STPC Consumer, it is necessary to install and test

this device using standard high frequency tech-

niques. The high clock frequencies used in the

STPC Consumer and its output buffer circuits can

cause transient power surges when several output

buffers switch output levels simultaneously. These

effects can be minimized by filtering the DC power

leads with low-inductance decoupling capacitors,

using low impedance wiring, and by utilizing all of

the VSS and VDD pins.

4.3 Absolute Maximum Ratings

The following table lists the absolute maximum

ratings for the STPC Consumer device. Stresses

beyond those listed under Table 4-1 limits may

cause permanent damage to the device. These

are stress ratings only and do not imply that oper-

ation under any conditions other than those spec-

ified in section ”Operating Conditions”.

Exposure to conditions beyond Table 4-1 may (1)

reduce device reliability and (2) result in prema-

ture failure even when there is no immediately ap-

parent sign of failure. Prolonged exposure to con-

ditions at or near the absolute maximum ratings

(Table 4-1) may also result in reduced useful life

and reliability.

4.2.2 Unused Input Pins

All inputs not used by the designer and not listed

in the table of pin connections in Chapter 3 should

be connected either to VDD or to VSS. Connect

active-high inputs to VDD through a20 kΩ (±10%)

pull-down resistor and active-low inputs to VSS

and connect active-low inputs to VCC through a

Table 4-1. Absolute Maximum Ratings

Symbol

Parameter

Value

-0.3, 4.0

-0.3, VDD + 0.3

-40, +150

0, +70

Units

V

DC Supply Voltage

DDx

V , V

Digital Input and Output Voltage

Storage Temperature

Operating Temperature

Total Power Dissipation

V

I

O

T

°C

W

STG

T

OPER

P

4.8

TOT

30/51

Issue 1.2

ELECTRICAL SPECIFICATIONS

4.4 DC Characteristics

Table 4-2. DC Characteristics

Recommended Operating conditions : VDD = 3.3V ±0.3V, Tcase = 0 to 100°C unless otherwise specified

Symbol Parameter

Test conditions

Min

Typ

3.3

3.2

Max

3.6

3.9

75

Unit

V

P

Operating Voltage

Supply Power

3.0

DD

V

= 3.3V, H = 66Mhz

CLK

W

DD

H

Internal Clock

(Note 1)

Mhz

CLK

V

REF_D

AC

DAC Voltage Reference

1.215

1.235

1.255

0.5

V

Output Low Voltage

Output High Voltage

Input Low Voltage

I

=1.5 to 8mA depending of the pin

=-0.5 to -8mA depending of the pin

Load

V

OL

Load

V

I

2.4

-0.3

2.1

OH

V

Except XTALI

XTALI

0.8

0.9

V

IL

V

Input High Voltage

Except XTALI

XTALI

V

+0.3

V

IH

DD

2.35

-5

+0.3

V

DD

I

Input Leakage Current

Input Capacitance

Output Capacitance

Clock Capacitance

Input, I/O

(Note 2)

5

µA

pF

LK

C

IN

C

(Note 2)

OUT

C

(Note 2)

CLK

Notes:

rising clock edge reference level VREF , and other

reference levels are shown in Table 4-3 below for

the STPC Consumer. Input or output signals must

cross these levels during testing.

1. MHz ratings refer to CPU clock frequency.

2. Not 100% tested.

Figure 4-1 shows output delay (A and B) and input

setup and hold times (C and D). Input setup and

hold times (C and D) are specified minimums, de-

fining the smallest acceptable sampling window a

synchronous input signal must be stable for cor-

rect operation.

4.5 AC Characteristics

Table 4-4 through Table 4-9 list the AC character-

istics including output delays, input setup require-

ments, input hold requirements and output float

delays. These measurements are based on the

measurement points identified in Figure 4-1 . The

Table 4-3. Drive Level and Measurement Points for Switching Characteristics

Symbol

Value

1.5

Units

V

REF

V

3.0

IHD

V

0.0

ILD

Note: Refer to Figure 4-1.

31/51

Issue 1.2

ELECTRICAL SPECIFICATIONS

Figure 4-1 Drive Level and Measurement Points for Switching Characteristics

Tx

V

IHD

CLK:

Ref

ILD

V

A

MAX

B

MIN

Valid

Output n

Valid

Output n+1

V

OUTPUTS:

Ref

C

D

V

IHD

Valid

Input

INPUTS:

LEGEND:

Ref

ILD

V

A - Maximum Output Delay Specification

B - Minimum Output Delay Specification

C - Minimum Input Setup Specification

D - Minimum Input Hold Specification

Figure 4-2 CLK Timing Measurement Points

T1

T2

V

IH (MIN)

V

Ref

IL (MAX)

CLK

T5

T3

T4

T1 - One Clock Cycle

T2 - Minimum Time at V

LEGEND:

IH

T3 - Minimum Time at V

T4 - Clock Fall Time

T5 - Clock Rise Time

IL

NOTE; All sIgnals are sampled on the rising edge of the CLK.

Note; The above timings are generic timings and are not specific to the interfaces defined below

32/51

Issue 1.2

ELECTRICAL SPECIFICATIONS

4.5.1 AC Timing parameters

Table 4-4. PCI Bus AC Timing

Name

t1

Parameter

Min

2

Max

11

12

Unit

ns

PCI_CLKI to AD[31:0] valid

PCI_CLKI to FRAME# valid

PCI_CLKI to CBE#[3:0] valid

PCI_CLKI to PAR valid

t2

2

t3

2

t4

2

t5

PCI_CLKI to TRDY# valid

PCI_CLKI to IRDY# valid

2

T6

T7

T8

T9

t10

t11

t12

t13

t14

t15

t16

t17

t18

t19

2

PCI_CLKI to STOP# valid

PCI_CLKI to DEVSEL# valid

PCI_CLKI to PCI_GNT# valid

AD[31:0] bus setup to PCI_CLKI

AD[31:0] bus hold from PCI_CLKI

PCI_REQ#[2:0] setup to PCI_CLKI

PCI_REQ#[2:0] hold from PCI_CLKI

CBE#[3:0] setup to PCI_CLKI

CBE#[3:0] hold to PCI_CLKI

IRDY# setup to PCI_CLKI

IRDY# hold to PCI_CLKI

2

7

0

7

4

7

0

7

0

FRAME# setup to PCI_CLKI

FRAME# hold from PCI_CLKI

7

0

Table 4-5. DRAM Bus AC Timing

Name

t22

t23

t24

t25

t26

t27

t28

t29

t30

t31

t32

t33

Parameter

Min

13

0

Max

19

Unit

ns

HCLK to RAS#[3:0] valid

HCLK to CAS#[7:0] bus valid

HCLK to MA[11:0] bus valid

HCLK to MWE# valid

19

17

HCLK to MD[63:0] bus valid

MD[63:0] Generic setup

GCLK2X to RAS#[3:0] valid

GCLK2X to CAS#[7:0] valid

GCLK2X to MA[11:0] bus valid

GCLK2X to MWE# valid

GCLK2X to MD[63:0] bus valid

MD[63:0] Generic hold

20

19

17

20

Table 4-6. IDE Bus AC Timing

Name

t20

Parameter

Min

15

0

Max

Unit

ns

DD[15:0] setup to PIOR#/SIOR# falling

DD[15:0} hold to PIOR#/SIOR# falling

t21

ns

33/51

Issue 1.2

ELECTRICAL SPECIFICATIONS

Table 4-7. Video Input AC Timing

Name

t35

Parameter

Min

5

Max

Unit

ns

VIN[7:0] setup to VCLK

VIN[7:0] hold from VCLK

VCLK to ODD_EVEN valid

VCLK to VCS valid

t36

4

t37

15

t38

t39

ODD_EVEN setup to VCLK

ODD_EVEN hold from VCLK

VCS setup to VCLK

10

5

t40

t41

10

5

t42

VCS hold from VCLK

Table 4-8. Graphics Adapter (VGA) AC Timing

Name

t43

Parameter

Min

Max

30

Unit

ns

DCLK to VSYNC valid

DCLK to HSYNC valid

t44

30

ns

Table 4-9. ISA Bus AC Timing

Name

t45

t46

t47

t48

t49

t50

t51

t52

t53

t54

t55

t56

t57

Parameter

Max

60

62

35

28

60

62

50

Unit

ns

XTALO to LA[23:17] bus active

XTALO to SA[19:0] bus active

XTALO to BHE# valid

XTALO to SD[15:0] bus active

PCI_CLKI to ISAOE# valid

XTALO to GPIOCS# valid

XTALO to ALE valid

XTALO to MEMW# valid

XTALO to MEMR# valid

XTALO to SMEMW# valid

XTALO to SMEMR# valid

XTALO to IOR# valid

XTALO to IOW# valid

34/51

Issue 1.2

Update History for Electrical Specification chapter

4.10 Update History for Electrical Specification chapter

The following changes have been made to the Electrical Specification Chapter on the 07/02/2000.

Section

4.5

Change

Revued

Text

Timings t35 - t42

The following changes have been made to the Electrical Specification Chapter on the 20/10/99.

Section

4.5

Change

Revued

Text

Timings T1-10, T12, T14, T16, T18, T26, T32, T35, T39-42 &T54

The following changes have been made to the Electrical Specification Chapter on the 16/08/99.

Section

18

Change

Text

Removed

Figure 4-2 CLK Timing Measurement Points.

35/51

Issue 1.2

Update History for Electrical Specification chapter

36/51

MECHANICAL DATA

5. MECHANICAL DATA

5.1 388-Pin Package Dimension

Dimensions are shown in Figure 5-2, Table 5-1

and Figure 5-3, Table 5-2.

The pin numbering for the STPC 388-pin Plastic

BGA package is shown in Figure 5-1.

Figure 5-1. 388-Pin PBGA Package - Top View

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

A

B

C

D

E

F

G

H

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

37/51

Issue 1.2

MECHANICAL DATA

Figure 5-2. 388-pin PBGA Package - PCB Dimensions

A1 Ball Pad Corner

A

B

A

D

E

F

Detail

G

C

Table 5-1. 388-pin PBGA Package - PCB Dimensions

mm

inches

Typ

Symbols

Min

34.95

1.22

0.58

1.57

0.15

0.05

0.75

Typ

35.00

1.27

0.63

1.62

0.20

0.10

0.80

Max

35.05

1.32

0.68

1.67

0.25

0.15

0.85

Min

Max

A

B

C

D

E

F

1.375

0.048

0.023

0.062

0.006

0.002

0.030

1.378

0.050

0.025

0.064

0.008

0.004

0.032

1.380

0.052

0.027

0.066

0.001

0.006

0.034

G

38/51

Issue 1.2

MECHANICAL DATA

Figure 5-3. 388-pin PBGA Package - Dimensions

C

F

D

E

Solderball

Solderball after collapse

B

G

A

Table 5-2. 388-pin PBGA Package - Dimensions

mm

inches

Symbols

Min

0.50

1.12

0.60

0.52

0.63

0.60

Typ

0.56

1.17

0.76

0.53

0.78

0.63

30.0

Max

0.62

1.22

0.92

0.54

0.93

0.66

Min

Typ

Max

A

B

C

D

E

F

0.020

0.044

0.024

0.020

0.025

0.024

0.022

0.046

0.030

0.021

0.031

0.025

11.8

0.024

0.048

0.036

0.022

0.037

0.026

G

39/51

Issue 1.2

MECHANICAL DATA

5.2 388-Pin Package thermal data

Structure in shown in Figure 5-4.

Thermal dissipation options are illustrated in Fig-

ure 5-5 and Figure 5-6.

388-pin PBGA package has a Power Dissipation

Capability of 4.5W which increases to 6W when

used with a Heatsink.

Figure 5-4. 388-Pin PBGA structure

Signal layers

Power & Ground layers

Thermal balls

Figure 5-5. Thermal dissipation without heatsink

Board

Board dimensions:

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

Ambient

Case

Junction

Rca

Rjc

6

The PBGA is centered on board

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

Board

8.5

Case

125

Junction

Board

Rjb

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

Ambient

Rba

Ambient

Airflow = 0

Rja = 13 °C/W

Board temperature taken at the center balls

40/51

Issue 1.2

MECHANICAL DATA

Figure 5-6. Thermal dissipation with heatsink

Board

Board dimensions:

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

Ambient

Case

Junction

Rca

Rjc

The PBGA is centered on board

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

3

6

Board

8.5

Case

50

Junction

Board

Rjb

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

Ambient

Rba

Airflow = 0

Ambient

Board temperature taken at the center balls

Heat sink is 11.1°C/W

Rja = 9.5 °C/W

41/51

Issue 1.2

MECHANICAL DATA

42/51

Issue 1.2

BOARD LAYOUT

6. BOARD LAYOUT

6.1 THERMAL DISSIPATION

Thermal dissipation of the STPC depends mainly

on supply voltage. As a result, when the system

does not need to work at 3.3V, it may be to reduce

the voltage to 3.15V for example. This may save

few 100’s of mW.

With such configuration the Plastic BGA 388 pack-

age dissipates 90% of the heat through theground

balls, and especially the central thermal balls

which are directly connected to the die, the re-

maining 10% is dissipated through the case. Add-

ing a heat sink reduces this value to 85%.

The second area that can be concidered is un-

used interfaces and functions. Depending on the

application, some input signals can be grounded,

and some blocks not powered or shutdown. Clock

speed dynamic adjustment is also a solution that

can be used along with the integrated power man-

agement unit.

As a result, some basic rules have to be applied

when routing the STPC in order to avoid thermal

problems.

First of all, the whole ground layer acts as a heat

sink and ground balls must be directly connected

to it as illustrated in Figure 6-1.

The standard way to route thermal balls to internal

ground layer implements only one via pad for each

ball pad, connected using a 8-mil wire.

If one ground layer is not enough, a second

ground plane may be added on the solder side.

Figure 6-1. Ground routing

Pad for ground ball

Thru hole to ground layer

Note: For better visibility, ground balls are not all routed.

43/51

Issue 1.2

BOARD LAYOUT

When considering thermal dissipation, the most

important - and not the more obvious - part of the

layout is the connection between the ground balls

and the ground layer.

To avoid solder wicking over to the via pads during

soldering, it is important to have a solder mask of

4 mil around the pad (NSMD pad), this gives a di-

ameter of 33 mil for a 25 mil ground pad.

A 1-wire connection is shown in Figure 6-2. The

use of a 8-mil wire results in a thermal resistance

of 105°C/W assuming copper is used (418 W/

m.°K). This high value is due to the thickness (34

µm) of the copper on the external side of the PCB.

To obtain the optimum ground layout, place the

vias directly under the ball pads. In this case no lo-

cal boar d distortion is tolerated.

The thickness of the copper on PCB layers is typ-

ically 34 µm for external layers and 17 µm for inter-

nal layers. This means thermal dissipation is not

good and temperature of the board is concentrat-

ed around the devices and falls quickly with in-

creased distance.

Considering only the central matrix of 36 thermal

balls and one via for each ball, the global thermal

resistance is 2.9°C/W. This can be easily im-

proved by using four 10 mil wires to connect to the

four vias around the ground pad link as in Figure

6-3. This gives a total of 49 vias and a global resis-

tance for the 36 thermal balls of 0.6°C/W.

When it is possible to place a metal layer inside

the PCB, this improves dramatically the heat

spreading and hence thermal dissipation of the

board.

The use of a ground plane like in Figure 6-4 is

even better.

Figure 6-2. Recommended 1-wire ground pad layout

Pad for ground ball (diameter = 25 mil)

Solder Mask (4 mil)

Connection Wire (width = 10 mil)

Via (diameter = 24 mil)

Hole to ground layer (diameter = 12 mil)

1 mil = 0.0254 mm

Figure 6-3. Recommended 4-wire ground pad layout

4 via pads for each ground ball

44/51

Issue 1.2

BOARD LAYOUT

Figure 6-4. Optimum layout for central ground ball

Clearance = 6mil

External diameter = 37 mil

Via to Ground layer

hole diameter = 14 mil

Solder mask

diameter = 33 mil

Pad for ground ball

diameter = 25 mil

connections = 10 mil

The PBGA Package also dissipates heat through

peripheral ground balls. When a heat sink is

placed on the device, heat is more uniformely

spread throughout the moulding increasing heat

dissipation through the peripheral ground balls.

The more via pads are connected to each ground

ball, the more heat is dissipated . The only limita-

tion is the risk of lossing routing channels.

Figure 6-5 shows a routing with a good trade off

between thermal dissipation and number of rout-

ing channels.

Figure 6-5. Global ground layout for good thermal dissipation

Via to ground layer

Ground pad

45/51

Issue 1.2

BOARD LAYOUT

Figure 6-6. Bottom side layout and decoupling

Ground plane for thermal dissipation

Via to ground layer

A local ground plane on opposite side of the board

as shown in Figure 6-6 improves thermal dissipa-

tion. It is used to connect decoupling capacitances

but can also be used for connection to a heat sink

or to the system’s metal box for better dissipation.

This possibility of using the whole system’s box for

thermal dissipation is very usefull in case of high

temperature inside the system and low tempera-

ture outside. In that case, both sides of the PBGA

should be thermally connected to the metal chas-

sis in order to propagate the heat through the met-

al. Figure 6-7 illustrates such an implementation.

Figure 6-7. Use of metal plate for thermal dissipation

Die

Board

Metal planes

Thermal conductor

46/51

Issue 1.2

BOARD LAYOUT

6.2 HIGH SPEED SIGNALS

Some Interfaces of the STPC run at high speed

and have to be carefully routed or even shielded.

All the clocks have to be routed first and shielded

for speeds of 27MHz or more. The high speed sig-

nals have the same contrainsts as some of the

memory interface control signals.

Here is the list of these interfaces, in decreasing

speed order:

The next interfaces to be routed are Memory, Vid-

eo/graphics, and PCI.

- Memory Interface.

- Graphics and video interfaces

- PCI bus

All the analog noise sensitive signals have to be

routed in a separate area and hence can be rout-

ed indepedently.

- 14MHz oscillator stage

Figure 6-8. Shielding signals

ground ring

shielded signal line

ground pad

shielded signal lines

47/51

Issue 1.2

ORDERING DATA

7. ORDERING DATA

7.1 Ordering Codes

ST

PC

C01

66

BT

C

3

STMicroelectronics

Prefix

Product Family

PC: PC Compatible

Product ID

C01: Consumer

Core Speed

66: 66MHz

75: 75MHz

80: 80MHz

10: 100MHz

Package

BT: 388 Overmoulded BGA

Temperature Range

C: Commercial

0 to +70°C

Tcase = 0 to +100°C

I: Industrial

-40 to +85°C

Tcase = -40 to +100°C

Operating Voltage

3 : 3.3V ± 0.3V

48/51

Issue 1.2

ORDERING DATA

7.2 Available Part Numbers

Core Frequency

Tcase Range

(C)

Operating Voltage

(V)

Part Number

CPU Mode

(MHz)

STPCC0166BTC3

STPCC0180BTC3

STPCC0110BTC3

STPCC0166BTI3

STPCC0180BTI3

66

DX

80

0°C to +100°C

100

66

DX2

DX

3.3V ± 0.3V

-40°C to +100°C

80

DX

49/51

Issue 1.2

ORDERING DATA

50/51

Issue 1.2

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

51

Issue 1.2


型号：	STPCC0180BTC3
厂家：	ST
描述：	PC Compatible Embeded Microprocessor PC兼容的嵌入式微处理器多功能外围设备微控制器和处理器外围集成电路微处理器 PC 时钟
文件：	总51页 (文件大小：726K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STPCC0180BTC3 [STMICROELECTRONICS]

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