STPCC03_技术文档

STPC_®CONSUMER-S

PC Compatible Embeded Microprocessor

■

POWERFUL x86 PROCESSOR

64-BIT 66MHz SDRAM UMA CONTROLLER

-SUPPORTS 16Mbit SDRAMs

(4MX4, 2MX8, 1MX16).

■

VGA & SVGA CRT CONTROLLER

2D GRAPHICS ENGINE

VIDEO INPUT PORT

VIDEO PIPELINE

- UP-SCALER

- VIDEO COLOR SPACE CONVERTER

- CHROMA & COLOUR KEY SUPPORT

TV OUTPUT

PBGA388

Figure 0-1. Logic Diagram

Host x86

■

- 3-LINE FLICKER FILTER

- CCIR 601/656 SCAN CONVERTER

- NTSC / PAL COMPOSITE, RGB, S-VIDEO

PCI MASTER / SLAVE CONTROLLER

ISA MASTER / SLAVE CONTROLLER

INTEGRATED PERIPHERAL CONTROLLER

- DMA CONTROLLER

■

- INTERRUPT CONTROLLER

- TIMER / COUNTERS

PCI Bus

PCI

m/s

PMU

ISA

■

OPTIONAL 16-BIT LOCAL BUS INTERFACE

EIDE CONTROLLER

IDE

PCI

IPC

I²C INTERFACE

POWER MANAGEMENT UNIT

3.45V OPERATION

ISA Bus

LB

Local Bus

STPC CONSUMER-S OVERVIEW

Video

The STPC Consumer-S integrates a standard 5th

generation x86 core, a Synchronous DRAM con-

troller, a graphics subsystem, a video input port,

video pipeline, and support logic including PCI,

ISA, and IDE controllers to provide a single con-

sumer orientated PC compatible subsystem on a

single device.

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing the same

memory array between the CPU main memory

and the graphics and video frame buffers.

C Key

K Key

Monitor

SVGA

CRTC

TVO

Cursor

GE

TV

Encoder

VIP

SDRAM

The STPC Consumer-S is packaged in a 388

Plastic Ball Grid Array (PBGA).

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STPC CONSUMER-S OVERVIEW

■

X86 Processor core

Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

Can access up to 4GB of external memory.

8Kbyte unified instruction and data cache

with write back and write through capability.

Parallel processing integral floating point unit,

with automatic power down.

■

CRT Controller

Integrated 135MHz triple RAMDAC allowing

for 1024 x 768 x 75Hz display.

8-, 16-, 24-bit pixels.

■

Interlaced or non-interlaced output.

■

Video Input port

Accepts video inputs in CCIR 601 mode.

Optional 2:1 decimator

Stores captured video in off setting area of

the onboard frame buffer.

■

Fully static design for dynamic clock control.

Low power and system management modes.

■

Video pass through to the onchip PAL/NTSC

encoder for full screen video images.

HSYNC and B/T generation or lock onto

external video timing source.

■

SDRAM Controller

64-bit data bus.

Up to 66MHz SDRAM clock speed.

Integrated system memory, graphic frame

memory and video frame memory.

Supports 2MB up to 128 MB memory.

Supports 8MB, 16M, and 32MB DIMMS.

Supports buffered, non buffered, and

registered DIMMS.

4-line write buffers for CPU to DRAM and PCI

to DRAM cycles.

4-line read prefetch buffers for PCI masters.

Programmable latency

Programmable timing for DRAM parameters.

Supports -8, -10 memory parts

Supports 1MB up to 8MB memory hole.

32-bit accesses not supported.

Autoprecharge not supported.

Power down not supported.

FPM and EDO not supported.

Supports 16M-bit full page mode SDRAMS’s

(1M x 16, 2M x 8 & 4M x 4)

■

Video Pipeline

Two-tap interpolative horizontal filter.

Two-tap interpolative vertical filter.

Color space conversion.

Programmable window size.

Chroma and color keying for integrated video

overlay.

■

TV Output

Programmable two tap filter with gamma

correction or three tap flicker filter.

Progressive to interlaced scan converter.

NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy

programmable video outputs.

■

CCIR601 encoding with programmable color

subcarrier frequencies.

■

Line skip/insert capability

Interlaced or non-interlaced operation mode.

625 lines/50Hz or 525 lines/60Hz 8 bit

multiplexed CB-Y-CR digital input.

CVBS and R,G,B simultaneous analog

outputs through 10-bit DACs.

Cross color reduction by specific trap filtering

on luma within CVBS flow.

Power down mode available on each DAC.

■

Graphics Controller

64-bit windows accelerator.

■

Compatibility to VGA & SVGA standards.

Hardware acceleration for text, bitblts,

transparent blts and fills.

Up to 64 x 64 bit graphics hardware cursor.

Up to 4MB long linear frame buffer.

8-, 16-, and 24-bit pixels.

■

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Issue 1.1 - October 16, 2000

STPC CONSUMER-S OVERVIEW

■

PCI Controller

■

Local Bus interface

Multiplxed with ISA interface.

Low latency bus

22-bit address bus.

16-bit data bus with word steering capability.

Programmable timing (Host clock granularity)

2 Programmable Flash Chip Select.

4 Programmable I/O Chip Select.

Supports 32-bit Flash burst.

Fully compliant with PCI 2.1 specification.

Integrated PCI arbitration interface. Up to 3

masters can connect directly. External PAL

allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to

PCI.

■

Support for burst read/write from PCI master.

PCI clock is 1/3 or 1/2 Host clock .

2-level hardware key protection for Flash boot

block protection.

■

Supports 2 banks of 8MB flash devices with

boot block shadowed to 0x000F0000.

■

ISA master/slave controller

Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

Supports programmable extra wait state for

ISA cycles

Supports I/O recovery time for back to back I/

O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

Supports flash ROM.

■

IDE Interface

Supports PIO and Bus Master IDE

Supports up to Mode 5 Timings

Transfer Rates to 22 MBytes/sec

Supports up to 4 IDE devices

Concurrent channel operation (PIO & DMA

modes) - 4 x 32-Bit Buffer FIFO per channel

Support for PIO mode 3 & 4.

■

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host bus.

NSP compliant.

Support for DMA mode 1 & 2.

Bus Master with scatter/gather capability

Multi-word DMA support for fast IDE drives

Individual drive timing for all four IDE devices

Supports both legacy & native IDE modes

Supports hard drives larger than 528MB

Support for CD-ROM and tape peripherals

Backward compatibility with IDE (ATA-1).

■

Integrated Peripheral Controller

2X8237/AT compatible 7-channel DMA

controller.

■

2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

Supports external RTC.

■

Power Management

Four power saving modes: On, Doze,

Standby, Suspend.

Programmable system activity detector

Supports SMM.

Supports STOPCLK.

■

Supports IO trap & restart.

Independent peripheral time-out timer to

monitor hard disk, serial & parallel ports.

Supports RTC, interrupts and DMAs wake-up

■

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GENERAL DESCRIPTION

1 GENERAL DESCRIPTION

At the heart of the STPC Consumer-S is an ad-

vanced 64-bit processor block, dubbed the

5ST86. The 5ST86 includes a 5th generation

processor core along with a 64-bit SDRAM con-

troller, advanced 64-bit accelerated graphics and

video controller, a high speed PCI local-bus con-

troller and Industry standard PC chip set functions

(Interrupt controller, DMA Controller, Interval timer

and ISA bus).

resistors on the memory data bus, checked on re-

set, which auto-configure the STPC Consumer-S.

GRAPHICS FUNCTIONS

Graphics functions are controlled through the on-

chip SVGA controller and the monitor display is

produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the

host CPU to provide a balanced graphics system

with a low silicon area cost. It performs limited

graphics drawing operations which include hard-

ware acceleration of text, bitblts, transparent blts

and fills. The results of these operations change

the contents of the on-screen or off-screen Frame

Buffer areas of DRAM memory. The Frame Buffer

can occupy a space up to 4 Mbytes anywhere in

the physical main memory and always starts from

the bottom of the main physical memory.

The STPC Consumer-S makes use of a tightly

coupled Unified Memory Architecture (UMA),

where the same memory array is used for CPU

main memory and graphics frame-buffer. This

means a reduction in total system memory for sys-

tem performances that are equal to that of a com-

parable Frame Buffer and system memory based

system, and generally much better, due to the

higher memory bandwidth allowed by attaching

the graphics engine directly to the 64-bit proces-

sor host interface running at the speed of the proc-

essor bus rather than the traditional PCI bus.

The graphics resolution supported is a maximum

of 1280x1024 in 65536 colours and 1024x768 in

true color at 75Hz refresh rate and is VGA and

SVGA compatible. Horizontal timing fields are

VGA compatible while the vertical fields are ex-

tended by one bit to accommodate above display

resolution.

The 64-bit wide memory array provides the sys-

tem with 528MB/s peak bandwidth. This allows for

higher resolution screens and greater color depth.

The ‘standard’ PC chipset functions (DMA, inter-

rupt controller, timers, power management logic)

are integrated together with the x86 processor

core; additional functions such as communica-

tions ports are accessed by the STPC Consumer-

S via internal ISA bus.

VIDEO FUNCTIONS

The STPC Consumer-S provides several addition-

al functions to handle MPEG or similar video

streams. The Video Input Port accepts an encod-

ed digital video stream in one of a number of in-

dustry standard formats, decodes it, optionally

decimates it, and deposits it into an off screen

area of the Frame Buffer. An interrupt request can

be generated when an entire field or frame has

been captured. The video output pipeline incorpo-

rates a video-scaler and color space converter

function and provisions in the CRT controller to

display a video window. While repainting the

screen the CRT controller fetches both the video

as well as the normal non-video Frame Buffer in

two separate internal FIFOs. The video stream

can be color-space converted (optionally) and

smooth scaled. Smooth interpolative scaling in

both horizontal and vertical direction are imple-

mented. Color and Chroma key functions are also

implemented to allow mixing video stream with

non-video Frame Buffer.

The PCI bus is the main data communication link

to the STPC Consumer-S chip. The STPC Con-

sumer-S translates appropriate host bus I/O and

Memory cycles onto the PCI bus. It also supports

generation of Configuration cycles on the PCI bus.

The STPC Consumer-S, as a PCI bus agent (host

bridge class), fully complies with PCI specification

2.1. The chip-set also implements the PCI manda-

tory header registers in Type 0 PCI configuration

space for easy porting of PCI aware system BI-

OS. The device contains a PCI arbitration function

for three external PCI devices.

The STPC Consumer-S has two functionnal

sharing the same balls

blocks

: The ISA / IPC /

IDE block and the Local Bus / IDE block (see Ta-

ble 2-1 & Table 2-4). Any board with the STPC

Consumer-S should be built using only one of

these two configurations.

The video output passes directly to the RAMDAC

for monitor output or through another optional

color space converter (RGB to 4:2:2 YCrCb) to the

programmable anti-flicker filter. The flicker filter is

At reset, the configuration is done by ‘strap op-

tions’ which initialises the STPC Consumer-S to

the right settings. It is a set of pull-up or pull-down

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Issue 1.1 - October 16, 2000

GENERAL DESCRIPTION

configured as either a two line filter with gamma

correction (primarily designed for DOS type text)

or a 3 line flicker filter (primarily designed for Win-

dows type displays). The flicker filter is optional

and can be software disabled for use with large

screen area’s of video.

Four Memory Banks (if DIMMS are used; Single

sided or two double-sided DIMMs) are supported

in the following configurations (see Table 1-1):

Table 1-1. Supported Memory Configs

Memory

Bank

size

Device

size

The Video output pipeline of the STPC Consumer-

S interfaces directly to the internal digital TV en-

coder. It takes a 24 bit RGB non-interlaced pixel

stream and converts to a multiplexed 4:2:2 YCrCb

8 bit output stream, the logic includes a progres-

sive to interlaced scan converter and logic to in-

sert appropriate CCIR656 timing reference codes

into the output stream. It facilitates the high quality

display of VGA or full screen video streams re-

ceived via the Video input port to standard NTSC

or PAL televisions.

Number

Organisation

1Mx64

2Mx64

4Mx64

4

8

1Mx16

2Mx8

4Mx4

16Mbit

16

The SDRAM Controller supports buffered or un-

buffered SDRAM but not EDO or FPM modes.

SDRAMs must support Full Page Mode Type ac-

cess.

The digital PAL/NTSC encoder outputs interlaced

or non-interlaced video in PAL-B,D,G,H,I PAL-N,

PAL-M or NTSC-M standards and “NTSC- 4.43” is

also possible.

The STPC Memory Controller provides various

programmable SDRAM parameters to allow the

SDRAM interface to be optimized for different

processor bus speeds SDRAM speed grades and

CAS Latency.

The four frame (for PAL) or 2 frame (for NTSC)

burst sequences are internally generated, subcar-

rier generation being performed numerically with

CKREF as reference. Rise and fall times of syn-

chronisation tips and burst envelope are internally

controlled according to the relevant ITU-R and

SMPTE recommendations.

IDE INTERFACE

An industry standard EIDE (ATA 2) controller is

built into the STPC Consumer-S. The IDE port is

capable of supporting a total of four devices.

POWER MANAGEMENT

Video output signals are directed to four analog

output pins through internal D/A converters giving,

simultaneous R,G,B and composite CVBS and S-

VHS outputs.

The STPC Consumer-S core is compliant with the

Advanced Power Management (APM) specifica-

tion to provide a standard method by which the

BIOS can control the power used by personal

computers. The Power Management Unit module

(PMU) controls the power consumption providing

a comprehensive set of features that control the

power usage and supports compliance with the

United States Environmental Protection Agency's

Energy Star Computer Program. The PMU pro-

vides following hardware structures to assist the

software in managing the power consumption by

the system.

MEMORY CONTROLLER

The STPC handles the memory data (DATA) bus

directly, controlling from 2 to 128 MBytes. The

SDRAM controller supports accesses to the Mem-

ory Banks to/from the CPU (via the host), from the

VIP, to/from the CRTC, to the VIDEO & to/from the

GE. (Banks 0 to 3) which can be populated with ei-

ther single or double sided 72-bit (4 bit parity)

DIMMs. Parity is not supported.

- System Activity Detection.

- Three power down timers.

- Doze timer for detecting lack of system activity

The SDRAM controller only supports 64 bit wide

Memory Banks.

for short durations.

- Stand-by timer for detecting lack of system activ-

ity for medium durations

- Suspend timer for detecting lack of system activ-

ity for long durations.

- House-keeping activity detection.

- House-keeping timer to cope with short bursts of

house-keeping activity while dozing or in stand-by

Issue 1.1 - October 16, 2000

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GENERAL DESCRIPTION

state.

on state. The chip-set supports up to three power

down states: Doze state, Stand-by state and Sus-

pend mode. These correspond to decreasing lev-

els of power savings.

- Peripheral activity detection.

- Peripheral timer for detecting lack of peripheral

activity

- SUSP# modulation to adjust the system perform-

ance in various power down states of the system

including full power on state.

- Power control outputs to disable power from dif-

ferent planes of the board.

POWER DOWN

Power down puts the STPC Consumer-S into sus-

pend mode. The processor completes execution

of the current instruction, any pending decoded in-

structions and associated bus cycles. During the

suspend mode, internal clocks are stopped. Re-

moving power down, the processor resumes in-

struction fetching and begins execution in the in-

struction stream at the point it had stopped. Be-

cause of the static nature of the core, no internal

data is lost.

Lack of system activity for progressively longer

period of times is detected by the three power

down timers. These timers can generate SMI in-

terrupts to CPU so that the SMM software can put

the system in decreasing states of power con-

sumption. Alternatively, system activity in a power

down state can generate SMI interrupt to allow the

software to bring the system back up to full power

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Issue 1.1 - October 16, 2000

GENERAL DESCRIPTION

Figure 1-1. .Functionnal description.

Host

I/F

x86

Core

PCI BUS

PCI m/s

PMU

watchdog

ISA

m/s

IPC

82C206

IDE

I/F

PCI m/s

ISA Bus

Local

Local Bus

Bus I/F

Video Pipeline

- Pixel formating

- Scaler

- Colour Space CVT

Colour Key

Chroma Key

LUT

Monitor

SVGA

CRTC

TVO

- CSC

- FF

- CCIR

HW Cursor

GE

NTSC/PAL

Encoder

TV

CCIR Input

VIP

SDRAM

I/F

Issue 1.1 - October 16, 2000

7/59

GENERAL DESCRIPTION

Figure 1-2. Typical Application

Keyboard / Mouse

Serial Ports

Parallel Port

Floppy

Super I/O

RTC

Flash

2x EIDE

ISA

DMUX

MUX

IRQ

Monitor

SVGA

DMA.REQ

TV

S-VHS

RGB

PAL

STPC Consumer-S

DMA.ACK

NTSC

DMUX

Video

CCIR601

CCIR656

PCI

4x 16-bit SDRAMs

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Issue 1.1 - October 16, 2000

PIN DESCRIPTION

2 PIN DESCRIPTION

2.1 INTRODUCTION

Table 2-1. Signal Description

Group name

System Clocks & Resets (SYS)

SDRAM Controler

PCI interface

Qty

The STPC Consumer-S integrates most of the

functionalities of the PC architecture. As a result,

many of the traditional interconnections between

the host PC microprocessor and the peripheral

devices are totally internal to the STPC Consum-

er-S. This offers improved performance due to the

tight coupling of the processor core and these pe-

ripherals. As a result many of the external pin con-

nections are made directly to the on-chip peripher-

al functions.

7

95

56

ISA Interface

79

34

49

IDE Controller

89

Local Bus

Video Input

9

10

8

TV Output

VGA Monitor interface

Grounds

Figure 2-1 shows the STPC Consumer-S external

interfaces. It defines the main busses and their

function. Table 2-1 describes the physical imple-

mentation listing signals type and their functionali-

ty. Table 2-2 provides a full pin listing and descrip-

tion of pins. Table 2-5 provides a full listing of pin

locations of the STPC Consumer-S package by

physical connection.

74

29

4

V

DD

Miscelaneous

Unconnected

Total Pin Count

7

388

Several interface pins are multiplexed with

Note:

other functions, refer to Table 2-3 and Table 2-4

for further details

Figure 2-1. STPC Consumer-S External Interfaces

STPC CONSUMER-S

x86

PCI

SDRAM VGA VIP

TV

10

SYS

ISA/IDE/LB

96

8

9

56

7

89

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PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name

Dir

Description

System Power Good Input

Qty

BASIC CLOCKS AND RESETS

2

SYSRSTI#

I

1

2

SYSRSTO#

O

System Reset Output

XTALI

I

14.3MHz Crystal Input

XTALO

I/O

O

14.3MHz Crystal Output - External Oscillator Input

Host Clock (Test)

2

HCLK

DEV_CLK

24MHz Peripheral Clock (floppy drive)

27-135MHz Graphics Dot Clock

Power Supply for PLL Clocks

2

DCLK

I/O

1

V

_xxx_PLL

DD

MEMORY INTERFACE

MCLKI

I

O

I/O

O

Memory Clock Input

1

MCLKO

Memory Clock Output

CS#[3:0]

Memory Bank Chip Select

Memory Row & Column Address/Bank Address

Memory Row & Column Address

Memory Data

4

BA[0]

1

MA[10:0]

11

64

2

MD[63:0]

RAS#[1:0]

CAS#[1:0]

MWE#

Row Address Strobe

Column Address Strobe

Write Enable

2

1

DQM[7:0]

Data Input/Output Mask

8

PCI INTERFACE

2

PCI_CLKI

I

33MHz PCI Input Clock

33MHz PCI Output Clock (from internal PLL)

PCI Address / Data

Bus Commands / Byte Enables

Cycle Frame

1

32

4

1

3

4

PCI_CLKO

O

2

AD[31:0]

I/O

I

2

CBE#[3:0]

2

FRAME#

2

IRDY#

Initiator Ready

2

TRDY#

Target Ready

2

LOCK#

PCI Lock

2

DEVSEL#

I/O

O

Device Select

2

STOP#

Stop Transaction

2

PAR

Parity Signal Transactions

System Error

2

SERR#

2

PCI_REQ#[2:0]

I

PCI Request

2

PCI_GNT#[2:0]

O

PCI Grant

2

PCI_INT[3:0]

I

PCI Interrupt Request

5V Power Supply for PCI ESD protection

VDD5

I

ISA CONTROL

2

ISA_CLK

O

ISA Clock Output - Multiplexer Select Line For IPC

ISA Clock x2 Output - Multiplexer Select Line For IPC

ISA bus synchronisation clock

1

7

2

ISA_CLK2X

2

OSC14M

2

LA[23:17]

Unlatched Address

1

Note ; These pins must be connected to the 2.5Vpower supply. They must not be connected to the 3.45V supply.

2

Note ; Denotes that the pin is V (see Section 4 )

5T

3

Note ; see Table 2-5 for the detail of individual V signals

5T

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Issue 1.1 - October 16, 2000

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name

Dir

I/O

O

Description

Qty

20

16

1

SA[19:0]

SD[15:0]

Latched Address

Data Bus

2

ALE

Address Latch Enable

2

MEMR# , MEMW#

I/O

O

Memory Read and Memory Write

System Memory Read and Memory Write

I/O Read and Write

2

SMEMR# , SMEMW#

2

IOR# , IOW#

I/O

I

2

MCS16# , IOCS16#

Memory/IO Chip Select16

System Bus High Enable

Zero Wait State

2

BHE#

O

1

2

ZWS#

I

1

2

REF#

O

Refresh Cycle.

1

2

MASTER#

I

Add On Card Owns Bus

Address Enable

1

2

AEN

O

1

2

IOCHCK#

I

I/O Channel Check.

1

2

IOCHRDY

I/O

O

I/O Channel Ready (ISA) - Busy/Ready (IDE)

ISA/IDE Selection

1

2

ISAOE#

1

2

GPIOCS#

I/O

I

General Purpose Chip Select

Time-Multiplexed Interrupt Request

Time-Multiplexed DMA Request

Encoded DMA Acknowledge

ISA Terminal Count

1

2

IRQ_MUX[3:0]

4

2

DREQ_MUX[1:0]

I

2

DACK_ENC[2:0]

O

3

2

TC

O

1

2

RTCAS#

O

Real Time Clock Address Strobe

ROM/RTC Chip Select

1

2

RMRTCCS#

I/O

1

2

KBCS#

Keyboard Chip Select

1

2

RTCRW#

RTC Read/Write

1

2

RTCDS#

RTC Data Strobe

1

LOCAL BUS

PA[21:0]

O

I/O

O

I

Address Bus

22

16

2

PD[15:0]

Data Bus

PRD1#,PRD0#

PWR1#,PWR0#

PRDY#

Peripheral Read Control

Peripheral Write Control

Data Ready

2

1

FCS1#, FCS0#

IOCS#[3:0]

O

Flash Chip Select

I/O Chip Select

2

4

IDE CONTROL

DA[2:0]

O

I/O

O

I

Address Bus

3

16

4

DD[15:0]

Data Bus

PCS3#,PCS1#,SCS3#,SCS1#

DIORDY

Primary & Secondary Chip Selects

Data I/O Ready

1

2

PIRQ , SIRQ

Primary & Secondary Interrupt Request

Primary & Secondary DMA Request

Primary & Secondary DMA Acknowledge

Primary & Secondary I/O Channel Read

Primary & Secondary I/O Channel Write

2

PDRQ , SDRQ

I

2

PDACK# , SDACK#

O

2

PDIOR# , SDIOR#

2

PDIOW# , SDIOW#

2

1

Note ; These pins must be connected to the 2.5Vpower supply. They must not be connected to the 3.45V supply.

2

Note ; Denotes that the pin is V (see Section 4 )

5T

3

Note ; see Table 2-5 for the detail of individual V signals

5T

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PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name

Dir

Description

Qty

MONITOR INTERFACE

RED, GREEN, BLUE

O

I

Analog Red, Green, Blue

Vertical Sync

3

1

2

VSYNC

2

HSYNC

Horizontal Sync

DAC Voltage reference

Resistor Set

VREF_DAC

RSET

I

COMP

I

Compensation

VIDEO INPUT

2

VCLK

I

27-33MHz Video Input Port Clock

1

8

2

VIN[7:0]

CCIR 601 or 656 YUV Video Data Input

ANALOG TV OUTPUT

2

RED_TV , GREEN_TV , BLUE_TV

O

Analog RGB or S-VHS outputs

Analog video composite output

Reference current of 9bit DAC for CVBS

Reference voltage of 9bit DAC for CVBS

Reference current of 8bit DAC for R,G,B

Reference voltage of 8bit DAC for R,G,B

Analog Vss for DAC

3

1

2

CVBS

O

IREF1_TV

VREF1_TV

I

2

IREF2_TV

I

2

VREF2_TV

I

VSSA_TV

VDDA_TV

I

Analog Vdd for DAC

2

VCS

I/O

Composite Synch or Horizontal line SYNC output

Frame Synchronisation

2

ODD_EVEN

MISCELLANEOUS

2

SPKRD

O

I/O

I

Speaker Device Output

1

2

SCL

I²C Interface - Clock / Can be used for VGA DDC[1] signal

I²C Interface - Data / Can be used for VGA DDC[0] signal

Reserved (Test pin)

2

SDA

2

SCAN_ENABLE

1

Note ; These pins must be connected to the 2.5Vpower supply. They must not be connected to the 3.45V supply.

2

Note ; Denotes that the pin is V (see Section 4 )

5T

3

Note ; see Table 2-5 for the detail of individual V signals

5T

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Issue 1.1 - October 16, 2000

PIN DESCRIPTION

2.2 SIGNAL DESCRIPTIONS

display controller. This input should be a buffered

version of the MCLKO signal with the track lengths

between the buffer and the pin matched with the

track lengths between the buffer and the Memory

Banks.

2.2.1 BASIC CLOCKS AND RESETS

SYSRSTI#

System Reset/Power good. This input

is low when the reset switch is depressed. Other-

wise, it reflects the power supply’s power good

signal. This input is asynchronous to all clocks,

and acts as a negative active reset. The reset cir-

cuit initiates a hard reset on the rising edge of this

signal.

MCLKO

Memory Clock Output. This clock drives

the Memory Banks on board and is generated

from an internal PLL.The default value is 80MHz.

CS#[3:0]

Chip Select These signals are used to

disable or enable device operation by masking or

enabling all SDRAM inputs except MCLK, CKE,

and DQM.

SYSRSTO#

Reset Output to System. This is the

system reset signal and is used to reset the rest of

the components (not on Host bus) in the system.

The ISA bus reset is an externally inverted buff-

ered version of this output and the PCI bus reset is

an externally buffered version of this output.

BA[0]

Memory Bank Address.

MA[10:0]

Memory Address. Multiplexed row and

column address lines.

XTALI

14.3MHz Crystal Input

MD[63:0] Memory Data. This is the 64-bit memory

data bus. MD[40-0] are read by the device strap

option registers during rising edge of SYSRSTI#.

XTALO

14.3MHz Crystal Output. These pins are

connected to the 14.318 MHz crystal to provide

the reference clock for the internal frequency syn-

thesizer to generate all the other clocks.

RAS#[1:0] Row Address Strobe. These signals

enable row access and precharge. Row address

is latched on rising edge of MCLK when RAS# is

low.

A 14.318 MHz Series Cut Crystal should be con-

nected between these two pins. Balance capaci-

tors of 15 pF should also be added. In the event of

an external quarzt oscillator providing the master

clock signal to the STPC Consumer-S device, the

TTL signal should be provided on XTALO.

These sig-

CAS#[1:0] Column Address Strobe.

nals enable column access. Column address is

latched on rising edge of MCLK when CAS# is

low.

HCLK

Host Clock. This clock supplies the CPU

and the host related blocks. This clock can e dou-

bled inside the CPU and is intended to operate in

the range of 25 to 100 MHz. This clock in generat-

ed internally from a PLL but can be driven directly

from the external system.

MWE#

Write Enable. Write enable specifies

whether the memory access is a read (MWE# = H)

or a write (MWE# = L).

DQM#[7:0]

Data Mask. Makes data output Hi-Z

after the clock and masks the SDRAM outputs. It

blocks SDRAM data input when DQM active.

DEV_CLK

24MHz Peripheral Clock. This 24MHZ

signal is provided as a convenience for the system

integration of a Floppy Disk driver function in an

external chip.

2.2.3 PCI INTERFACE

DCLK

135MHz Dot Clock. This is the Dot clock,

PCI_CLKI

33MHz PCI Input Clock. This signal is

the PCI bus clock input and should be driven from

the PCI_CLKO pin.

which drives graphics display cycles. Its frequency

can go from 8MHz (using internal PLL) up to 135

MHz, and it is required to have a worst case duty

cycle of 60-40.

This signal is either driven by the internal pll (VGA)

or an external 27MHz oscillator (when the com-

posite video output is enabled). The direction can

be controlled by a strap option or an internal regis-

ter bit.

PCI_CLKO

33MHz PCI Output Clock. This is the

master PCI bus clock output.

AD[31:0]

PCI Address/Data. This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and data phase of write transactions. It is

driven by the target during data phase of read

transactions. Signals AD[12:11] for internal use

only. Not to be used for External PCI devices.

2.2.2 MEMORY INTERFACE

MCLKI

Memory Clock Input. This clock is driving

the SDRAM controller, the graphics engine and

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13/59

PIN DESCRIPTION

CBE#[3:0] Bus Commands/Byte Enables. These

are the multiplexed command and byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

phase they carry the byte enable information.

These pins are inputs when a PCI master other

than the STPC Consumer-S owns the bus and

outputs when the STPC Consumer-S owns the

bus.

SERR# System Error. This is the system error sig-

nal of the PCI bus. It may, if enabled, be asserted

for one PCI clock cycle if target aborts a STPC

Consumer-S initiated PCI transaction. Its asser-

tion by either the STPC Consumer-S or by another

PCI bus agent will trigger the assertion of NMI to

the host CPU. This is an open drain output.

PCI_REQ#[2:0]

PCI Request.

This pin are the

three external PCI master request pins. They indi-

cates to the PCI arbiter that the external agents

desire use of the bus.

FRAME# Cycle Frame. This is the frame signal of

the PCI bus. It is an input when a PCI master owns

the bus and is an output when STPC Consumer-S

owns the PCI bus.

PCI_GNT#[2:0]

PCI Grant.

These pins indicate

that the PCI bus has been granted to the master

requesting it on its PCI_REQ#.

IRDY# Initiator Ready. This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Consumer-S initiates a bus cycle on the

PCI bus. It is used as an input during the PCI cy-

cles targeted to the STPC Consumer-S to deter-

mine when the current PCI master is ready to

complete the current transaction.

PCI_INT[3:0]

PCI Interrupt Request.

These are

the PCI bus interrupt signals.

VDD5

5V Power Supply.

These power pins are

necessary for 5V ESD protection. In case the PCI

bus is used in 3.45V only, these pins can be con-

nected to 3.45V.

TRDY# Target Ready. This is the target ready sig-

nal of the PCI bus. It is driven as an output when

the STPC Consumer-S is the target of the current

bus transaction. It is used as an input when STPC

Consumer-S initiates a cycle on the PCI bus.

2.2.4 ISA INTERFACE

ISA_CLK, ISA_CLKX2 ISA Clock x1, x2. These

pins generate the Clock signal for the ISA bus and

a Doubled Clock signal. They are also used as the

multiplexor control lines for the Interrupt Controller

Interrupt input lines. ISA_CLK is generated from

either PCICLK/4 or OSC14M/ 2.

LOCK# PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

DEVSEL# I/O Device Select. This signal is used

as an input when the STPC Consumer-S initiates

a bus cycle on the PCI bus to determine if a PCI

slave device has decoded itself to be the target of

the current transaction. It is asserted as an output

either when the STPC Consumer-S is the target of

the current PCI transaction or when no other de-

vice asserts DEVSEL# prior to the subtractive de-

code phase of the current PCI transaction.

OSC14M ISA bus synchronisation clock Output.

This is the buffered 14.318 Mhz clock for the ISA

bus.

LA[23:17] Unlatched Address. When the ISA bus

is active, these pins are ISA Bus unlatched ad-

dress for 16-bit devices. When ISA bus is ac-

cessed by any cycle initiated from PCI bus, these

pins are in output mode. When an ISA bus master

owns the bus, these pins are in input mode.

STOP# Stop Transaction. Stop is used to imple-

ment the disconnect, retry and abort protocol of

the PCI bus. It is used as an input for the bus cy-

cles initiated by the STPC Consumer-S and is

used as an output when a PCI master cycle is tar-

geted to the STPC Consumer-S.

SA[19:0] ISA Address Bus. System address bus

of ISA on 8-bit slot. These pins are used as an in-

put when an ISA bus master owns the bus and are

outputs at all other times.

PAR Parity Signal Transactions. This is the parity

signal of the PCI bus. This signal is used to guar-

antee even parity across AD[31:0], CBE#[3:0],

and PAR. This signal is driven by the master dur-

ing the address phase and data phase of write

transactions. It is driven by the target during data

phase of read transactions. (Its assertion is identi-

cal to that of the AD bus delayed by one PCI clock

cycle)

SD[15:0] I/O Data Bus. These pins are the exter-

nal databus to the ISA bus.

ALE Address Latch Enable. This is the address

latch enable output of the ISA bus and is asserted

by the STPC Consumer-S to indicate that LA23-

17, SA19-0, AEN and SBHE# signals are valid.

The ALE is driven high during refresh, DMA mas-

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Issue 1.1 - October 16, 2000

PIN DESCRIPTION

ter or an ISA master cycles by the STPC Consum-

er-S. ALE is driven low after reset.

Refresh Cycle. This is the refresh command

REF#

signal of the ISA bus. It is driven as an output

when the STPC Consumer-S performs a refresh

cycle on the ISA bus. It is used as an input when

an ISA master owns the bus and is used to trigger

a refresh cycle.

The STPC Consumer-S performs a pseudo hid-

den refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

in external buffers. The host bus is then relin-

quished while the refresh cycle continues on the

ISA bus.

MEMR#

Memory Read. This is the memory read

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

MEMW#

Memory Write. This is the memory write

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

MASTER#

Add On Card Owns Bus. This signal is

active when an ISA device has been granted bus

ownership.

SMEMR#

System Memory Read. The STPC Con-

sumer-S generates SMEMR# signal of the ISA

bus only when the address is below one megabyte

or the cycle is a refresh cycle.

AEN

Address Enable. Address Enable is enabled

when the DMA controller is the bus owner to indi-

cate that a DMA transfer will occur. The enabling

of the signal indicates to IO devices to ignore the

IOR#/IOW# signal during DMA transfers.

SMEMW#

System Memory Write. The STPC Con-

sumer-S generates SMEMW# signal of the ISA

bus only when the address is below one mega-

byte.

IOCHCK#

IO Channel Check. IO Channel Check

This is the IO read command sig-

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal be-

comes active upon seeing IOCHCK# active if the

corresponding bit in Port B is enabled.

IOR# I/O Read.

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

IOW#

I/O Write. This is the IO write command sig-

IOCHRDY

Channel Ready. IOCHRDY is the IO

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

channel ready signal of the ISA bus and is driven

as an output in response to an ISA master cycle

targeted to the host bus or an internal register of

the STPC Consumer-S. The STPC Consumer-S

monitors this signal as an input when performing

an ISA cycle on behalf of the host CPU, DMA

master or refresh.

MCS16#

Memory Chip Select16. This is the de-

code of LA23-17 address pins of the ISA address

bus without any qualification of the command sig-

nal lines. MCS16# is always an input. The STPC

Consumer-S ignores this signal during IO and re-

fresh cycles.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Consumer-

S since the access to the system memory can be

considerably delayed due UMA architecture.

IOCS16#

IO Chip Select16. This signal is the de-

code of SA15-0 address pins of the ISA address

bus without any qualification of the command sig-

nals. The STPC Consumer-S does not drive

IOCS16# (similar to PC-AT design). An ISA mas-

ter access to an internal register of the STPC Con-

sumer-S is executed as an extended 8-bit IO cy-

cle.

Bidirectional OE Control. This signal con-

trols the OE signal of the external transceiver that

connects the IDE DD bus and ISA SA bus.

ISAOE#

GPIOCS#

I/O General Purpose Chip Select. This

output signal is used by the external latch on ISA

bus to latch the data on the SD[7:0] bus. The latch

can be use by PMU unit to control the external pe-

ripheral devices or any other desired function.

BHE#

System Bus High Enable. This signal, when

asserted, indicates that a data byte is being trans-

ferred on SD15-8 lines. It is used as an input when

an ISA master owns the bus and is an output at all

other times.

IRQ_MUX[3:0] Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They

have to be encoded before connection to the

STPC Consumer-S using ISACLK and ISACLKX2

as the input selection strobes.

ZWS#

Zero Wait State. This signal, when assert-

ed by addressed device, indicates that current cy-

cle can be shortened.

Note that IRQ8B, which by convention is connect-

ed to the RTC, is inverted before being sent to the

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15/59

PIN DESCRIPTION

interrupt controller, so that it may be connected di-

rectly to the IRQ pin of the RTC.

PD[15:0]

Data Bus.

This is the 16-bit data bus.

D[7:0] is the LSB and PD[15:8] is the MSB.

DREQ_MUX[1:0] ISA Bus Multiplexed DMA Re-

PRD#[1:0] Read Control output. PRD0# is used

to read the LSB and PRD1# to read the MSB.

quest.

These are the ISA bus DMA request sig-

nals. They are to be encoded before connection to

the STPC Consumer-S using ISACLK and

ISACLKX2 as the input selection strobes.

PWR#[1:0]

Write Control output.

to write the LSB and PWR1# to write the MSB.

PWR0# is used

DACK_ENC[2:0] DMA Acknowledge. These are

the ISA bus DMA acknowledge signals. They are

encoded by the STPC Consumer-S before output

and should be decoded externally using ISACLK

and ISACLKX2 as the control strobes.

PRDY# Data Ready input. This signal is used to

create wait states on the bus. When HIGH it com-

pletes the cycle without any wait state added.

FCS#[1:0]

Flash Chip Select output.

These are

the Programmable Chip Select signals for up to 2

TC ISA Terminal Count. This is the terminal count

output of the DMA controller and is connected to

the TC line of the ISA bus. It is asserted during the

last DMA transfer, when the byte count expires.

banks of Flash memory.

IOCS#[3:0]

I/O Chip Select output.

These are the

Programmable Chip Select signals for up to 4 ex-

ternal I/O devices.

2.2.5 X-Bus Interface pins

2.2.7 IDE INTERFACE

RTCAS# Real time clock address strobe. This sig-

nal is asserted for any I/O write to port 70H.

DA[2:0]

Address.

These signals are connected to

DA[2:0] of IDE devices directly or through a buffer.

If the toggling of signals are to be masked during

ISA bus cycles, they can be externally ORed with

ISAOE# before being connected to the IDE devic-

es.

RMRTCCS# ROM/Real Time clock chip select.

This signal is asserted if a ROM access is decod-

ed during a memory cycle. It should be combined

with MEMR# or MEMW# signals to properly ac-

cess the ROM. During a IO cycle, this signal is as-

serted if access to the Real Time Clock (RTC) is

decoded. It should be combined with IOR or IOW#

signals to properly access the real time clock.

DD[15:0]

Databus.

When the IDE bus is active,

they serve as IDE signals DD[15:0]. IDE devices

are connected to SA[19:8] directly and ISA bus is

connected to these pins through two LS245 trans-

ceivers as described in Figure 2-2.

KBCS# Keyboard Chip Select. This signal is as-

serted if a keyboard access is decoded during a I/

O cycle.

PCS1#, PCS3#

Primary Chip Select.

These sig-

nals are used as the active high primary master &

slave IDE chip select signals. These signals must

RTCRW# Real Time Clock RW. This pin is a multi-

function pin. When ISAOE# is active, this signal is

used as RTCRW#. This signal is asserted for any

I/O write to port 71H.

#

be externally ANDed with the ISAOE signal be-

fore driving the IDE devices to guarantee it is ac-

tive only when ISA bus is idle.

RTCDS# Real Time Clock DS. This pin is a multi-

function pin. When ISAOE# is active, this signal is

used as RTCDS. This signal is asserted for any I/

O read to port 71H.

SCS1#, SCS3# Secondary Chip Select. These

signals are used as the active high secondary

master & slave IDE chip select signals. These sig-

nals must be externally ANDed with the ISAOE

signal before driving the IDE devices to guarantee

it is active only when ISA bus is idle.

#

Note: RMRTCCS#, KBCS#, RTCRW# and

RTCDS# signals must be ORed externally with

ISAOE# and then connected to the external de-

vice. An LS244 or equivalent function can be used

if OE# is connected to ISAOE# and the output is

provided with a weak pull-up resistor as shown in

Figure 2-2.

DIORDY

Busy/Ready.

nal DIORDY.

This pin serves as IDE sig-

PIRQ

SIRQ

Primary Interrupt Request.

Secondary Interrupt Request.

Interrupt request from IDE channels.

2.2.6 LOCAL BUS

PA[21:0] Address Bus Output.

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Issue 1.1 - October 16, 2000

PIN DESCRIPTION

PDRQ

SDRQ

Primary DMA Request.

Secondary DMA Request.

DMA request from IDE channels.

2.2.10 TV OUTPUT

Analog video outputs synchro-

nized with CVBS. This output is current-driven and

must be connected to analog ground over a load

RED_TV / C_TV

PDACK#

SDACK#

Primary DMA Acknowledge.

Secondary DMA Acknowledge.

DMA acknowledge to IDE channels.

resistor (R

). Following the load resistor, a

LOAD

simple analog low pass filter is recommended. In

S-VHS mode, this is the Chrominance Output.

PDIOR#, PDIOW#

SDIOR#, SDIOW#

Primary I/O Read & Write.

Secondary I/O Read & Write.

Primary & Secondary channel read & write.

GREEN_TV / Y_TV Analog video outputs syn-

chronized with CVBS. This output is current-driv-

en and must be connected to analog ground over

2.2.8 Monitor Interface

a load resistor (R

). Following the load resis-

LOAD

tor, a simple analog low pass filter is recommend-

ed. In S-VHS mode, this is the Luminance Output.

RED, GREEN, BLUE

RGB Video Outputs. These

are the 3 analog color outputs from the RAM-

DACs. These signals are sensitive to interference,

therefore they need to be properly shielded.

BLUE_TV / CVBS

Analog video outputs synchro-

nized with CVBS. This output is current-driven and

must be connected to analog ground over a load

VSYNC

Vertical Synchronisation Pulse. This is

the vertical synchronization signal from the VGA

controller.

resistor (R

). Following the load resistor, a

LOAD

simple analog low pass filter is recommended. In

S-VHS mode, this is a second composite output.

HSYNC

Horizontal Synchronisation Pulse. This is

the horizontal synchronization signal from the

VGA controller.

CVBS

Analog video composite output (luminance/

chrominance). CVBS is current-driven and must

be connected to analog ground over a load resis-

tor (R

). Following the load resistor, a simple

LOAD

An external

analog low pass filter is recommended.

VREF_DAC DAC Voltage reference.

voltage reference is connected to this pin to bias

the DAC.

IREF1_TV

IREF2_TV

Ref. current for CVBS 10-bit DAC.

RSET

Resistor Current Set. This reference cur-

Reference current for RGB 9-bit DAC.

rent input to the RAMDAC is used to set the full-

scale output of the RAMDAC.

VREF1_TV Ref. voltage for CVBS 10-bit DAC.

Reference voltage for RGB 9-bit DAC.

COMP

Compensation. This is the RAMDAC com-

VREF2_TV

VSSA_TV Analog V

pensation pin. Normally, an external capacitor

(typically 10nF) is connected between this pin and

for DACs.

SS

V

to damp oscillations.

DD

VDDA_TV

Analog V

DD

2.2.9 VIDEO INPUT

VCS

Line synchronisation Output. This pin is an

input in ODDEV+HSYNC or VSYNC + HSYNC or

VSYNC slave modes and an output in all other

modes (master/slave)

VCLK

Pixel Clock Input.This signal is used to syn-

chronise data being transfered from an external

video device to either the frame buffer, or alterna-

tively out the TV output in bypass mode. This pin

can be sourced from STPC if no external VCLK is

detected, or can be input from an external video

clock source.

ODD_EVEN

Frame Synchronisation Ourput. This

pin supports the Frame synchronisation signal. It

is an input in slave modes, except when sync is

extracted from YCrCbdata, and an output in mas-

ter mode and when sync is extracted from YCrCb

data

VIN[7:0]

YUV Video Data Input CCIR 601 or 656.

The signal is synchronous to rising edge of DCLK.

The default polarity for this pin is:

- odd (not-top) field : LOW level

- even (bottom) field : HIGH level

Time multiplexed 4:2:2 luminance and chromi-

nance data as defined in ITU-R Rec601-2 and

Rec656 (except for TTL input levels). This bus

typically carries a stream of Cb,Y,Cr,Y digital vid-

eo at VCLK frequency, clocked on the rising edge

(by default) of VCLK.

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17/59

PIN DESCRIPTION

2

2.2.11 MISCELLANEOUS

DDC capabilities. They conform to I C electrical

specifications, they have open-collector output

drivers which are internally connected to V

through pull-up resistors.

They can be used for the DDC1 (SCL) and DDC0

(SDA) lines of the VGA interface.

SPKRD Speaker Drive. This the output to the

speaker and is AND of the counter 2 output with

bit 1 of Port 61, and drives an external speaker

driver. This output should be connected to 7407

type high voltage driver.

DD

SCAN_ENABLE Reserved. Must be connected to

ground.

SCL, SDA I²C Interface. These bidirectional pins

are connected to CRTC register 3Fh to implement

18/59

Issue 1.1 - October 16, 2000

PIN DESCRIPTION

Table 2-3. ISA / IDE dynamic multiplexing

Table 2-4. ISA / Local Bus pin sharing

.

ISA BUS

(ISAOE# = 0)

IDE

(ISAOE# = 1)

ISA / IPC

SD[15:0]

LOCAL BUS

PD[15:0]

RMRTCCS#

DD[15]

DREQ_MUX[1:0]

SMEMR#

PA[21:20]

PA[19]

KBCS#

DD[14]

DD[13]

DD[12]

DD[11:0]

SCS3#

SCS1#

PCS3#

PCS1#

DA[2:0]

DIORDY

RTCRW#

RTCDS#

SA[19:8]

LA[23]

MEMW#

PA[18]

BHE#

PA[17]

AEN

PA[16]

ALE

PA[15]

LA[22]

MEMR#

PA[14]

SA[21]

IOR#

PA[13]

SA[20]

IOW#

PA[12]

LA[19:17]

IOCHRDY

REF#

PA[11]

IOCHCK#

PA[10]

GPIOCS#

PA[9]

ZWS#

PA[8]

SA[7:4]

PA[7:4]

PA[3:0]

PRDY

TC, DACK_ENC[2:0]

SA[3]

ISAOE#,SA[2:0]

DEV_CLK, RTCAS#

IOCS16#, MASTER#

SMEMW#, MCS16#

ISACLK, ISA_CLK2X

IOCS#[3:0]

FCS#[1:0]

PRD#[1:0]

PWR#[1:0]

Figure 2-2. Typical ISA/IDE Demultiplexing

74LS245

A

B

STPC bus / DD[15:0]

RMRTCCS#

KBCS#

MASTER#

ISAOE#

DIR

OE

RTCRW#

RTCDS

SA[19:8]

PCS1#

PCS3#

LA[22]

LA[23]

SCS1#

SCS3#

LA[22]

LA[23]

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19/59

PIN DESCRIPTION

Table 2-5. Pinout.

Pin #

U3

Pin name

MD[10]

Pin #

T25

Pin name

MD[59]

Pin #

AF3

Pin name

V1

MD[11]

MD[12]

MD[13]

MD[14]

MD[15]

MD[16]

MD[17]

MD[18]

MD[19]

MD[20]

MD[21]

MD[22]

MD[23]

MD[24]

MD[25]

MD[26]

MD[27]

MD[28]

MD[29]

MD[30]

MD[31]

MD[32]

MD[33]

MD[34]

MD[35]

MD[36]

MD[37]

MD[38]

MD[39]

MD[40]

MD[41]

MD[42]

MD[43]

MD[44]

MD[45]

MD[46]

MD[47]

MD[48]

MD[49]

MD[50]

MD[51]

MD[52]

MD[53]

MD[54]

MD[55]

MD[56]

MD[57]

MD[58]

U24

T26

R25

R26

F24

D25

B20

C20

B19

A19

C19

B18

A18

B17

C18

A17

D17

B16

C17

B15

A15

C16

B14

D15

A14

B13

D13

A13

C14

B12

C13

A12

C12

A11

D12

B10

C11

A10

D10

C10

A9

MD[60]

MD[61]

MD[62]

MD[63]

PCI_CLKI

PCI_CLKO

AD[0]

SYSRSTI#

SYSRSTO#

XTALI

W2

AE4

V3

A3

Y2

C4

XTALO

HCLK

W4

G23

Y1

H24

DEV_CLK

DCLK

W3

AD11

AF15

AB23

AE16

AD15

AF16

AE17

AD16

AF17

AE18

AD17

AF18

AE19

AE20

AC19

AF22

AD21

AE24

AD23

AF23

AD22

AE21

AC20

AF20

AD19

AF21

AD20

AE22

AE23

AF19

AD18

AC22

R1

AA2

Y4

AD[1]

MCLKI

MCLKO

MA[0]

AD[2]

AA1

Y3

AD[3]

AD[4]

MA[1]

AB2

AB1

AA3

AB4

AC1

AB3

AD2

AC3

AD1

AF2

AF24

AE26

AD25

AD26

AC25

AC24

AC26

AB25

AB24

AB26

AA25

Y23

AA24

AA26

Y25

Y26

Y24

W25

V23

W26

W24

V25

V26

U25

V24

U26

U23

AD[5]

MA[2]

AD[6]

MA[3]

AD[7]

MA[4]

AD[8]

MA[5]

AD[9]

MA[6]

AD[10]

AD[11]

AD[12]

AD[13]

AD[14]

AD[15]

AD[16]

AD[17]

AD[18]

AD[19]

AD[20]

AD[21]

AD[22]

AD[23]

AD[24]

AD[25]

AD[26]

AD[27]

AD[28]

AD[29]

AD[30]

AD[31]

CBE[0]

CBE[1]

CBE[2]

CBE[3]

FRAME#

TRDY#

IRDY#

STOP#

DEVSEL#

PAR

MA[7]

MA[8]

MA[9]

MA[10]

BA[0]

CS#[0]

CS#[1]

CS#[2]

CS#[3]

RAS#[0]

RAS#[1]

CAS#[0]

CAS#[1]

DQM#[0]

DQM#[1]

DQM#[2]

DQM#[3]

DQM#[4]

DQM#[5]

DQM#[6]

DQM#[7]

MWE#

MD[0]

T2

MD[1]

R3

MD[2]

B8

T1

MD[3]

A8

R4

MD[4]

B7

U2

MD[5]

D8

T3

MD[6]

A7

U1

MD[7]

C8

U4

MD[8]

B6

V2

MD[9]

20/59

Issue 1.1 - October 16, 2000

PIN DESCRIPTION

Pin #

D7

Pin name

SERR#

Pin #

J24

Pin name

Pin #

D1

Pin name

SDACK#

SD[9]

A6

LOCK#

G25

H23

D24

C26

A25

B24

SD[10]

SD[11]

SD[12]

SD[13]

SD[14]

SD[15]

E2

E4

E3

E1

PDIOR#

D20

C21

A21

C22

A22

B21

A5

PCI_REQ#[0]

PCI_REQ#[1]

PCI_REQ#[2]

PCI_GNT#[0]

PCI_GNT#[1]

PCI_GNT#[2]

PCI_INT[0]

PCI_INT[1]

PCI_INT[2]

PCI_INT[3]

PDIOW#

SDIOR#

SDIOW#

AF9

RED

AE9

AD8

AC5

AE5

AC10

AE10

AD7

AF8

GREEN

AD4

AF4

C9

ISA_CLK

ISA_CLK2X

OSC14M

ALE

BLUE

C6

VSYNC

B4

HSYNC

D5

P25

AE8

R23

P26

R24

N25

N23

N26

P24

N24

M26

M25

L25

M24

L26

T24

M23

A4

VREF_DAC

RSET

ZWS#

F2

LA[17]/DA[0]

LA[18]/DA[1]

LA[19]/DA[2]

LA[20]/PCS1#

LA[21]/PCS3#

LA[22]/SCS1#

LA[23]/SCS3#

BHE#

COMP

G4

F3

MEMR#

VDD_DAC1

VDD_DAC2

VSS_DAC1

VSS_DAC2

MEMW#

SMEMR#

SMEMW#

IOR#

AD9

AC9

AF10

F1

G2

G1

H2

J4

IOW#

AE15

AD5

AF7

AF5

AE6

AC7

AD6

AF6

AE7

VCLK

VIN[0]

VIN[1]

VIN[2]

VIN[3]

VIN[4]

VIN[5]

VIN[6]

VIN[7]

2

SA[0]

MCS16#

IOCS16#

MASTER#

REF#

2

H1

H3

J2

SA[1]

2

SA[2]

2

SA[3]

2

J1

SA[4]

AEN

2

K2

SA[5]

IOCHCK#

IOCHRDY

ISAOE#

2

J3

SA[6]

2

K1

SA[7]

2

K4

SA[8]

RTCAS#

RTCDS#

RTCRW#

RMRTCCS#

GPIOCS#

IRQ_MUX[0]

IRQ_MUX[1]

IRQ_MUX[2]

IRQ_MUX[3]

DREQ_MUX[0]

DREQ_MUX[1]

DACK_ENC[0]

DACK_ENC[1]

DACK_ENC[2]

TC

2

L2

SA[9]

P3

AD10

AF11

AE12

AF14

AE11

AF12

AE14

AC14

AD12

AE13

AC12

AF13

RED_TV

2

K3

SA[10]

R2

GREEN_TV

BLUE_TV

CVBS

2

L1

SA[11]

P1

2

M2

M1

L3

SA[12]

AE3

E23

D26

E24

C25

A24

B23

C23

A23

B22

D22

N3

2

SA[13]

IREF1_TV

VREF1_TV

IREF2_TV

VREF2_TV

VDDA_TV

VCS

2

SA[14]

2

N2

M4

M3

P2

SA[15]

2

SA[16]

2

SA[17]

2

SA[18]

2

P4

SA[19]

ODD_EVEN

VSSA_TV

K25

L24

K26

K23

J25

K24

J26

H25

H26

SD[0]

SD[1]

SD[2]

SD[3]

SD[4]

SD[5]

SD[6]

SD[7]

SD[8]

C5

B5

C7

B3

SPKRD

SCL

KBCS#

B1

PIRQ

SDA

C2

SIRQ

SCAN_ENABLE

C1

PDRQ

D2

SDRQ

G24

VDD_CPUCLK_PLL

VDD_DCLK_PLL

D3

PDACK#

AD13

Issue 1.1 - October 16, 2000

21/59

PIN DESCRIPTION

Pin #

F25

Pin name

Pin #

W23

Pin name

VDD_DEVCLK_PLL

VSS

AC17

AC15

F26

A16

B11

B9

VDD_MCLKI_PLL

AC4

VDD_MCLKO_PLL

VDD_HCLK_PLL

VDD5

VDD

AC8

AC13

AC18

AC23

AD3

D18

D6

AD14

AD24

AE1:2

AE25

AF1

D11

D16

D21

F4

VDD

AF25

AF26

F23

L4

VDD

L23

VDD

A20

C15

G3

Unconnected

T4

VDD

T23

AA4

AA23

AC6

AC11

AC16

AC21

VDD

G26

N1

VDD

W1

AC2

VDD

E25

VSS_DLL

VSS

E26

A1:2

A26

B2

B25:26

C3

C24

D4

D9

D14

D19

D23

H4

J23

L11:16

M11:16

N4

N11:16

P11:16

P23

R11:16

T11:16

V4

22/59

Issue 1.1 - October 16, 2000

STRAP OPTIONS

3 STRAP OPTIONS

This chapter defines the STPC Consumer-S Strap

Options and their location

Memory

Data

Lines

Actual

Settings

Refer to

Designation

Location

Set to ’0’

Set to ’1’

MD0

MD1

-

Reserved

Index 4A, bit 0

Index 4A, bit 1

Index 4A, bit 2

Index 4A, bit 3

Index 4A, bit 4

Index 4A, bit 5

Index 4A, bit 6

Index 4A, bit 7

Index 4B, bit 0

Index 4B, bit 1

Index 4B, bit 2

Index 4B, bit 3

Index 4B, bit 4

Index 4B, bit 5

Index 4B, bit 6

Index 4B, bit 7

-

MD2

-

Reserved

-

MD3

-

Reserved

-

MD4

-

Reserved

-

MD5

-

Reserved

-

MD6

-

Reserved

-

MD7

-

Reserved

-

MD8

-

Reserved

-

MD9

-

Reserved

-

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD22

MD23

MD24

MD25

MD26

-

Reserved

-

Reserved

-

Reserved

-

Reserved

-

Reserved

-

Reserved

-

Normal

HCLK / 2

Internal

-

ISA Control

PCI Clock

Host Clock

Master#

Index 4C,bit0 User defined Test mode

Index 4C,bit 1 User defined HCLK / 3

Index 4C,bit 2 User defined External

Index 4C,bit 3 User defined External

Index 4C, bit4 User defined External

PCI_CLKO Divisor

HCLK Pad Direction

Memory Clock MCLK Pad Direction

Dot Clock

DCLK Pad Direction

Reserved

-

Index 5F, bit 0

Index 5F, bit 1

Index 5F,bit 2

Pull up

-

Reserved

-

Reserved

-

HCLK

HCLK PLL Speed

Index 5F,bit 3 User defined

Index 5F,bit 4 User defined

Index 5F,bit 5 User defined

000

001

010

011

100

101

110

111

-

25 MHz

33 MHz

100 MHz

50 MHz

60 MHz

66 MHz

75 MHz

90 MHz

-

MD27

MD28

MD29

MD30

MD31

MD32

MD33

MD34

MD35

-

Reserved

REserved

Reserved

Hardware

Pull down

-

Note; Where the indication hardware appears, the strap options are selected directly on the board by jumpers

or resistances. Refer to the reference schematics for examples.

Issue 1.1 - October 16, 2000

23/59

STRAP OPTIONS

Memory

Data

Lines

Actual

Settings

Refer to

Designation

Location

Set to ’0’

Set to ’1’

MD36

MD37

MD38

MD39

MD40

MD41

MD42

MD43

MD44

MD45

MD46

MD47

MD48

-

Reserved

CPU Mode

Reserved

-

CPU

Hardware

User defined

Pull down

Pull up

Pull down

Pull up

Pull down

Pull up

DX1

DX2

-

Note; Where the indication hardware appears, the strap options are selected directly on the board by jumpers

or resistances. Refer to the reference schematics for examples.

3.1 Power on strap registers description

1: Internal. MCLKO pin is an output

and is connected to the internal fre-

quency synthesizer output.

3.1.1 Strap register 0 Configuration Index 4Ah

(Strap0)

Bit 2 This bit reflects the value sampled on

MD[18] pin and controls the Host/CPU clock

source as follows:

This register is Reserved.

3.1.2 Strap register 1 Configuration Index 4Bh

(Strap1)

0: External. HCLK pin is an input.

1: Internal. HCLK pin is an output and

is connected to the internal frequen-

cy synthesizer output.

This register is Reserved.

3.1.3 Strap register 2 Configuration Index 4Ch

(Strap2)

Bit 1 This bit reflects the value sampled on

MD[17] pin and controls the PCI clock output as

follows:

Reserved

Bits 7-5

.

0: PCI clock output = HCLK / 3

1: PCI clock output = HCLK / 2

Bit 4 This bit reflects the value sampled on

MD[20] pin and controls the Dot clock (DCLK)

source as follows:

Bit 0 This bit reflects the value sampled on

MD[16] pin and controls the configuration of

MASTERx and either SD[15:8] (in user mode) or

VIN[7:0] for use in test/debug modes.

0: External. DCLK pin is an input.

1: Internal. DCLK pin is an output and

is connected to the internal frequen-

cy synthesizer output.

0: Configured as test bus.

Note this bit is writeable as well as readable.

1: Configured as normal IOs.

Bit 3 This bit reflects the value sampled on

MD[19] pin and controls the Memory clock output

(MCLKO) source as follows:

This register defaults to the values sampled on

MD[23] & MD[20:16] pins after reset.

0: External. MCLKO pin is tristated.

24/59

Issue 1.1 - October 16, 2000

STRAP OPTIONS

3.1.4 HCLK Strap register Configuration Index

5Fh (HCLK_Strap)

grammed through strap values on MD[35:31] &

MD[46:45].

MD[46:45] set the source of the HCLKI and the

programming value if the PLL option is chosen.

Bits 7-6 Reserved.

Bits 5-3 These pins reflect the

value sampled on

MD[46:45] HCLKI source

respectively and control the Host

MD[26:24] pins

clock frequency synthesizer as follows:

MD[46] MD[45] HCLKI Source

HCLKI PLL enabled & HCLKI frequen-

cy between 16 & 32 MHz

Bit 5

Bit 4

Bit 3

Description

25 MHz

33 MHz

100 MHz

50 MHz

60 MHz

66 MHz

75 MHz

90 MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HCLKI PLL enabled & HCLKI frequen-

cy between 32 & 64 MHz

HCLKI PLL enabled & HCLKI frequen-

cy greater than 64 MHz

HCLKI PLL disabled; delay chains se-

lected

, MD[35:31] are used to set

CPU to HCLKI skew

the correct skew between the HCLKI and the CPU

clock. MD[35] controls whether the CPU clock

leads (strap to vss) or lags (strap to vdd) the

chipset host clock. MD[34:31] set the value of the

skew between these two clocks. Contact your ST

applications support for the correct value to strap

to these bits. These bits are only enabled when

MD[46:45] == 11.

Bit 2-0 Reserved.

This register defaults to the values sampled on

above pins after reset.

The recommended value for these three bits is

110.

3.1.7 486 Clock Programming (486_Prog)

3.1.5 Delay Programming For DLL (DLL_Prog)

The bit MD[40] is used to set the clock multiplica-

tion factor of the 486 core. With the MD[40] pin

pulled low the 486 will run in DX (x1) mode, while

with the MD[40] pin pulled high the 486 will run in

DX2 (x2) mode. The default value of the resistor

on this strap input should be a resister to gnd (DX

mode).

The bits MD[30:27] are used to set the delay of the

host clock entering the on chip DLL used to gener-

ate PCI_CLKO that is synchronous with HCLK.

Please refer to the STPC Consumer-S Reference

Design Schematics for the appropriate value or

contact your ST application engineer.

3.1.6 HCLKI Programming (HCLK_Prog)

MD[43:41] are used to set the

clock tic input value for the 486 core DLL.

CPU clock tic,

The HCLKI clock signal (the clock that is used in

the ADPC std cell logic) is selected and pro-

The recommended value for these three bits is

010.

Issue 1.1 - October 16, 2000

25/59

ELECTRICAL SPECIFICATIONS

4 ELECTRICAL SPECIFICATIONS

4.1 Introduction

20 kΩ (±10%) pull-up resistor to prevent spurious

operation.

The electrical specifications in this chapter are val-

id for the STPC Consumer-S.

4.2.3 Reserved Designated Pins

Pins designated reserved should be left discon-

nected. Connecting a reserved pin to a pull-up re-

sistor, pull-down resistor, or an active signal could

cause unexpected results and possible circuit

malfunctions.

4.2 Electrical Connections

4.2.1 Power/Ground Connections/Decoupling

Due to the high frequency of operation of the

STPC Consumer-S, it is necessary to install and

test this device using standard high frequency

techniques. The high clock frequencies used in

the STPC Consumer-S and its output buffer cir-

cuits can cause transient power surges when sev-

eral output buffers switch output levels simultane-

ously. These effects can be minimized by filtering

the DC power leads with low-inductance decou-

pling capacitors, using low impedance wiring, and

by utilizing all of the VSS and VDD pins.

4.3 Absolute Maximum Ratings

The following table lists the absolute maximum

ratings for the STPC Consumer-S device. Stress-

es beyond those listed under Table 4-1 limits may

cause permanent damage to the device. These

are stress ratings only and do not imply that oper-

ation under any conditions other than those spec-

ified in section "Operating Conditions".

Exposure to conditions beyond Table 4-1 may (1)

reduce device reliability and (2) result in prema-

ture failure even when there is no immediately ap-

parent sign of failure. Prolonged exposure to con-

ditions at or near the absolute maximum ratings

(Table 4-1) may also result in reduced useful life

and reliability.

4.2.2 Unused Input Pins

All inputs not used by the designer and not listed

in the table of pin connections in Chapter 3 should

be connected either to VDD or to VSS. Connect

active-high inputs to VDD through a 20 k (±10%)

pull-down resistor and active-low inputs to VSS

and connect active-low inputs to VCC through a

Ω

Table 4-1. Absolute Maximum Ratings

Symbol

Parameter

Value

-0.3, 4.0

Units

V

DC Supply Voltage

DDx

V , V

Digital Input and Output Voltage

-0.3, VDD + 0.3

-40, +150

V

I

O

T

Storage Temperature

°C

W

STG

1

P

Total Power Dissipation (HCLK = 90MHz, MCLK = 75MHz)

4.9

TOT

Note 1; See Table 5.2 for heat dissipation requirements

26/59

Issue 1.1 - October 16, 2000

ELECTRICAL SPECIFICATIONS

4.4 DC Characteristics

Table 4-2. DC Characteristics

±

°C unless otherwise specified

Recommended Operating conditions : VDD = 3.45V 0.15V, Tcase = 0 to 100

Symbol

Parameter

Operating Voltage

Supply Power

Test conditions

Min

Typ

3.45

4.5

Max

3.6

4.7

4.9

75

Unit

V

P

3.3

DD

V

=3.45V, H

=75Mhz, MCLK=75MHz

W

Mhz

V

DD

CLK

=3.45V, H

=90Mhz, MCLK=75MHz

4.6

CLK

H

V

Internal Clock

(Note 1)

CLK

DAC Voltage Reference

Output Low Voltage

Output High Voltage

Input Low Voltage

1.04

1.12

1.20

0.5

REF

V

I

=1.5 to 8mA depending of the pin

=-0.5 to -8mA depending of the pin

V

OL

Load

V

2.4

-0.3

2.1

V

OH

V

Except XTALI

XTALI

0.8

0.9

V

IL

V

Input High Voltage

Except XTALI

XTALI

V

+0.15

V

IH

DD

2.35

-5

+0.15

5

V

I

Input Leakage Current

Dynamic Current

Input, I/O

A

µ

LK

at RESET, H

= 66Mhz, V = 3.45V,

DD

CLK

I

1.8

A

dd

@Room Temp

C

Input Capacitance

Output Capacitance

Clock Capacitance

(Note 2)

pF

IN

C

(Note 2)

OUT

C

(Note 2)

CLK

rising clock edge reference level VREF , and other

reference levels are shown in Table 4-3 below for

the STPC Consumer-S. Input or output signals

must cross these levels during testing.

Notes:

1. MHz ratings refer to CPU clock frequency.

2. Not 100% tested.

Figure 4-1 shows output delay (A and B) and input

setup and hold times (C and D). Input setup and

hold times (C and D) are specified minimums, de-

fining the smallest acceptable sampling window a

synchronous input signal must be stable for cor-

rect operation.

4.5 AC Characteristics

Table 4-4 through Table 4-9 list the AC character-

istics including output delays, input setup require-

ments, input hold requirements and output float

delays. These measurements are based on the

measurement points identified in Figure 4-1. The

Table 4-3. Drive Level and Measurement Points for Switching Characteristics

Symbol

Value

1.5

Units

V

REF

V

3.0

IHD

V

0.0

ILD

Note: Refer to Figure 4-1.

Issue 1.1 - October 16, 2000

27/59

ELECTRICAL SPECIFICATIONS

Figure 4-1. Drive Level and Measurement Points for Switching Characteristics

Tx

V

IHD

CLK:

Ref

ILD

V

A

MAX

B

MIN

Valid

Output n

Valid

Output n+1

V

OUTPUTS:

Ref

C

D

V

IHD

Valid

Input

INPUTS:

LEGEND:

Ref

ILD

V

A - Maximum Output Delay Specification

B - Minimum Output Delay Specification

C - Minimum Input Setup Specification

D - Minimum Input Hold Specification

28/59

Issue 1.1 - October 16, 2000

ELECTRICAL SPECIFICATIONS

4.5.1 POWER ON SEQUENCE

3.45V Supply

14M H z

> 10 us

1.6V

SYSRSTI#

Strap Options

HCLK

VALID CONFIGURATION

PCI_CLK

SYSRSTO#

FRAM E#

2.3 m s

SYSRSTI# has no constraint on its rising time but

needs to be set to high at least 10µs after power

supply is stable.

Strap Options are continuously sampled during

SYSRSTI# low and should be stable. Once

SYSRSTI# is high, they MUST NOT CHANGE

until SYSRSTO# is high.

Issue 1.1 - October 16, 2000

29/59

ELECTRICAL SPECIFICATIONS

Table 4-4. PCI Bus AC Timing

Name

t1

Parameter

Min

-

Max

Unit

ns

PCI_CLKI to any output

Setup to PCICKLI

12.8

t2

7.0

1.0

-

ns

t3

Hold from PCICLKI

-

ns

t4

PCICLKI to PCI_GNT# output valid

PCI_REQ# setup to PCI_CLKI

PCI_REQ# hold to PCI_CLKI

12.0

ns

t5

12.0

0.0

-

ns

T6

ns

Table 4-5. IDE Bus AC Timing

Name

t20

t21

t22

t23

t24

t25

t26

t27

t28

t29

t30

t31

t32

t33

t34

t35

t36

t37

t38

t39

t40

t41

Parameter

Min

Max

42

10

28

32

28

Unit

ns

PCI_CLKI to SA[19:8] Active

-

PCI_CLKI to RMRTCCS# Active

PCI_CLKI to KBCS# Active

-

PCI_CLKI to RTCRW# Active

PCI_CLKI to RTCDS Active

-

SA[19:8] Input Setup to SIOR# Rising

SA[19:8] Input Hold to SIOR# Rising

RMRTCCS# Input Setup to SIOR# Rising

RMRTCCS# Input Hold to SIOR# Rising

KBCS# Input Setup to SIOR# Rising

KBCS# Input Hold to SIOR# Rising

RTCRW# Input Setup to SIOR# Rising

RTCRW# Input Hold to SIOR# Rising

RTCDS Input Setup to SIOR# Rising

RTCDS Input Hold to SIOR# Rising

PCI_CLKI to LA[23:17] Active

PCI_CLKI to PDACK# Active

PCI_CLKI to SDACK Active

-10

-

PCI_CLKI to PIOR# Active

-

PCI_CLKI to PIOW# Active

-

PCI_CLKI to SIOR# Active

-

PCI_CLKI to SIOW# Active

-

Table 4-6. SDRAM Bus AC Timing

Name

t42

Parameter

Min

Max

6.2

7.6

8.1

Unit

ns

MCLKI to RAS#[1:0] Output Valid

MCLKI to CAS#[1:0] Output Valid

MCLKI to CS#[3:0] Output Valid

MCLKI to DQM#[7:0] Output Valid

-

t43

ns

t44

ns

t45

ns

Note; The figures are extrapolated from silicon characterisation results and design timing analysis

Please refer to STPC Consumer-S Programming Manual for RDCLK settings

30/59

Issue 1.1 - October 16, 2000

ELECTRICAL SPECIFICATIONS

Table 4-6. SDRAM Bus AC Timing

Name

t46

t47

t48

t49

t50

t51

t52

t53

t54

t55

Parameter

Min

-

Max

Unit

ns

MCLKI to MA[11:0] Output Valid

6.2

MCLKI to MWE# Output Valid

-

6.2

MCLKI to MD[63:0] Output Valid

-

8.2

MD[63:0] setup to MCKLI (no RDCLK)

MD[63:0] setup to MCKLI (RDCLK at min delay)

MD[63:0] setup to MCKLI (RDCLK at mid delay)

MD[63:0] setup to MCKLI (RDCLK at max delay)

MD[63:0] hold from MCKLI (no RDCLK)

MD[63:0] hold from MCKLI (RDCLK at min delay)

MD[63:0] hold from MCKLI (RDCLK at mid delay)

MD[63:0] hold from MCKLI (RDCLK at max delay)

8.2

4.9

4.0

3.0

3.1

6.5

7.1

8.5

-

Note; The figures are extrapolated from silicon characterisation results and design timing analysis

Please refer to STPC Consumer-S Programming Manual for RDCLK settings

Table 4-7. Video Input/TV Output AC Timing

Name

t56

Parameter

Min

5

Max

Unit

ns

VIN[7:0] setup to VCLK

VIN[7:0] hold from VCLK

VCLK to ODD_EVEN valid

VCLK to VCS valid

t57

4

t58

15

t59

t60

ODD_EVEN setup to VCLK

ODD_EVEN hold from VCLK

VCS setup to VCLK

10

5

t61

t62

10

5

t63

VCS hold from VCLK

Table 4-8. Graphics Adapter (VGA) AC Timing

Name

t64

Parameter

Min

Max

30

Unit

ns

DCLK to VSYNC valid

DCLK to HSYNC valid

t65

30

ns

Issue 1.1 - October 16, 2000

31/59

ELECTRICAL SPECIFICATIONS

Figure 4-2 ISA Cycle (ref table Table 4-9)

2

15

38

37

14

13

12

25

9

56

18

29

ALE

22

AEN

Valid AENx

34

33

3

Valid Address

LA [23:17]

42

11

24

41

57

10

27

SA [19:0]

Valid Address, SBHE*

26

23

55

58

59

48

47

28

61

64

CONTROL (Note 1)

IOCS16#

MCS16#

54

IOCHRDY

READ DATA

WRITE DATA

V.Data

VALID DATA

Note 1; Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.

Note; The clock has not been represented as it cannot be accuratly represented depending on the ISA Slave mode.

Table 4-9. ISA Bus AC Timing

Name

Parameter

Min

Max

Units

4

2

LA[23:17] valid before ALE# negated

LA[23:17] valid before MEMR#, MEMW# asserted

5T

Cycles

4

3

4

3a Memory access to 16 bit ISA Slave

5T

1T

Cycles

4

3b Memory access to 8 bit ISA Slave

4

9

SA[19:0] & SBHE valid before ALE# negated

4

10

SA[19:0] & SBHE valid before MEMR#, MEMW# asserted

4

10a Memory access to 16 bit ISA Slave

2T

Cycles

4

10b Memory access to 8 bit ISA Slave

4

10

SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted

4

10c Memory access to 16 bit ISA Slave

2T

Cycle

Cycles

4

10d Memory access to 8 bit ISA Slave

4

10e

SA[19:0] & SBHE valid before IOR#, IOW# asserted

4

11

XTALO to IOW# valid

4

11a Memory access to 16 bit ISA Slave - 2BCLK

2T

Cycles

4

11b Memory access to 16 bit ISA Slave - Standard 3BCLK

Note; The signal numbering refers to Table 4-2

Note 4; These timings are extracted from simulations and are not garanteed by testing

32/59

Issue 1.1 - October 16, 2000

ELECTRICAL SPECIFICATIONS

Table 4-9. ISA Bus AC Timing

Name

Parameter

Min

2T

1T

Max

Units

Cycles

4

11c Memory access to 16 bit ISA Slave - 4BCLK

4

11d Memory access to 8 bit ISA Slave - 2BCLK

4

11e

Memory access to 8 bit ISA Slave - Standard 3BCLK

ALE# asserted before ALE# negated

4

12

4

13

ALE# asserted before MEMR#, MEMW# asserted

4

13a Memory Access to 16 bit ISA Slave

2T

Cycles

4

13b Memory Access to 8 bit ISA Slave

4

13

ALE# asserted before SMEMR#, SMEMW# asserted

4

13c Memory Access to 16 bit ISA Slave

2T

Cycles

4

13d Memory Access to 8 bit ISA Slave

4

13e

ALE# asserted before IOR#, IOW# asserted

4

14

ALE# asserted before AL[23:17]

4

14a Non compressed

15T

Cycles

4

14b Compressed

4

15

ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated

4

15a Memory Access to 16 bit ISA Slave- 4 BCLK

11T

14T

Cycles

4

15e Memory Access to 8 bit ISA Slave- Standard Cycle

4

18a

ALE# negated before LA[23:17] invalid (non compressed)

ALE# negated before LA[23:17] invalid (compressed)

MEMR#, MEMW# asserted before LA[23:17]

4

22

23

24

4

22a Memory access to 16 bit ISA Slave.

13T

Cycles

4

22b Memory access to 8 bit ISA Slave.

4

MEMR#, MEMW# asserted before MEMR#, MEMW# negated

4

23b Memory access to 16 bit ISA Slave Standard cycle

9T

Cycles

4

23e Memory access to 8 bit ISA Slave Standard cycle

4

SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated

4

23h Memory access to 16 bit ISA Slave Standard cycle

9T

Cycles

4

23l Memory access to 16 bit ISA Slave Standard cycle

9T

IOR#, IOW# asserted before IOR#, IOW# negated

4

23o Memory access to 16 bit ISA Slave Standard cycle

9T

Cycles

4

23r Memory access to 8 bit ISA Slave Standard cycle

MEMR#, MEMW# asserted before SA[19:0]

4

24b Memory access to 16 bit ISA Slave Standard cycle

10T

Cycles

4

24d Memory access to 8 bit ISA Slave - 3BLCK

4

24e Memory access to 8 bit ISA Slave Standard cycle

4

24f Memory access to 8 bit ISA Slave - 7BCLK

4

24

SMEMR#, SMEMW# asserted before SA[19:0]

24h Memory access to 16 bit ISA Slave Standard cycle

10T

Cycles

4

24i Memory access to 16 bit ISA Slave - 4BCLK

4

24k Memory access to 8 bit ISA Slave - 3BCLK

4

24l Memory access to 8 bit ISA Slave Standard cycle

4

24

25

IOR#, IOW# asserted before SA[19:0]

4

24o I/O access to 16 bit ISA Slave Standard cycle

19T

Cycles

4

24r I/O access to 16 bit ISA Slave Standard cycle

MEMR#, MEMW# asserted before next ALE# asserted

Note; The signal numbering refers to Table 4-2

Note 4; These timings are extracted from simulations and are not garanteed by testing

Issue 1.1 - October 16, 2000

33/59

ELECTRICAL SPECIFICATIONS

Table 4-9. ISA Bus AC Timing

Name

Parameter

Min

10T

Max

Units

Cycles

4

25b

25d

Memory access to 16 bit ISA Slave Standard cycle

Memory access to 8 bit ISA Slave Standard cycle

4

25

SMEMR#, SMEMW# asserted before next ALE# aserted

4

25e

Memory access to 16 bit ISA Slave - 2BCLK

Memory access to 16 bit ISA Slave Standard cycle

Memory access to 8 bit ISA Slave Standard cycle

10T

Cycles

4

25f

4

25h

4

25

IOR#, IOW# asserted before next ALE# asserted

4

25i

I/O access to 16 bit ISA Slave Standard cycle

10T

Cycles

4

25k

4

26

MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted

4

26b

26d

Memory access to 16 bit ISA Slave Standard cycle

Memory access to 8 bit ISA Slave Standard cycle

12T

Cycles

4

26

SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted

4

26f

Memory access to 16 bit ISA Slave Standard cycle

Memory access to 8 bit ISA Slave Standard cycle

12T

Cycles

4

26h

4

26

IOR#, IOW# asserted before next IOR#, IOW# asserted

4

26i

I/O access to 16 bit ISA Slave Standard cycle

I/O access to 8 bit ISA Slave Standard cycle

12T

Cycles

4

26k

4

28

Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted

4

28a

28b

Memory access to 16 bit ISA Slave

Memory access to 8 bit ISA Slave

3T

Cycles

4

28

Any command negated to IOR#, IOW# asserted

4

28c

I/O access to ISA Slave

3T

1T

Cycles

4

29a

MEMR#, MEMW# negated before next ALE# asserted

SMEMR#, SMEMW# negated before next ALE# asserted

IOR#, IOW# negated before next ALE# asserted

4

29b

4

29c

4

33

LA[23:17] valid to IOCHRDY negated

4

33a

33b

Memory access to 16 bit ISA Slave - 4 BCLK

Memory access to 8 bit ISA Slave - 7 BCLK

8T

Cycles

4

14T

4

34

LA[23:17] valid to read data valid

4

34b

34e

Memory access to 16 bit ISA Slave Standard cycle

Memory access to 8 bit ISA Slave Standard cycle

8T

Cycles

4

14T

4

37

ALE# asserted to IOCHRDY# negated

4

37a

37b

Memory access to 16 bit ISA Slave - 4 BCLK

Memory access to 8 bit ISA Slave - 7 BCLK

I/O access to 16 bit ISA Slave - 4 BCLK

I/O access to 8 bit ISA Slave - 7 BCLK

6T

12T

6T

Cycles

4

37c

4

37d

12T

4

38

ALE# asserted to read data valid

4

38b

38e

38h

Memory access to 16 bit ISA Slave Standard Cycle

Memory access to 8 bit ISA Slave Standard Cycle

I/O access to 16 bit ISA Slave Standard Cycle

I/O access to 8 bit ISA Slave Standard Cycle

4T

10T

4T

Cycles

4

38l

10T

4

41

SA[19:0] SBHE valid to IOCHRDY negated

4

41a

41b

Memory access to 16 bit ISA Slave

Memory access to 8 bit ISA Slave

6T

Cycles

4

12T

Note; The signal numbering refers to Table 4-2

Note 4; These timings are extracted from simulations and are not garanteed by testing

34/59

Issue 1.1 - October 16, 2000

ELECTRICAL SPECIFICATIONS

Table 4-9. ISA Bus AC Timing

Name

Parameter

Min

6T

Max

Units

Cycles

4

41c

41d

I/O access to 16 bit ISA Slave

I/O access to 8 bit ISA Slave

4

12T

4

42

SA[19:0] SBHE valid to read data valid

4

42b

42e

42h

Memory access to 16 bit ISA Slave Standard cycle

Memory access to 8 bit ISA Slave Standard cycle

I/O access to 16 bit ISA Slave Standard cycle

I/O access to 8 bit ISA Slave Standard cycle

4T

10T

4T

Cycles

4

42l

10T

4

47

MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated

4

47a

Memory access to 16 bit ISA Slave

Memory access to 8 bit ISA Slave

I/O access to 16 bit ISA Slave

I/O access to 8 bit ISA Slave

2T

5T

2T

5T

Cycles

4

47b

4

47c

47d

4

48

MEMR#, SMEMR#, IOR# asserted to read data valid

4

48b

48e

48h

Memory access to 16 bit ISA Slave Standard Cycle

Memory access to 8 bit ISA Slave Standard Cycle

I/O access to 16 bit ISA Slave Standard Cycle

I/O access to 8 bit ISA Slave Standard Cycle

2T

5T

2T

5T

Cycles

4

48l

4

54

IOCHRDY asserted to read data valid

4

54a

Memory access to 16 bit ISA Slave

Memory access to 8 bit ISA Slave

I/O access to 16 bit ISA Slave

I/O access to 8 bit ISA Slave

1T(R)/2T(W)

Cycles

4

54b

4

54c

54d

IOCHRDY asserted to MEMR#, MEMW#, SMEMR#,

SMEMW#, IOR#, IOW# negated

4

55a

1T

Cycles

4

55b

IOCHRY asserted to MEMR#, SMEMR# negated (refresh)

IOCHRDY asserted to next ALE# asserted

1T

2T

0T

Cycles

4

56

4

57

IOCHRDY asserted to SA[19:0], SBHE invalid

MEMR#, IOR#, SMEMR# negated to read data invalid

MEMR#, IOR#, SMEMR# negated to daabus float

4

58

4

59

4

61

Write data before MEMW# asserted

4

61a

Memory access to 16 bit ISA Slave

2T

Cycles

Memory access to 8 bit ISA Slave (Byte copy at end of

start)

4

61b

4

61

Write data before SMEMW# asserted

4

61c

61d

Memory access to 16 bit ISA Slave

Memory access to 8 bit ISA Slave

2T

Cycles

4

61

Write Data valid before IOW# asserted

4

61e

I/O access to 16 bit ISA Slave

I/O access to 8 bit ISA Slave

2T

1T

Cycles

4

61f

4

64a

MEMW# negated to write data invalid - 16 bit

MEMW# negated to write data invalid - 8 bit

SMEMW# negated to write data invalid - 16 bit

SMEMW# negated to write data invalid - 8 bit

IOW# negated to write data invalid

4

64b

4

64c

4

64d

4

64e

Note; The signal numbering refers to Table 4-2

Note 4; These timings are extracted from simulations and are not garanteed by testing

Issue 1.1 - October 16, 2000

35/59

ELECTRICAL SPECIFICATIONS

Table 4-9. ISA Bus AC Timing

Name

Parameter

Min

Max

Units

MEMW# negated to copy data float, 8 bit ISA Slave, odd Byte

by ISA Master

4

64f

1T

Cycles

IOW# negated to copy data float, 8 bit ISA Slave, odd Byte by

ISA Master

4

64g

1T

Cycles

Note; The signal numbering refers to Table 4-2

Note 4; These timings are extracted from simulations and are not garanteed by testing

36/59

Issue 1.1 - October 16, 2000

MECHANICAL DATA

5. MECHANICAL DATA

5.1 388-Pin Package Dimension

Dimensions are shown in Figure 5-2, Table 5-1

and Figure 5-3, Table 5-2.

The pin numbering for the STPC 388-pin Plastic

BGA package is shown in Figure 5-1.

Figure 5-1. 388-Pin PBGA Package - Top View

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

A

B

C

D

E

F

G

H

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

Issue 1.1 - October 16, 2000

37/59

MECHANICAL DATA

Figure 5-2. 388-pin PBGA Package - PCB Dimensions

A1 Ball Pad Corner

A

B

A

D

E

F

Detail

G

C

388-pin PBGA Package - PCB Dimensions

Table 5-1.

mm

inches

Typ

Symbols

Min

34.95

1.22

0.58

1.57

0.15

0.05

0.75

Typ

35.00

1.27

0.63

1.62

0.20

0.10

0.80

Max

35.05

1.32

0.68

1.67

0.25

0.15

0.85

Min

Max

A

B

C

D

E

F

1.375

0.048

0.023

0.062

0.006

0.002

0.030

1.378

0.050

0.025

0.064

0.008

0.004

0.032

1.380

0.052

0.027

0.066

0.001

0.006

0.034

G

38/59

Issue 1.1 - October 16, 2000

MECHANICAL DATA

Figure 5-3. 388-pin PBGA Package - Dimensions

C

F

D

E

Solderball

Solderball after collapse

B

G

A

388-pin PBGA Package - Dimensions

Table 5-2.

mm

inches

Symbols

Min

0.50

1.12

0.60

0.52

0.63

0.60

Typ

0.56

1.17

0.76

0.53

0.78

0.63

30.0

Max

0.62

1.22

0.92

0.54

0.93

0.66

Min

Typ

Max

A

B

C

D

E

F

0.020

0.044

0.024

0.020

0.025

0.024

0.022

0.046

0.030

0.021

0.031

0.025

11.8

0.024

0.048

0.036

0.022

0.037

0.026

G

Issue 1.1 - October 16, 2000

39/59

MECHANICAL DATA

5.2 388-Pin Package thermal data

Structure in shown in Figure 5-4.

Thermal dissipation options are illustrated in Fig-

ure 5-5 and Figure 5-6.

388-pin PBGA package has a Power Dissipation

Capability of 4.5W which increases to 6W when

used with a Heatsink.

Figure 5-4. 388-Pin PBGA structure

Signal layers

Power & Ground layers

Thermal balls

Figure 5-5. Thermal dissipation without heatsink

Board

Board dimensions:

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

Ambient

Case

Junction

Rca

Rjc

6

The PBGA is centered on board

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

Board

8.5

Case

125

Junction

Board

Rjb

Rba

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

Ambient

Airflow = 0

Rja = 13 °C/W

Board temperature taken at the center balls

40/59

Issue 1.1 - October 16, 2000

MECHANICAL DATA

Figure 5-6. Thermal dissipation with heatsink

Board

Board dimensions:

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

Ambient

Case

Junction

Rca

Rjc

The PBGA is centered on board

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

3

6

Board

8.5

Case

50

Junction

Board

Rjb

Rba

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

Ambient

Airflow = 0

Ambient

Board temperature taken at the center balls

Heat sink is 11.1°C/W

Rja = 9.5 °C/W

Issue 1.1 - October 16, 2000

41/59

BOARD LAYOUT

6. BOARD LAYOUT

6.1 Thermal dissipation

With such configuration the Plastic BGA 388 pack-

age does 90% of the thermal dissipation through

the ground balls, and especially the central ther-

mal balls which are directly connected to the die,

the remaining 10% is dissipated through the case.

Adding a heat sink reduces this value to 85%.

Thermal dissipation of the STPC depends mainly

on supply voltage. As a result, when the system

does not need to work at 3.45V, it is interesting to

reduce the voltage to 3.15V, for example, if it is

possible. This may save few 100’s of mW.

As a result, some basic rules has to be applied

when routing the STPC in order to avoid thermal

problems.

The second area to look at is unused interfaces

and functions. Depending on the application,

some input signals can be grounded, and some

blocks not powered or shutdown. Clock speed dy-

namic adjustment is also a solution that can be

used along with the integrated power manage-

ment unit.

First of all, the whole ground layer acts as a heat

sink and ground balls must be directly connected

to it as illustrated in Figure 6-1.

If one ground layer is not enough, a second

ground plane may be added on solder side.

The standard way to route thermal balls to internal

ground layer implements only one via pad for each

ball pad, connected using a 8-mil wire.

Figure 6-1. Ground routing

Pad for ground ball

Thru hole to ground layer

Note: For better visibility, ground balls are not all routed.

42/59

Issue 1.1 - October 16, 2000

BOARD LAYOUT

When considering thermal dissipation, the most

important - and not the more obvious - part of the

layout is the connection between the ground balls

and the ground layer.

To avoid solder wicking over to the via pads during

soldering, it is important to have a solder mask of

4 mil around the pad (NSMD pad), this gives a di-

ameter of 33 mil for a 25 mil ground pad.

A 1-wire connection is shown in Figure 6-2. The

use of a 8-mil wire results in a thermal resistance

of 105°C/W assuming copper is used (418 W/

m.°K). This high value is due to the thickness (34

µm) of the copper on the external side of the PCB.

To obtain the optimum ground layout, place the

vias directly under the ball pads. In this case no lo-

cal boar d distortion is tolerated.

The thickness of the copper on PCB layers is typ-

ically 34 µm for external layers and 17 µm for inter-

nal layers. That means thermal dissipation is not

good and temperature of the board is concentrat-

ed around the devices and falls quickly with in-

creased distance.

Considering only the central matrix of 36 thermal

balls and one via for each ball, the global thermal

resistance is 2.9°C/W. This can be easily im-

proved using four 10 mil wires to connect to the

four vias around the ground pad link as in Figure

6-3. This gives a total of 49 vias and a global re-

sistance for the 36 thermal balls of 0.6°C/W.

When it is possible to place a metal layer inside

the PCB, this improves dramatically the heat

spreading and hence thermal dissipation of the

board.

The use of a ground plane like in Figure 6-4 is

even better.

Figure 6-2. Recommended 1-wire ground pad layout

Pad for ground ball (diameter = 25 mil)

Solder Mask (4 mil)

Connection Wire (width = 10 mil)

Via (diameter = 24 mil)

Hole to ground layer (diameter = 12 mil)

1 mil = 0.0254 mm

Figure 6-3. Recommended 4-wire ground pad layout

4 via pads for each ground ball

Issue 1.1 - October 16, 2000

43/59

BOARD LAYOUT

Figure 6-4. Optimum layout for central ground ball

Clearance = 6mil

External diameter = 37 mil

Via to Ground layer

hole diameter = 14 mil

Solder mask

diameter = 33 mil

Pad for ground ball

diameter = 25 mil

connections = 10 mil

The PBGA Package dissipates also through pe-

ripheral ground balls. When a heat sink is placed

on the device, heat is more uniformely spread

throughout the moulding increasing heat dissipa-

tion through the peripheral ground balls.

6.2 High speed signals

Some Interfaces of the STPC run at high speed

and have to be carefully routed or even shielded.

Here is the list of these interfaces, in decreasing

speed order:

The more via pads are connected to each ground

ball, the more heat is dissipated . The only limita-

tion is the risk of lossing routing channels.

1) Memory Interface.

2) Graphics and video interfaces

3) PCI bus

Figure 6-5 shows a routing with a good trade off

between thermal dissipation and number of rout-

ing channels.

A local ground plane on opposite side of the board

as shown in Figure 6-6 improves thermal dissipa-

tion. It is used to connect decoupling capacitances

but can also be used for connection to a heat sink

or to the system’s metal box for better dissipation.

4) 14MHz oscillator stage

All the clocks haves to be routed first and shielded

for speeds of 27MHz or more. The high speed sig-

nals follow the same contrainsts, like the memory

control signals and the PCI control signals.

This possibility of using the whole system’s box for

thermal dissipation is very usefull in case of high

temperature inside the system and low tempera-

ture outside. In that case, both sides of the PBGA

should be thermally connected to the metal chas-

sis in order to propagate the heat flow through the

metal. Figure 6-7 illustrates such implementation.

The next interfaces to be routed are Memory, Vid-

eo/graphics, and PCI.

All the analog noise sensitive signals have to be

routed in a separate area and hence can be rout-

ed indepedently.

44/59

Issue 1.1 - October 16, 2000

BOARD LAYOUT

Figure 6-5. Global ground layout for good thermal dissipation

Via to ground layer

Ground pad

Figure 6-6. Bottom side layout and decoupling

Ground plane for thermal dissipation

Via to ground layer

Issue 1.1 - October 16, 2000

45/59

BOARD LAYOUT

Figure 6-7. Use of metal plate for thermal dissipation

Die

Board

Metal planes

Thermal conductor

Figure 6-8. Shielding signals

ground ring

shielded signal line

ground pad

shielded signal lines

46/59

Issue 1.1 - October 16, 2000

BOARD LAYOUT

no longer present but it is then up to the user to

verify the timings.

6.3 Memory interface

6.3.1 Introduction

6.3.2 SDRAM Clocking Scheme

In order to achieve SDRAM memory interfaces

which work at clock frequencies of 100MHz and

above, careful consideration has to be given to the

timing of the interface with all the various electrical

and physical constraints taken into consideration.

The guidelines described below are related to

SDRAM components on DIMM modules. For ap-

plications where the memories are directly sol-

dered to the motherboard, the PCB should be laid

out such that the trace lengths fit within the con-

straints shown here. The traces could be slightly

longer since the extra routing on the DIMM PCB is

The SDRAM Clocking Scheme deserves a special

mention here. Basically the memory clock is gen-

erated on-chip through a PLL and goes directly to

the MCLKO output pin of the STPC. The nominal

frequency is 100MHz. Because of the high load

presented to the MCLK on the board by the

DIMMs it is recommeded to rebuffer the MCLKO

signal on the board and balance the skew to the

clock ports of the different DIMMs and the MCLKI

input pin of STPC.

Figure 6-9. Clock scheme

MCLKO

PLL

MCLKI

PLL

MA[] + Control

SDRAM

MD[]

CONTROLLER

and ground planes to provide a low impedance

path between the planes for the return paths for

signal routings which change layers. If possible

the traces should be routed adjacent to the same

power or ground plane for the length of the trace.

6.3.3 Board Layout Issues

The physical layout of the motherboard PCB as-

sumed in this presentation is as shown in Figure

6-10. Because all the memory interface signal

balls are located in the same region of the STPC

device it is possible to orientate the device to re-

duce the trace lengths. The worst case routing

length to the DIMM1 is estimated to be 100mm.

For the SDRAM interface the most critical signal is

the clock. Any skew between the clocks at the

SDRAM components and the memory controller

will impact the timing budget. In order to get well

matched clocks at all the components it is recom-

mended that all the DIMM clock pins, STPC mem-

ory clock input (MCLKI) and any other component

using the memory clock are individually driven

Solid power and ground planes are a must in order

to provide good return paths for the signals and to

reduce EMI and noise. Also there should be ample

high frequency decoupling between the power

Issue 1.1 - October 16, 2000

47/59

BOARD LAYOUT

Figure 6-10. DIMM placement

35mm

STPC

35mm

15mm

SDRAM I/F

DIMM4

DIMM3

DIMM2

DIMM1

116mm

10mm

from a low skew clock driver with matched routing

lengths. This is shown in Figure 6-11.

Figure 6-11. Clock routing

L

Low skew clock driver:

DIMM CKn input

STPC MCLKI

MCLKO

L+75mm*

20pF

* No additionnal 75mm when SDRAM directly soldered on board

The maximum skew between pins for this part is

250ps. The important factors for the clock buffer

are a consistent drive strength and low skew be-

tween the outputs. The delay through the buffer is

not important so it does not have to be a zero de-

lay PLL type buffer. The trace lengths from the

clock driver to the DIMM CKn pins should be

matched exactly. Since the propagation speed

can vary between PCB layers the clocks should

be routed in a consistent way. The routing to the

STPC memory input should be longer by 75mm to

compensate for the extra clock routing on the

DIMM. Also a 20pF capacitor should be placed as

near as possible to the clock input of the STPC to

compensate for the DIMM’s higher clock load. The

impedance of the trace used for the clock routing

^p^sh^e^o^d^u^a^lⁿ^d^ce^be⁽⁶^m⁰^a^-7^tc⁵^he^o^d^hm^to^s)^th.^e^T^D^o^IMmMⁱⁿⁱ^c^m^lo^is^c^e^k t^c^r^r^a^o^c^s^e^stⁱ^a^m^lk^-

the clocks should be routed with spacing to adja-

cent tracks of at least twice the clock trace width.

48/59

Issue 1.1 - October 16, 2000

BOARD LAYOUT

For designs which use SDRAMs directly mounted

on the motherboard PCB all the clock trace

lengths should be matched exactly.

lines could control either 4 single row DIMMs or 2

dual row DIMMs.

When using DIMM modules, schematics have to

be done carefully in order to avoid data busses

completely crossed on the board. This has to be

checked at the library level. In order to achive lay-

out shown in Figure 6-12, schematics have to im-

plement the crossing described on Figure 6-13.

The DQM signals must be exchanged using the

same order.

The DIMM sockets should be populated starting

with the furthest DIMM from the STPC device first

(DIMM1). There are 2 types of DIMM devices; sin-

gle row and dual row. The dual row devices re-

quire 2 chip select signals to select between the

two rows. A STPC device with 4 chip select control

Figure 6-12. Optimum data bus layout for DIMM

STPC

MD[31:00]

MD[63:32]

SDRAM I/F

D[15:00]

D[47:32]

D[31:16]

D[63:48]

DIMM

Figure 6-13. Schematics for optimum data bus layout for DIMM

STPC

MD[15:00],DQM[1:0]

DIMM

D[15:00],DQM[1:0]

D[31:16],DQM[3:2]

D[47:32],DQM[5:4]

D[63:48],DQM[7:6]

MD[31:16],DQM[3:2]

MD[47:32],DQM[5:4]

MD[63:48],DQM[7:6]

Issue 1.1 - October 16, 2000

49/59

BOARD LAYOUT

6.3.4 Address & Control Signals

nents used (x4, x8 or x16) and whether the DIMM

module is single or dual row. The capacitive load-

ing of the SDRAM inputs alone for an x8 single

row DIMM will be about 30-40pF. An equivalent

circuit for the timing simulation is shown in Figure

6-14 Most of the delays are due to the PCB traces

and loading rather than the pad itself.

This group encompasses the memory address

MA[10:0], bank address BA[0], RAS, CAS and

write enable WE signals. The load of the DIMM

module on these signals is the most important one

and depends upon the type of SDRAM compo-

Figure 6-14. Address/control equivalent circuit

100mm

(0.7ns)

Rterm

10mm

ZØ

pcb

50/59

Issue 1.1 - October 16, 2000

BOARD LAYOUT

row of SDRAMs and chip selects 1 and 3 select

the second row on dual bank SDRAMs. The chip

select outputs only have to drive one DIMM each

6.3.5 Chip Select Signals (CS#[3:0])

There are 4 chip select pins per DIMM. Chip se-

lects 0 and 2 are always used to select the first

Figure 6-15. CS# equivalent circuit

130mm

(0.9ns)

CS[0]

CS[2]

Issue 1.1 - October 16, 2000

51/59

BOARD LAYOUT

6.3.6 Data Write (MD[63:0])

be compared to the timings for registered DIMMs

for the other pins.

The load on the data signals is much lower than

the address/control signals for an unbuffered

DIMM. For a registered DIMM the data signals are

the only memory pins of the DIMM which are not

registered. For the design to get maximum benefit

from using registered DIMMs the timings should

6.3.7 Data Read (MD[63:0])

The data read simulation circuit is shown below..

Figure 6-16. Data read equivalent circuit

DIMM1

125mm

(0.9ns)

10 ohms

SDRAM

DQ

10mm

52/59

Issue 1.1 - October 16, 2000

BOARD LAYOUT

The following Figure 6-17 and Figure 6-18, shows

two possible SDRAM organizations based on one

or two bank configurations.

6.3.8 Data Mask (DQM[7:0])

The data mask load is quite similar to that of the

data signals.

Notes for Figure 6-17 and Figure 6-18;

All buffers must be low skew clock buffers

6.3.9 Summary

For unbuffered DIMMs the address/control signals

will be the most critical for timing. The simulations

show that for these signals the best way to drive

them is to use a parallel termination. For applica-

tions where speed is not so critical series termina-

tion can be used as this will save power. Using a

low impedance such as 50Ω for these critical trac-

es is recommended as it both reduces the delay

and the overshoot.

One clock driver can operate upto four memory

chips.

All the clock lines must follow the rules below;

MCLKI = MCLK0 + MCLK0A

= ......

= MCLK0 + MCLK0D

= MCLK1 + MCLK1A

= ......

The other memory interface signals will typically

be not as critical as the address/control signals for

unbuffered DIMMs. When using registered DIMMs

the other signals will probably be just as critical as

the address/control signals so to gain maximum

benefit from using registered DIMMs the timings

should also be considered in that situation. Using

lower impedance traces is also beneficial for the

other signals but if their timing is not as critical as

the address/control signals they could use the de-

fault value. Using a lower impedance implies us-

ing wider traces which may have an impact on the

routing of the board.

= MCLK1 + MCLK1D

This means that all line lengths must go from the

buffer to the memory chips (MCLK1 or MCLK0 or

...) and from the buffer to the STPC (MCLKI) must

be identical.

6.4.1 Host Address to MA bus Mapping

6.4 SDRAM LAYOUT EXAMPLES

Graphics memory resides at the beginning of

Bank 0. Host memory begins at the top of graphics

memory and extends to the top of populated

SDRAM.

The STPC provides MA, RAS#, CAS#, WE#, CS#,

DQM#, BA0 (MA[11])and MD for SDRAM control.

From 2 to 128 MBytes of main memory are sup-

ported in 1 to 4 banks. All Banks must be 64 bits

wide.

The bank attributes can be retrieved from a lookup

table to select the final SDRAM row and column

address mappings. (Table 6-2). Also Table 6-1

shows the Standard DIMM Pinout for the users

that wish to design with DIMMs.

The following memory devices are supported:

4Mbit x 4, 8Mbit x 2 & 16Mbit x 1 or if in the case of

two internal bank chips, 2Mbit x 4 x 2, 4Mbit x 2 x

2 & 8Mbit x 1 x 2 .

.

Issue 1.1 - October 16, 2000

53/59

BOARD LAYOUT

Standard Memory DIMM Pinout

Table 6-1.

Memory Banks pin

16Mbit(2 banks)

number

...

MA[10:0]

123

126

39

-

122

BA0(MA11)

Address Mapping

Table 6-2.

Address Mapping: 16 Mbit - 2 banks

STPC I/F

BA0(MA11) MA10 MA9 MA8 MA7

MA6 MA5 MA4 MA3

MA2

A14

A5

MA1

A13

A4

MA0

A12

A3

RAS ADDRESS A11

CAS ADDRESS A11

A22

0

A21

A24

A2

A19

A10

A18

A9

A17

A8

A16

A7

A15

A6

A23

56/59

Issue 1.1 - October 16, 2000

ORDERING DATA

7 ORDERING DATA

7.1 Ordering Codes

ST

PC

C03

66

BT

C

3

STMicroelectronics

Prefix

Product Family

PC: PC Compatible

Product ID

C03: Consumer-S

Core Speed

66: 66MHz

75: 75MHz

90: 90MHz

Package

BT: 388 Overmoulded BGA

Temperature Range

C: Commercial

Case Temperature (Tcase) = 0°C to +100°C

I: Industrial

Case Temperature (Tcase) = -40°C to +100°C

Operating Voltage

3 : 3.45V ± 0.3V

Issue 1.1 - October 16, 2000

57/59

ORDERING DATA

7.2 Available Part Numbers

Core Frequency

CPU Mode

( X1 / X2 )

Tcase Range

( °C )

Operating Voltage

( V )

Part Number

( MHz )

STPCC0375BTC3

STPCC0390BTC3

75

X1

0°C to +100°

3.45V ± 0.3V

90

58/59

Issue 1.1 - October 16, 2000

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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59

Issue 1.1


型号：	STPCC03
厂家：	ETC
描述：	STPC CONSUMER-S DATASHEET/ PC COMPATIBLE EMBEDDED MICROPROCESSOR STPC消费者-S数据表/ PC兼容的嵌入式微处理器\n 微处理器 PC
文件：	总59页 (文件大小：1008K)
中文：	中文翻译
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