STPCC0366BTC3 [STMICROELECTRONICS]
PC Compatible Embeded Microprocessor; PC兼容的嵌入式微处理器型号: | STPCC0366BTC3 |
厂家: | ST |
描述: | PC Compatible Embeded Microprocessor |
文件: | 总51页 (文件大小:835K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STPC CONSUMER-S
PC Compatible Embeded Microprocessor
ADVANCED DATA
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POWERFUL x86 PROCESSOR
64-BIT 66MHz SDRAM UMA CONTROLLER
VGA & SVGA CRT CONTROLLER
2D GRAPHICS ENGINE
VIDEO INPUT PORT
VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
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TV OUTPUT
- 3-LINE FLICKER FILTER
PBGA388
- CCIR 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO
Figure 1. Logic Diagram
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PCI MASTER / SLAVE CONTROLLER
ISA MASTER / SLAVE CONTROLLER
Host
I/F
x86
Core
INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
PCI
m/s
PCI Bus
PMU
W.dog
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OPTIONAL 16-BIT LOCAL BUS INTERFACE
EIDE CONTROLLER
ISA
m/s
IDE
I/F
PCI
m/s
IPC
I C INTERFACE
ISA Bus
POWER MANAGEMENT UNIT
3.3V OPERATION
LB
CTR
Local Bus
STPC CONSUMER-S OVERVIEW
Video
C Key
K Key
LUT
Pipeline
The STPC Consumer-S integrates a standard 5th
generation x86 core, a Synchronous DRAM con-
troller, a graphics subsystem, a video input port,
video pipeline, and support logic including PCI,
ISA, and IDE controllers to provide a single con-
sumer orientated PC compatible subsystem on a
single device.
Monitor
SVGA
CRTC
TVO
Cursor
GE
TV
Encoder
VIP
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
SDRAM
CTRL
The STPC Consumer-S is packaged in a 388
Plastic Ball Grid Array (PBGA).
29/10/99
1/51
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STPC CONSUMER-S
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X86 Processor core
Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.
Can access up to 4GB of external memory.
8Kbyte unified instruction and data cache
with write back and write through capability.
Parallel processing integral floating point unit,
with automatic power down.
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CRT Controller
Integrated 135MHz triple RAMDAC allowing
for 1024 x 768 x 75Hz display.
8-, 16-, 24-bit pixels.
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Interlaced or non-interlaced output.
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Video Input port
Accepts video inputs in CCIR 601 mode.
Optional 2:1 decimator
Stores captured video in off setting area of
the onboard frame buffer.
Video pass through to the onchip PAL/NTSC
encoder for full screen video images.
HSYNC and B/T generation or lock onto
external video timing source.
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Fully static design for dynamic clock control.
Low power and system management modes.
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SDRAM Controller
64-bit data bus.
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Up to 66MHz SDRAM clock speed.
Integrated system memory, graphic frame
memory and video frame memory.
Supports 2MB up to 128 MB memory.
Supports 8MB, 16M, and 32MB DIMMs.
Supports buffered, non buffered, and
registered DIMMs
4-line write buffers for CPU to DRAM and PCI
to DRAM cycles.
4-line read prefetch buffers for PCI masters.
Programmable latency
Programmable timing for DRAM parameters.
Supports -8, -10, -12, -13, -15 memory parts
Supports 1MB up to 8MB memory hole.
32-bit accesses not supported.
Autoprecharge not supported.
Power down not supported.
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Video Pipeline
Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Color space conversion.
Programmable window size.
Chroma and color keying for integrated video
overlay.
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TV Output
Programmable two tap filter with gamma
correction or three tap flicker filter.
Progressive to interlaced scan converter.
NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy
programmable video outputs.
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CCIR601 encoding with programmable color
subcarrier frequencies.
FPM and EDO not supported.
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Graphics Controller
64-bit windows accelerator.
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Line skip/insert capability
Interlaced or non-interlaced operation mode.
625 lines/50Hz or 525 lines/60Hz 8 bit
multiplexed CB-Y-CR digital input.
CVBS and R,G,B simultaneous analog
outputs through 10-bit DACs.
Cross color reduction by specific trap filtering
on luma within CVBS flow.
Power down mode available on each DAC.
Compatibility to VGA & SVGA standards.
Hardware acceleration for text, bitblts,
transparent blts and fills.
Up to 64 x 64 bit graphics hardware cursor.
Up to 4MB long linear frame buffer.
8-, 16-, and 24-bit pixels.
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2/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STPC CONSUMER-S
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PCI Controller
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IDE Interface
Supports PIO and Bus Master IDE
Supports up to Mode 5 Timings
Transfer Rates to 22 MBytes/sec
Supports up to 4 IDE devices
Concurrent channel operation (PIO & DMA
modes) - 4 x 32-Bit Buffer FIFO per channel
Support for PIO mode 3 & 4.
Support for DMA mode 1 & 2.
Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers.
Fully compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3
masters can connect directly. External PAL
allows for greater than 3 masters.
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
PCI.
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Support forburst read/write from PCI master.
PCI clock is 1/3 or 1/2 Host clock .
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Supports 13.3/16.6 MB/s DMA data transfers
Bus Master with scatter/gather capability
Multi-word DMA support for fast IDE drives
Individual drive timing for all four IDE devices
Supports both legacy & native IDE modes
Supports hard drives larger than 528MB
Support for CD-ROM and tape peripherals
Backward compatibility with IDE (ATA-1).
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ISA master/slave controller
Generates the ISA clock from either
14.318MHz oscillator clock or PCI clock
Supports programmable extra wait state for
ISA cycles
Supports I/O recovery time for back to back I/
O cycles.
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
Supports flash ROM.
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Power Management
Four power saving modes: On, Doze,
Standby, Suspend.
Programmable system activity detector
Supports SMM.
Supports STOPCLK.
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Supports ISA hidden refresh.
Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.
NSP compliant.
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Supports IO trap & restart.
Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.
Supports RTC, interrupts and DMAs wake-up
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Integrated Peripheral Controller
2X8237/AT compatible 7-channel DMA
controller.
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2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
Three 8254 compatible Timer/Counters.
Co-processor error support logic.
Supports external RTC.
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Local Bus interface
Multiplxed with ISA interface.
Low latency bus
22-bit address bus.
16-bit data bus with word steering capability.
Programmable timing (Host clock granularity)
2 Programmable Flash Chip Select.
5 Programmable I/O Chip Select.
Supports 32-bit Flash burst.
2-level hardwarekey protection for Flash boot
block protection.
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Supports 2 banks of 8MB flash devices with
boot block shadowed to 0x000F0000.
3/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
At the heart of the STPC Consumer-S is an ad-
vanced 64-bit processor block, dubbed the
5ST86. The 5ST86 includes a 486 processor core
along with a 64-bit SDRAM controller, advanced
64-bit accelerated graphics and video controller, a
high speed PCI local-bus controller and Industry
standard PC chip set functions (Interrupt control-
ler, DMA Controller, Interval timer and ISA bus).
Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include hard-
ware acceleration of text, bitblts, transparent blts
and fills. The results of these operations change
the contents of the on-screen or off-screen frame
buffer areas of DRAM memory. The frame buffer
can occupy a space up to 4 Mbytes anywhere in
the physical main memory and always starts from
the bottom of the main physical memory.
The STPC Consumer-S makes use of a tightly
coupled Unified Memory Architecture (UMA),
where the same memory array is used for CPU
main memory and graphics frame-buffer. This
means a reduction in total system memory for sys-
tem performances that are equal to that of a com-
parable frame buffer and system memory based
system, and generally much better, due to the
higher memory bandwidth allowed by attaching
the graphics engine directly to the 64-bit proces-
sor host interface running at the speed of the proc-
essor bus rather than the traditional PCI bus.
The graphics resolution supported is a maximum
of 1280x1024 in 65536 colours and 1024x768 in
true color at 75Hz refresh rate and is VGA and
SVGA compatible. Horizontal timing fields are
VGA compatible while the vertical fields are ex-
tended by one bit to accommodate above display
resolution.
The 64-bit wide memory array provides the sys-
tem with 528MB/s peak bandwidth. This allows for
higher resolution screens and greater color depth.
VIDEO FUNCTIONS
The ‘standard’ PC chipset functions (DMA, inter-
rupt controller, timers, power management logic)
are integrated together with the x86 processor
core; additional functions such as communica-
tions ports are accessed by the STPC Consumer-
S via internal ISA bus.
The STPC Consumer-S provides several addition-
al functions to handle MPEG or similar video
streams. The Video Input Port accepts an encod-
ed digital video stream in one of a number of in-
dustry standard formats, decodes it, optionally
decimates it, and deposits it into an off screen
area of the frame buffer. An interrupt request can
be generated when an entire field or frame has
been captured. The video output pipeline incorpo-
rates a video-scaler and color space converter
function and provisions in the CRT controller to
display a video window. While repainting the
screen the CRT controller fetches both the video
as well as the normal non-video frame buffer in
two separate internal FIFOs. The video stream
can be color-space converted (optionally) and
smooth scaled. Smooth interpolative scaling in
both horizontal and vertical direction are imple-
mented. Color and Chroma key functions are also
implemented to allow mixing video stream with
non-video frame buffer.
The PCI bus is the main data communication link
to the STPC Consumer-S chip. The STPC Con-
sumer-S translates appropriate host bus I/O and
Memory cycles onto the PCI bus. It also supports
generation of Configuration cycles on the PCI bus.
The STPC Consumer-S, as a PCI bus agent (host
bridge class), fully complies with PCI specification
2.1. The chip-set also implements the PCI manda-
tory header registers in Type 0 PCI configuration
space for easy porting of PCI aware system BI-
OS. The device contains a PCI arbitration function
for three external PCI devices.
The STPC Consumer-S has two functionnal
blocks sharing the same balls : The ISA / IPC /
IDE block and the Local Bus / IDE block (see Ta-
ble 3). Any board with the STPC Consumer-S
should be built using only one of these two config-
urations.
The video output passes directly to the RAMDAC
for monitor output or through another optional
color space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
or a 3 line flicker filter (primarily designed for Win-
dows type displays). The fliker filter is optional and
can be software disabled for use with large screen
area’s of video.
At reset, the configuration is done by ‘strap op-
tions’ which initialises the STPC Consumer-S to
the right settings. It is a set of pull-up or pull-down
resistors on the memory data bus, checked on re-
set, which auto-configure the STPC Consumer-S.
GRAPHICS FUNCTIONS
4/51
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GENERAL DESCRIPTION
The Video output pipeline of the STPC Consumer-
S interfaces directly to the internal digital TV en-
coder. It takes a 24 bit RGB non-interlaced pixel
stream and converts to a multiplexed 4:2:2 YCrCb
8 bit output stream, the logic includes a progres-
sive to interlaced scan converter and logic to in-
sert appropriate CCIR656 timing reference codes
into the output stream. It facilitates the high quality
display of VGA or full screen video streams re-
ceived via the Video input port to standard NTSC
or PAL televisions.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer for detecting lack of peripheral
activity
- SUSP# modulation to adjust the system perform-
ance in various power down states of the system
including full power on state.
- Power control outputs to disable power from dif-
ferent planes of the board.
The digital PAL/NTSC encoder outputs interlaced
or non-interlaced video in PAL-B,D,G,H,I PAL-N,
PAL-M or NTSC-M standards and “NTSC- 4.43” is
also possible.
Lack of system activity for progressively longer
period of times is detected by the three power
down timers. These timers can generate SMI in-
terrupts to CPU so that the SMM software can put
the system in decreasing states of power con-
sumption. Alternatively, system activity in a power
down state can generate SMI interrupt to allow the
software to bring the system back up to full power
on state. The chip-set supports up to three power
down states: Doze state, Stand-by state and Sus-
pend mode. These correspond to decreasing lev-
els of power savings.
The four frame (for PAL) or 2 frame (for NTSC)
burst sequences are internally generated, subcar-
rier generation being performed numerically with
CKREF as reference. Rise and fall times of syn-
chronisation tips and burst envelope are internally
controlled according to the relevant ITU-R and
SMPTE recommendations.
Video output signals are directed to four analog
output pins through internal D/A converters giving,
simultaneous R,G,B and composite CVBS out-
puts.
POWER DOWN
Power down puts the STPC Consumer-S into sus-
pend mode. The processor completes execution
of the current instruction, any pending decoded in-
structions and associated bus cycles. During the
suspend mode, internal clocks are stopped. Re-
moving power down, the processor resumes in-
struction fetching and begins execution in the in-
struction stream at the point it had stopped. Be-
cause of the static nature of the core, no internal
data is lost.
IDE INTERFACE
An industry standard EIDE (ATA 2) controller is
built into the STPC Consumer-S. The IDE port is
capable of supporting a total of four devices.
POWER MANAGEMENT
The STPC Consumer-S core is compliant with the
Advanced Power Management (APM) specifica-
tion to provide a standard method by which the
BIOS can control the power used by personal
computers. The Power Management Unit module
(PMU) controls the power consumption providing
a comprehensive set of features that control the
power usage and supports compliance with the
United States Environmental Protection Agency’s
Energy Star Computer Program. The PMU pro-
vides following hardware structures to assist the
software in managing the power consumption by
the system.
- System Activity Detection.
- Three power down timers.
- Doze timer for detecting lack of system activity
for short durations.
- Stand-by timer for detecting lack of system activ-
ity for medium durations
- Suspend timer for detecting lack of system activ-
ity for long durations.
- House-keeping activity detection.
5/51
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GENERAL DESCRIPTION
Figure 2. Functionnal description.
Host
I/F
x86
Core
PCI BUS
PCI m/s
PMU
watch-
ISA
m/s
IPC
82C206
IDE
I/F
PCI m/s
ISA Bus
Local
Local Bus
Bus I/F
Video Pipeline
- Pixel formating
- Scaler
- Colour Space
Colour Key
Chroma Key
LUT
Monitor
SVGA
CRTC
TVO
- CSC
- FF
- CCIR
HW Cursor
GE
NTSC/PAL
Encoder
TV
CCIR Input
VIP
SDRAM
I/F
6/51
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GENERAL DESCRIPTION
Figure 3. Typical Application
Keyboard / Mouse
Serial Ports
Parallel Port
Floppy
Super I/O
RTC
Flash
2x EIDE
ISA
DMUX
MUX
IRQ
Monitor
SVGA
MUX
DMA.REQ
TV
S-VHS
RGB
PAL
STPC Consumer-S
DMA.ACK
NTSC
DMUX
Video
CCIR601
CCIR656
PCI
4x 16-bit SDRAMs
7/51
Release B
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GENERAL DESCRIPTION
8/51
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Update History for Video controller chapter
1.1 UPDATE HISTORY FOR VIDEO CONTROLLER CHAPTER
The following changes have been made to the General Description Chapter on 29/10/99.
Section
1
Change
Text
“The STPC Consumer-S has in addition to the 5ST86 a TFT output, a Local
Bus interface, a WatchDog and a JTAG interface.”
Removed
9/51
Release B
PIN DESCRIPTION
2 PIN DESCRIPTION
2.1 INTRODUCTION
The STPC Consumer-S integrates most of the
functionalities of the PC architecture. As a result,
many of the traditional interconnections between
the host PC microprocessor and the peripheral
devices are totally internal to the STPC Consum-
er-S. This offers improved performance due to the
tight coupling of the processor core and these pe-
ripherals. As aresult many of the external pin con-
nections are made directly to the on-chip peripher-
al functions.
Table 2.1. Signal Description
Group name
System Clocks & Resets
Memory Interface
PCI interface
ISA
Qty
11
95
60
79
34
49
IDE
89
Local Bus
Video Input
11
8
TV Output
Figure 2.1 shows the STPC Consumer-S external
interfaces. It defines the main busses and their
function. Table 2.1 describes the physical imple-
mentation listing signals type and their functionali-
ty. Table 2.2 provides a full pin listing and descrip-
tion of pins. Table 2.5 provides a full listing of pin
locations of the STPC Consumer-S package by
physical connection.
VGA Monitor interface
Grounds
8
71
29
6
V
DD
Analog specific V /V
CC DD
Total Pin Count
388
Note: Several interface pins are multiplexed with
other functions, refer to Table 2.3 and Table 2.4
for further details
Figure 2.1. STPC Consumer-S External Interfaces
x86
STPC CONSUMER-S
PCI
SDRAM VGA VIP
TV
SYS
11
ISA/IDE/LB
95
8
11
8
60
89
10/51
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PIN DESCRIPTION
Table 2.2. Definition of Signal Pins
Signal Name
Dir
Description
System Power Good Input
Qty
BASIC CLOCKS AND RESETS
SYSRSTI#
SYSRSTO#
XTALI
I
1
1
1
O
System Reset Output
14.3MHz Crystal Input
I
XTALO
I/O
I/O
O
14.3MHz Crystal Output - External Oscillator Input
Host Clock (Test)
1
1
1
1
HCLK
DEV_CLK
DCLK
24MHz Peripheral Clock (floppy drive)
27-135MHz Graphics Dot Clock
I/O
MEMORY INTERFACE
MCLKI
I
O
O
O
I/O
O
O
O
O
Memory Clock Input
Memory Clock Output
DIMM Chip Select
1
1
MCLKO
CS#[3:0]
4
MA[11:0]
Memory Row & Column Address
Memory Data
12
64
2
MD[63:0]
RAS#[1:0]
CAS#[1:0]
MWE#
Row Address Strobe
Column Address Strobe
Write Enable
2
1
DQM[7:0]
Data Input/Output Mask
8
PCI INTERFACE
PCI_CLKI
PCI_CLKO
AD[31:0]
I
O
33MHz PCI Input Clock
33MHz PCI Output Clock (from internal PLL)
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
1
1
I/O
I/O
I/O
I/O
I/O
I
32
4
CBE#[3:0]
FRAME#
IRDY#
1
Initiator Ready
1
TRDY#
Target Ready
1
LOCK#
PCI Lock
1
DEVSEL#
STOP#
I/O
I/O
I/O
O
Device Select
1
Stop Transaction
1
PAR
Parity Signal Transactions
System Error
1
SERR#
1
PCIREQ#[2:0]
PCI_GNT#[2:0]
PCI_INT[3:0]
VDD5
I
PCI Request
3
O
PCI Grant
3
I
PCI Interrupt Request
5V Power Supply for PCI ESD protection
4
I
4
ISA CONTROL
ISA_CLK
O
O
ISA Clock Output - Multiplexer Select Line For IPC
ISA Clock x2 Output - Multiplexer Select Line For IPC
ISA bus synchronisation clock
Unlatched Address
1
1
ISA_CLK2X
OSC14M
O
1
LA[23:17]
O
7
SA[19:0]
I/O
I/O
O
Latched Address
20
16
1
SD[15:0]
Data Bus
ALE
Address Latch Enable
MEMR#, MEMW#
SMEMR#, SMEMW#
I/O
O
Memory Read and Memory Write
System Memory Read and Memory Write
2
2
11/51
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PIN DESCRIPTION
Table 2.2. Definition of Signal Pins
Signal Name
IOR#, IOW#
Dir
I/O
I
Description
Qty
2
2
1
1
1
1
1
1
1
1
1
4
2
3
1
1
1
1
1
1
I/O Read and Write
MCS16#, IOCS16#
BHE#
Memory/IO Chip Select16
System Bus High Enable
Zero Wait State
O
I
ZWS#
REF#
O
I
Refresh Cycle.
MASTER#
AEN
Add On Card Owns Bus
Address Enable
O
I
IOCHCK#
IOCHRDY
ISAOE#
I/O Channel Check.
I/O
O
I/O
I
I/O Channel Ready (ISA) - Busy/Ready (IDE)
ISA/IDE Selection
GPIOCS#
IRQ_MUX[3:0]
DREQ_MUX[1:0]
DACK_ENC[2:0]
TC
General Purpose Chip Select
Time-Multiplexed Interrupt Request
Time-Multiplexed DMA Request
Encoded DMA Acknowledge
ISA Terminal Count
I
O
O
O
I/O
I/O
I/O
I/O
RTCAS
Real Time Clock Address Strobe
ROM/RTC Chip Select
Keyboard Chip Select
RMRTCCS#
KBCS#
RTCRW#
RTCDS
RTC Read/Write
RTC Data Strobe
LOCAL BUS
PA[21:0]
O
I/O
O
O
I
Address Bus
22
16
2
PD[15:0]
Data Bus
PRD1#,PRD0#
PWR1#,PWR0#
PRDY#
Peripheral Read Control
Peripheral Write Control
Data Ready
2
1
FCS1#, FCS0#
IOCS#[3:0]
O
O
Flash Chip Select
I/O Chip Select
2
4
IDE CONTROL
DA[2:0]
O
I/O
O
O
I
Address Bus
3
16
4
DD[15:0]
Data Bus
PCS3#,PCS1#,SCS3#,SCS1#
DIORDY
Primary & Secondary Chip Selects
Data I/O Ready
1
PIRQ, SIRQ
Primary & Secondary Interrupt Request
Primary & Secondary DMA Request
Primary & Secondary DMA Acknowledge
Primary & Secondary I/O Channel Read
Primary & Secondary I/O Channel Write
2
PDRQ, SDRQ
PDACK#, SDACK#
PDIOR#, SDIOR#
PDIOW#, SDIOW#
I
2
O
O
O
2
2
2
MONITOR INTERFACE
RED, GREEN, BLUE
VSYNC
O
O
O
I
Analog Red, Green, Blue
Vertical Sync
3
1
1
1
1
1
HSYNC
Horizontal Sync
DAC Voltage reference
Resistor Set
VREF_DAC
RSET
I
COMP
I
Compensation
12/51
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PIN DESCRIPTION
Table 2.2. Definition of Signal Pins
Signal Name
VIDEO INPUT
Dir
Description
27-33MHz Video Input Port Clock
Qty
VCLK
I
1
8
1
1
VIN
I
CCIR 601 or 656 YUV Video Data Input
Composite Synch or Horizontal line SYNC output
Frame Synchronisation
VCS
I/O
I/O
ODD_EVEN
ANALOG TV OUTPUT
RED_TV, GREEN_TV, BLUE_TV
CVBS
O
O
I
Analog RGB or S-VHS outputs
Analog video composite output
Reference current of 9bit DAC for CVBS
Reference voltage of 9bit DAC for CVBS
Reference current of 8bit DAC for R,G,B
Reference voltage of 8bit DAC for R,G,B
Analog Vss for DAC
3
1
1
1
1
1
1
1
IREF1_TV
VREF1_TV
I
IREF2_TV
I
VREF2_TV
I
VSSA_TV
I
VDDA_TV
I
Analog Vdd for DAC
MISCELLANEOUS
SPKRD
O
I/O
I/O
I
Speaker Device Output
1
SCL
I C Interface - Clock / Can be used for VGA DDC[1] signal
I C Interface - Data / Can be used for VGA DDC[0] signal
Reserved (Test pin)
1
1
1
SDA
SCAN_ENABLE
2.2 SIGNAL DESCRIPTIONS
2.2.1 BASIC CLOCKS AND RESETS
clock signal to the STPC Consumer-S device, the
TTL signal should be provided on XTALO.
SYSRSTI# System Reset/Power good. This input
is low when the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. This input is asynchronous to all clocks,
and acts as a negative active reset. The reset cir-
cuit initiates a hard reset on the rising edge of this
signal.
HCLK Host Clock. This clock supplies the CPU
and the host related blocks. This clock can e dou-
bled inside the CPU and is intended to operate in
the range of 25 to 100 MHz. This clock in generat-
ed internally from a PLL but can be driven directly
from the external system.
SYSRSTO# Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus reset is
an externally buffered version of this output.
DCLK Dot Clock / Pixel clock. This clock supplies
the display controller, the video pipeline, the ram-
dac, and the TV output logic. Its value is depend-
ent on the selected display mode.
Its frequency can be as high as 135 MHz. This sig-
nal is either driven by the internal PLL either by an
external oscillator. The direction can be controlled
by a strap option or an internal register bit.
XTALI 14.3MHz Crystal Input
XTALO 14.3MHz Crystal Output. These pins are
connected to the 14.318 MHz crystal to provide
the reference clock for the internal frequency syn-
thesizer to generate all the other clocks.
A 14.318 MHz Series Cut Crystal should be con-
nected between these two pins. Balance capaci-
tors of 15 pF should also be added. In the event of
an external quarzt oscillator providing the master
DEV_CLK 24MHz Peripheral Clock. This 24MHZ
signal is provided as a convenience for the system
integration of a Floppy Disk driver function in an
external chip.
13/51
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PIN DESCRIPTION
2.2.2 MEMORY INTERFACE
2.2.3 PCI INTERFACE
MCLKO Memory Clock Output. This clock is driv-
ing the DIMMs on board and is generated from an
internal PLL. The default value is 66MHz.
PCI_CLKI 33MHz PCI Input Clock. This signal is
the PCI bus clock input and should be driven from
the PCI_CLKO pin.
MCLKI Memory Clock Input. This clock is driving
the SDRAM controller, the graphics engine and
display controller. This input should be a buffered
version of the MCLKO signal with the track lengths
between the buffer and the pin matched with the
track lengths between the buffer and the DIMMs.
PCI_CLKO 33MHz PCI Output Clock. This is the
master PCI bus clock output.
AD[31:0] PCI Address/Data. This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and data phase of write transactions. It is
driven by the target during data phase of read
transactions.
CS#[3:0] Chip Select These signals are used to
disable or enable device operation by masking or
enabling all SDRAM inputs except MCLK, CKE,
and DQM.
CBE#[3:0] Bus Commands/Byte Enables. These
are the multiplexed command and byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the byte enable information.
These pins are inputs when a PCI master other
than the STPC Consumer-S owns the bus and
outputs when the STPC Consumer-S owns the
bus.
MA[11:0] Memory Address. Multiplexed row and
column address lines.
MD[63:0] Memory Data. This is the 64-bit memory
data bus. MD[40-0] are read by the device strap
option registers during rising edge of SYSRSTI#.
RAS#[1:0] Row Address Strobe. These signals
enable row access and precharge. Row address
is latched on rising edge of MCLK when RAS# is
low.
FRAME# Cycle Frame. This is the frame signal of
the PCI bus. It is an input when aPCI master owns
the bus and is an output when STPC Consumer-S
owns the PCI bus.
CAS#[1:0] Column Address Strobe. These sig-
nals enable column access. Column address is
latched on rising edge of MCLK when CAS# is
low.
IRDY# Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Consumer-S initiates a bus cycle on the
PCI bus. It is used as an input during the PCI cy-
cles targeted to the STPC Consumer-S to deter-
mine when the current PCI master is ready to
complete the current transaction.
MWE# Write Enable. Write enable specifies
whether thememory access is a read (MWE# = H)
or a write (MWE# = L).
TRDY# Target Ready. This is the target ready sig-
nal of the PCI bus. It is driven as an output when
the STPC Consumer-S is the target of the current
bus transaction. It is used as an input when STPC
Consumer-S initiates a cycle on the PCI bus.
DQM#[7:0] Data Mask. Makes data output Hi-Z
after the clock and masks the SDRAM outputs.
Blocks SDRAM data input when DQM active.
LOCK# PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
14/51
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PIN DESCRIPTION
DEVSEL# I/O Device Select. This signal is used
as an input when the STPC Consumer-S initiates
a bus cycle on the PCI bus to determine if a PCI
slave device has decoded itself to be the target of
the current transaction. It is asserted as an output
either whenthe STPC Consumer-S is the target of
the current PCI transaction or when no other de-
vice asserts DEVSEL# prior to the subtractive de-
code phase of the current PCI transaction.
2.2.4 ISA INTERFACE
ISA_CLK, ISA_CLKX2 ISA Clock x1, x2. These
pins generate the Clock signal for the ISA bus and
a Doubled Clock signal. They are also used as the
multiplexor control lines for the Interrupt Controller
Interrupt input lines. ISA_CLK is generated from
either PCICLK/4 or OSC14M/ 2.
OSC14M ISA bus synchronisation clock Output.
This is the buffered 14.318 Mhz clock for the ISA
bus.
STOP# Stop Transaction. Stop is used to imple-
ment the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cy-
cles initiated by the STPC Consumer-S and is
used as an output when a PCI master cycle is tar-
geted to the STPC Consumer-S.
LA[23:17] Unlatched Address. When the ISA bus
is active, these pins are ISA Bus unlatched ad-
dress for 16-bit devices. When ISA bus is ac-
cessed by any cycle initiated from PCI bus, these
pins are in output mode. When an ISA bus master
owns the bus, these pins are in input mode.
PAR Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to guar-
antee even parity across AD[31:0], CBE#[3:0],
and PAR. This signal is driven by the master dur-
ing the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identi-
cal to that of the AD bus delayed by one PCI clock
cycle)
SA[19:0] ISA Address Bus. System address bus
of ISA on 8-bit slot. These pins are used as an in-
put when an ISA bus master owns the bus and are
outputs at all other times.
SD[15:0] I/O Data Bus. These pins are the exter-
nal databus to the ISA bus.
SERR# System Error. This is the system error sig-
nal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if target aborts a STPC
Consumer-S initiated PCI transaction. Its asser-
tion by either the STPC Consumer-S orby another
PCI bus agent will trigger the assertion of NMI to
the host CPU. This is an open drain output.
ALE Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Consumer-S to indicate that LA23-
17, SA19-0, AEN and SBHE# signals are valid.
The ALE is driven high during refresh, DMA mas-
ter or an ISA master cycles by the STPC Consum-
er-S. ALE is driven low after reset.
PCIREQ#[2:0] PCI Request. This pin are the
three external PCI master request pins. They indi-
cates to the PCI arbiter that the external agents
desire use of the bus.
MEMR# Memory Read. This is the memory read
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
PCI_GNT#[2:0] PCI Grant. These pins indicate
that the PCI bus has been granted to the master
requesting it on its PCIREQ#.
The MEMR# signal is active during refresh.
MEMW# Memory Write. This is the memory write
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
PCI_INT[3:0] PCI Interrupt Request. These are
the PCI bus interrupt signals.
VDD5 5V Power Supply. These power pins are
necessary for 5V ESD protection. In case the PCI
bus is used in 3.3V only, these pins can be con-
nected to 3.3V.
SMEMR# System Memory Read. The STPC Con-
sumer-S generates SMEMR# signal of the ISA
bus only whenthe address is below one megabyte
or the cycle is a refresh cycle.
15/51
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PIN DESCRIPTION
SMEMW# System Memory Write. The STPC Con-
sumer-S generates SMEMW# signal of the ISA
bus only when the address is below one mega-
byte.
MASTER# Add On Card Owns Bus. This signal is
active when an ISA device has been granted bus
ownership.
AEN Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to indi-
cate that a DMA transfer will occur. The enabling
of the signal indicates to IO devices to ignore the
IOR#/IOW# signal during DMA transfers.
IOR# I/O Read. This is the IO read command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
IOW# I/O Write. This is the IO write command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
IOCHCK# IO Channel Check. IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal be-
comes active upon seeing IOCHCK# active if the
corresponding bit in Port B is enabled.
MCS16# Memory Chip Select16. This is the de-
code of LA23-17 address pins of the ISA address
bus without any qualification of the command sig-
nal lines. MCS16# is always an input. The STPC
Consumer-S ignores this signal during IO and re-
fresh cycles.
IOCHRDY Channel Ready. IOCHRDY is the IO
channel ready signal of the ISA bus and is driven
as an output in response to an ISA master cycle
targeted to the host bus or an internal register of
the STPC Consumer-S. The STPC Consumer-S
monitors this signal as an input when performing
an ISA cycle on behalf of the host CPU, DMA
master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Consumer-
S since the access to the system memory can be
considerably delayed due UMA architecture.
IOCS16# IO Chip Select16. This signal is the de-
code of SA15-0 address pins of the ISA address
bus without any qualification of the command sig-
nals. The STPC Consumer-S does not drive
IOCS16# (similar to PC-AT design). An ISA mas-
ter access to an internal register of the STPC Con-
sumer-S is executed as an extended 8-bit IO cy-
cle.
ISAOE# Bidirectional OE Control. This signal con-
trols the OE signal of the external transceiver that
connects the IDE DD bus and ISA SA bus.
BHE# System Bus High Enable. This signal, when
asserted, indicates that a data byte is being trans-
ferred on SD15-8 lines. It is used as an input when
an ISA master owns the bus and is an output at all
other times.
GPIOCS# I/O General Purpose Chip Select. This
output signal is used by the external latch on ISA
bus to latch the data on the SD[7:0] bus. The latch
can be use by PMU unit to control the external pe-
ripheral devices or any other desired function.
ZWS# Zero Wait State. This signal, when assert-
ed by addressed device, indicates that current cy-
cle can be shortened.
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They
have to be encoded before connection to the
STPC Consumer-S using ISACLK and ISACLKX2
as the input selection strobes.
Note that IRQ8B, which by convention is connect-
ed to the RTC, is inverted before being sent to the
interrupt controller, so that it may be connected di-
rectly to the IRQ pin of the RTC.
REF# Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Consumer-S performs a refresh
cycle on the ISA bus. It is used as an input when
an ISA master owns the bus and is used to trigger
a refresh cycle.
The STPC Consumer-S performs a pseudo hid-
den refresh. It requests the host bus for two host
clocks to drive the refresh address and capture it
in external buffers. The host bus is then relin-
quished while the refresh cycle continues on the
ISA bus.
DREQ_MUX[1:0] ISA Bus Multiplexed DMA Re-
quest. These are the ISA bus DMA request sig-
nals. They are to be encoded before connection to
the STPC Consumer-S using ISACLK and
ISACLKX2 as the input selection strobes.
16/51
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PIN DESCRIPTION
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Consumer-S before output
and should be decoded externally using ISACLK
and ISACLKX2 as the control strobes.
2.2.6 LOCAL BUS
PA[21:0] Address Bus Output.
PD[15:0] Data Bus. This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the byte count expires.
PWR#[1:0] Write Control output. PWR0# is used
to write the LSB and PWR1# to write the MSB.
PRD#[1:0] Read Control output. PRD0# is used
to read the LSB and PRD1# to read the MSB.
2.2.5 X-Bus Interface pins
PRDY# Data Ready input. This signal is used to
create wait states on the bus. When low, it com-
pletes the current cycle.
RTCAS# Real time clock address strobe. This sig-
nal is asserted for any I/O write to port 70H.
RMRTCCS# ROM/Real Time clock chip select.
This signal is asserted if a ROM access is decod-
ed during a memory cycle. It should be combined
with MEMR# or MEMW# signals to properly ac-
cess the ROM. During a IO cycle, this signal is as-
serted if access to the Real Time Clock (RTC) is
decoded. It should be combined with IOR or IOW#
signals to properly access the real time clock.
FCS#[1:0] Flash Chip Select output. These are
the Programmable Chip Select signals for up to 2
banks of Flash memory.
IOCS#[3:0] I/O Chip Select output. These are the
Programmable Chip Select signals for up to 4 ex-
ternal I/O devices.
KBCS# Keyboard Chip Select. This signal is as-
serted if a keyboard access is decoded during a I/
O cycle.
RTCRW# Real Time Clock RW. This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCRW#. This signal is asserted for any
I/O write to port 71H.
RTCDS# Real Time Clock DS. This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCDS. This signal is asserted for any I/
O read to port 71H.
Note: RMRTCCS#, KBCS#, RTCRW# and
RTCDS# signals must be ORed externally with
ISAOE# and then connected to the external de-
vice. An LS244 or equivalent function can be used
if OE# is connected to ISAOE# and the output is
provided with a weak pull-up resistor as shown in
Figure 2.2.
17/51
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PIN DESCRIPTION
2.2.7 IDE INTERFACE
2.2.8 Monitor Interface
PCS1#, PCS3# Primary Chip Select. These sig-
nals are used as the active high primary master &
slave IDE chip select signals. These signals must
be externally ANDed with the ISAOE# signal be-
fore driving the IDE devices to guarantee it is ac-
tive only when ISA bus is idle.
RED, GREEN, BLUE RGB Video Outputs. These
are the 3 analog color outputs from the RAMDACs
VSYNC Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
SCS1#, SCS3# Secondary Chip Select. These
signals are used as the active high secondary
master & slave IDE chip select signals. These sig-
nals must be externally ANDed with the ISAOE#
signal before driving the IDE devices to guarantee
it is active only when ISA bus is idle.
HSYNC Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC DAC Voltage reference. An external
voltage reference is connected to this pin to bias
the DAC.
DA[2:0] Address. These signals are connected to
DA[2:0] of IDE devices directly or through a buffer.
If the toggling of signals are to be masked during
ISA bus cycles, they can be externally ORed with
ISAOE# before being connected to the IDE devic-
es.
RSET Resistor Current Set. This reference cur-
rent input to the RAMDAC is used to set the full-
scale output of the RAMDAC.
COMP Compensation. This is the RAMDAC com-
pensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
DD[15:0] Databus. When the IDE bus is active,
they serve as IDE signals DD[11:0]. IDE devices
are connected to SA[19:8] directly and ISA bus is
connected to these pins through two LS245 trans-
ceivers as described in Figure 2.2.
V
DD
to damp oscillations.
DIORDY Busy/Ready. This pin serves as IDE sig-
nal DIORDY.
PIRQ Primary Interrupt Request.
SIRQ Secondary Interrupt Request.
Interrupt request from IDE channels.
PDRQ Primary DMA Request.
SDRQ Secondary DMA Request.
DMA request from IDE channels.
PDACK# Primary DMA Acknowledge.
SDACK# Secondary DMA Acknowledge.
DMA acknoledge to IDE channels.
PDIOR#, PDIOW# Primary I/O Read & Write.
SDIOR#, SDIOW# Secondary I/O Read & Write.
Primary & Secondary channel read & write.
18/51
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PIN DESCRIPTION
2.2.9 VIDEO INTERFACE
2.2.10 TV OUTPUT
VCLK Pixel Clock Input.This signal is used to syn-
chronise data being transfered from an external
video device to either the frame buffer, or alterna-
tively out the TV output in bypass mode. This pin
can be sourced from STPC if no external VCLK is
detected, or can be input from an external video
clock source.
RED_TV / C_TV Analog video outputs synchro-
nized with CVBS. This output is current-driven and
must be connected to analog ground over a load
resistor (R
). Following the load resistor, a
LOAD
simple analog low pass filter is recommended. In
S-VHS mode, this is the Chrominance Output.
GREEN_TV / Y_TV Analog video outputs syn-
chronized with CVBS. This output is current-driv-
en and must be connected to analog ground over
VIN[7:0] YUV Video Data Input CCIR 601 or 656.
Time multiplexed 4:2:2 luminance and chromi-
nance data as defined in ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This bus
typically carries a stream of Cb,Y,Cr,Y digital vid-
eo at VCLK frequency, clocked on the rising edge
(by default) of VCLK.
a load resistor (R
). Following the load resis-
LOAD
tor, a simple analog low pass filter is recommend-
ed. In S-VHS mode, this is the Luminance Output.
BLUE_TV / CVBS Analog video outputs synchro-
nized with CVBS. This output is current-driven and
must be connected to analog ground over a load
resistor (R
). Following the load resistor, a
VCS Line synchronisation Output. This pin is an
input in ODDEV+HSYNC or VSYNC + HSYNC or
VSYNC slave modes and an output in all other
modes (master/slave)
LOAD
simple analog low pass filter is recommended. In
S-VHS mode, this is a second composite output.
CVBS Analog video composite output (luminance/
chrominance). CVBS is current-driven and must
be connected to analog ground over a load resis-
ODD_EVEN Frame Synchronisation Ourput. This
pin supports the Frame synchronisation signal. It
is an input in slave modes, except when sync is
extracted from YCrCbdata, and an output in mas-
ter mode and when sync is extracted from YCrCb
data
tor (R
). Following the load resistor, a simple
LOAD
analog low pass filter is recommended.
The signal is synchronous to rising edge of DCLK.
The default polarity for this pin is:
IREF1_TV Ref. current for CVBS 10-bit DAC.
IREF2_TV Reference current for RGB 9-bit DAC.
VREF1_TV Ref. voltage for CVBS 10-bit DAC.
VREF2_TV Reference voltage for RGB 9-bit DAC.
- odd (not-top) field : LOW level
- even (bottom) field : HIGH level
VSSA_TV Analog V
for DACs.
for DACs.
SS
VDDA_TV Analog V
DD
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PIN DESCRIPTION
2.2.11 MISCELLANEOUS
SPKRD Speaker Drive. This the output to the
speaker and is AND of the counter 2 output with
bit 1 of Port 61, and drives an external speaker
driver. This output should be connected to 7407
type high voltage driver.
SCL, SDA I C Interface. These bidirectional pins
are connected to CRTC register 3Fh to implement
2
DDC capabilities. They conform to I C electrical
specifications, they have open-collector output
drivers which are internally connected to V
through pull-up resistors.
DD
They can be used for the DDC1 (SCL) and DDC0
(SDA) lines of the VGA interface.
SCAN_ENABLE Reserved. The pin is reserved
for Test and Miscellaneous functions.
20/51
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PIN DESCRIPTION
Table 2.3. ISA / IDE dynamic multiplexing
Table 2.4. ISA / Local Bus pin sharing
.
.
ISA BUS
(ISAOE# = 0)
IDE
(ISAOE# = 1)
ISA / IPC
SD[15:0]
LOCAL BUS
PD[15:0]
RMRTCCS#
DD[15]
DREQ_MUX[1:0]
SMEMR#
PA[21:20]
PA[19]
KBCS#
RTCRW#
RTCDS
SA[19:8]
LA[23]
DD[14]
DD[13]
DD[12]
DD[11:0]
SCS3#
SCS1#
PCS3#
PCS1#
DA[2:0]
DIORDY
MEMW#
PA[18]
BHE#
PA[17]
AEN
PA[16]
ALE
PA[15]
LA[22]
MEMR#
PA[14]
SA[21]
IOR#
PA[13]
SA[20]
IOW#
PA[12]
LA[19:17]
IOCHRDY
REF#
PA[11]
IOCHCK#
PA[10]
GPIOCS#
PA[9]
ZWS#
PA[8]
SA[7:4]
PA[7:4]
PA[3:0]
PRDY
TC, DACK_ENC[2:0]
SA[3]
ISAOE#,SA[2:0]
DEV_CLK, RTCAS#
IOCS16#, MASTER#
SMEMW#, MCS16#
ISACLK, ISA_CLK2X
IOCS#[3:0]
FCS#[1:0]
PRD#[1:0]
PWR#[1:0]
Figure 2.2. Typical ISA/IDE Demultiplexing
STPC bus / DD[15:0]
74LS245
A
B
RMRTCCS#
KBCS#
RTCRW#
RTCDS
MASTER#
ISAOE#
DIR
OE
SA[19:8]
PCS1#
PCS3#
SCS1#
SCS3#
LA[22]
LA[23]
LA[22]
LA[23]
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PIN DESCRIPTION
Table 2.5. Pinout.
Pin #
U3
Pin name
MD[10]
Pin #
T25
Pin name
MD[59]
Pin #
AF3
Pin name
V1
MD[11]
MD[12]
MD[13]
MD[14]
MD[15]
MD[16]
MD[17]
MD[18]
MD[19]
MD[20]
MD[21]
MD[22]
MD[23]
MD[24]
MD[25]
MD[26]
MD[27]
MD[28]
MD[29]
MD[30]
MD[31]
MD[32]
MD[33]
MD[34]
MD[35]
MD[36]
MD[37]
MD[38]
MD[39]
MD[40]
MD[41]
MD[42]
MD[43]
MD[44]
MD[45]
MD[46]
MD[47]
MD[48]
MD[49]
MD[50]
MD[51]
MD[52]
MD[53]
MD[54]
MD[55]
MD[56]
MD[57]
MD[58]
U24
T26
R25
R26
F24
D25
B20
C20
B19
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
B15
A15
C16
B14
D15
A14
B13
D13
A13
C14
B12
C13
A12
C12
A11
D12
B10
C11
A10
D10
C10
A9
MD[60]
MD[61]
MD[62]
MD[63]
PCI_CLKI
PCI_CLKO
AD[0]
SYSRSTI#
SYSRSTO#
XTALI
W2
AE4
V3
A3
Y2
C4
XTALO
HCLK
W4
G23
Y1
H24
DEV_CLK
DCLK
W3
AD11
AF15
AB23
AE16
AD15
AF16
AE17
AD16
AF17
AE18
AD17
AF18
AE19
AE20
AC19
AF22
AD21
AE24
AD23
AF23
AD22
AE21
AC20
AF20
AD19
AF21
AD20
AE22
AE23
AF19
AD18
AC22
R1
AA2
Y4
AD[1]
MCLKI
MCLKO
MA[0]
AD[2]
AA1
Y3
AD[3]
AD[4]
MA[1]
AB2
AB1
AA3
AB4
AC1
AB3
AD2
AC3
AD1
AF2
AF24
AE26
AD25
AD26
AC25
AC24
AC26
AB25
AB24
AB26
AA25
Y23
AA24
AA26
Y25
Y26
Y24
W25
V23
W26
W24
V25
V26
U25
V24
U26
U23
AD[5]
MA[2]
AD[6]
MA[3]
AD[7]
MA[4]
AD[8]
MA[5]
AD[9]
MA[6]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
CBE[0]
CBE[1]
CBE[2]
CBE[3]
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
PAR
MA[7]
MA[8]
MA[9]
MA[10]
MA[11]
CS#[0]
CS#[1]
CS#[2]
CS#[3]
RAS#[0]
RAS#[1]
CAS#[0]
CAS#[1]
DQM#[0]
DQM#[1]
DQM#[2]
DQM#[3]
DQM#[4]
DQM#[5]
DQM#[6]
DQM#[7]
MWE#
MD[0]
T2
MD[1]
R3
MD[2]
B8
T1
MD[3]
A8
R4
MD[4]
B7
U2
MD[5]
D8
T3
MD[6]
A7
U1
MD[7]
C8
U4
MD[8]
B6
V2
MD[9]
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PIN DESCRIPTION
Pin #
D7
Pin name
SERR#
Pin #
K24
Pin name
Pin #
B1
Pin name
PIRQ
SD[5]
SD[6]
SD[7]
SD[8]
SD[9]
A6
LOCK#
J26
C2
C1
D2
D3
D1
E2
E4
E3
E1
SIRQ
D20
C21
A21
C22
A22
B21
A5
PCI_REQ#[0]
PCI_REQ#[1]
PCI_REQ#[2]
PCI_GNT#[0]
PCI_GNT#[1]
PCI_GNT#[2]
PCI_INT[0]
PCI_INT[1]
PCI_INT[2]
PCI_INT[3]
VDD5
H25
H26
J24
PDRQ
SDRQ
PDACK#
SDACK#
PDIOR#
PDIOW#
SDIOR#
SDIOW#
G25
H23
D24
C26
A25
B24
SD[10]
SD[11]
SD[12]
SD[13]
SD[14]
SD[15]
C6
B4
D5
AF9
AE9
AD8
AC5
AE5
AC10
AE10
AD7
B5
RED
A16
B11
B9
AD4
AF4
C9
ISA_CLK
ISA_CLK2X
OSC14M
ALE
GREEN
BLUE
VDD5
VDD5
VSYNC
HSYNC
VREF_DAC
RSET
D18
VDD5
P25
AE8
R23
P26
R24
N25
N23
N26
P24
N24
M26
M25
L25
M24
L26
T24
M23
A4
ZWS#
F2
LA[17]/DA[0]
LA[18]/DA[1]
LA[19]/DA[2]
LA[20]/PCS1#
LA[21]/PCS3#
LA[22]/SCS1#
LA[23]/SCS3#
SA[0]
BHE#
G4
F3
MEMR#
COMP
SCL
MEMW#
F1
SMEMR#
SMEMW#
IOR#
C7
SDA
G2
G1
H2
J4
AE15
AD5
AF7
AF5
AE6
AC7
AD6
AF6
AE7
VCLK
VIN[0]
VIN[1]
VIN[2]
VIN[3]
VIN[4]
VIN[5]
VIN[6]
VIN[7]
IOW#
MCS16#
H1
H3
J2
SA[1]
IOCS16#
MASTER#
REF#
SA[2]
SA[3]
J1
SA[4]
AEN
K2
J3
SA[5]
IOCHCK#
IOCHRDY
ISAOE#
SA[6]
K1
K4
L2
SA[7]
SA[8]
RTCAS#
RTCDS#
RTCRW#
RMRTCCS#
GPIOCS#
IRQ_MUX[0]
IRQ_MUX[1]
IRQ_MUX[2]
IRQ_MUX[3]
DREQ_MUX[0]
DREQ_MUX[1]
DACK_ENC[0]
DACK_ENC[1]
DACK_ENC[2]
TC
AD10
AF11
AE12
AE13
AC12
AF14
AE11
AF12
AE14
AC14
AD12
AF8
RED_TV
SA[9]
P3
GREEN_TV
BLUE_TV
VCS
K3
L1
SA[10]
R2
SA[11]
P1
M2
M1
L3
SA[12]
AE3
E23
D26
E24
C25
A24
B23
C23
A23
B22
D22
C5
ODD_EVEN
CVBS
SA[13]
SA[14]
IREF1_TV
VREF1_TV
IREF2_TV
VREF2_TV
VDDA_TV
VDD_DAC1
VDD_DAC2
VSSA_TV
VSS_DAC1
VSS_DAC2
N2
M4
M3
P2
P4
K25
L24
K26
K23
J25
SA[15]
SA[16]
SA[17]
SA[18]
SA[19]
SD[0]
AD9
SD[1]
AF13
AC9
SD[2]
SD[3]
SPKRD
AF10
SD[4]
N3
KBCS#
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PIN DESCRIPTION
Pin #
B3
Pin name
Pin #
N4
Pin name
SCAN_ENABLE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N11:16
P11:16
P23
G24
AD13
F25
AC17
AC15
F26
A20
C15
D6
VDD_CPUCLK_PLL
VDD_DCLK_PLL
VDD_DEVCLK_PLL
R11:16
T11:16
V4
VDD_MCLKI_PLL
VDD_MCLKO_PLL
VDD_HCLK_PLL
VDD
W23
AC4
VDD
AC8
VDD
AC13
AC18
AC23
AD3
D11
D16
D21
F4
VDD
VDD
VDD
VDD
AD14
AD24
AE1:2
AE25
AF1
F23
G3
VDD
VDD
G26
L4
VDD
VDD
L23
VDD
AF25
AF26
N1
VDD
T4
VDD
T23
W1
VDD
VDD
AA4
AA23
AC6
AC2
AC11
AC16
AC21
VDD
VDD
VDD
VDD
VDD
VDD
VDD
E25
E26
A1:2
A26
B2
VSS_DLL
VSS_DLL
VSS
VSS
VSS
B25:26
C3
VSS
VSS
C24
D4
VSS
VSS
D9
VSS
D14
D19
D23
H4
VSS
VSS
VSS
VSS
J23
VSS
L11:16
M11:16
VSS
VSS
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STRAP OPTIONS
3 STRAP OPTIONS
This chapter defines the STPC Consumer-S Strap Options and their location
Memory
Data
Lines
Actual
Settings
Note
Refer to
Designation
Location
Set to ’0’
Set to ’1’
MD0
MD1
1
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCI_CLKO Divisor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HCLK PLL Speed
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MD2
-
-
-
-
MD3
-
-
-
-
MD4
-
-
-
-
MD5
-
-
-
-
MD6
-
-
-
-
MD7
-
-
-
-
MD8
-
-
-
-
MD9
-
-
-
-
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Index 4C,bit0
Pull up
-
PCI Clock
Index 4C,bit 1 User defined HCLK / 3
HCLK / 2
-
Index 4C,bit 2
Index 4C,bit 3
Index 4C, bit4
Index 5F, bit 0
Index 5F, bit 1
Index 5F,bit 2
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
-
-
-
-
-
-
HCLK
Index 5F,bit 3 User defined
Index 5F,bit 4 User defined
Index 5F,bit 5 User defined
000
001
010
011
100
101
110
111
25 MHz
33 MHz
100 MHz
50 MHz
60 MHz
66 MHz
75 MHz
90 MHz
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull down
Pull up
Pull up
Pull up
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STRAP OPTIONS
Memory
Data
Lines
Actual
Settings
Note
Refer to
Designation
Location
Set to ’0’
Set to ’1’
MD39
MD40
MD41
MD42
MD43
Reserved
CPU Mode
Reserved
Reserved
Reserved
Pull up
User defined
Pull down
Pull down
Pull down
CPU
DX1
DX2
Note;
1) This Strap Option selects between two different functional blocks, the first is the ISA and the other is
the VGA block.
3.1 STRAP REGISTER DESCRIPTION
Strap Option [16:0] are reserved.
3.1.1 STRAP REGISTER 2 INDEX 4CH (STRAP2)
Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the sta-
tus of pin MD[23]. Bit 4 is writeable, writes to other bits in this register have no effect. They are use by the
chip as follows:
Bit 4-2; Reserved
Bit 1; This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows:
0: PCI clock output = HCLK / 2
1: PCI clock output = HCLK / 3
Bit 0; Reserved
This register defaults to the values sampled on MD[23] & MD[20:16] pins after reset.
3.1.2 HCLK PLL STRAP REGISTER 0 INDEX 5FH (HCLK_Strap)
Bits 5-0 of this register reflect the status of pins MD[26:21] respectively.
They are use by the chip as follows:
Bits 5-3 These pins reflect the value sampled on MD[26:24] pins respectively and control the Host clock
frequency synthesizer.
Bit 2-0; Reserved
This register defaults to the values sampled on above pins after reset.
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STRAP OPTIONS
3.1.3 486 CLOCK PROGRAMMING (486_CLK)
The bit MD[40] is used to set the clock multiplication factor of the 486 core. With the MD[40] pin pulled low
the 486 will run in DX (x1) mode, while with the MD[40] pin pulled high the 486 will run in DX2 (x2) mode.
The default value of the resistor on this strap input should be a resister to gnd (DX mode).
Strap Options [43:41] and [39:27] are reserved.
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ELECTRICAL SPECIFICATIONS
4 ELECTRICAL SPECIFICATIONS
4.1 Introduction
The electrical specifications in this chapter are val-
id for the STPC Consumer-S.
4.2 Electrical Connections
4.2.1 Power/Ground Connections/Decoupling
be connected either to VDD or to VSS. Connect
active-high inputs to VDD through a 20 kΩ (±10%)
pull-down resistor and active-low inputs to VSS
and connect active-low inputs to VCC through a
20 kΩ (±10%) pull-up resistor to prevent spurious
operation.
Due to the high frequency of operation of the
STPC Consumer-S, it is necessary to install and
test this device using standard high frequency
techniques. The high clock frequencies used in
the STPC Consumer-S and its output buffer cir-
cuits can cause transient power surges when sev-
eral output buffers switch output levels simultane-
ously. These effects can be minimized by filtering
the DC power leads with low-inductance decou-
pling capacitors, using low impedance wiring, and
by utilizing all of the VSS and VDD pins.
4.2.3 Reserved Designated Pins
Pins designated reserved should be left discon-
nected. Connecting a reserved pin to a pull-up re-
sistor, pull-down resistor, or an active signal could
cause unexpected results and possible circuit
malfunctions.
4.2.2 Unused Input Pins
All inputs not used by the designer and not listed
in the table of pin connections in Chapter 3 should
4.3 Absolute Maximum Ratings
The following table lists the absolute maximum
ratings for the STPC Consumer-S device. Stress-
es beyond those listed under Table 4.1 limits may
cause permanent damage to the device. These
are stress ratings only and do not imply that oper-
ation under any conditions other than those spec-
ified in section ”Operating Conditions”.
Exposure to conditions beyond Table 4.1 may (1)
reduce device reliability and (2) result in prema-
ture failure even when there is no immediately ap-
parent sign of failure. Prolonged exposure to con-
ditions at or near the absolute maximum ratings
(Table 4.1) may also result in reduced useful life
and reliability.
Table 4.1. Absolute Maximum Ratings
Symbol
Parameter
Value
-0.3, 4.0
-0.3, VDD + 0.3
-40, +150
0, +70
Units
V
V
DC Supply Voltage
DDx
V , V
Digital Input and Output Voltage
Storage Temperature
V
I
O
T
°C
°C
W
STG
T
Operating Temperature
Total Power Dissipation
OPER
P
4.8
TOT
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ELECTRICAL SPECIFICATIONS
4.1 DC Characteristics
Table 4.2. DC Characteristics
Recommended Operating conditions : VDD = 3.3V ±0.3V, Tcase = 0 to 100°C unless otherwise specified
Symbol
Parameter
Operating Voltage
Supply Power
Test conditions
Min
Typ
3.3
3.2
Max
3.6
Unit
V
V
P
3.0
DD
DD
V
= 3.3V, H = 66Mhz
3.9
W
Mhz
V
DD
CLK
H
Internal Clock
(Note 1)
75
CLK
REF
V
DAC Voltage Reference
Output Low Voltage
Output High Voltage
Input Low Voltage
1.215
1.235
1.255
0.5
V
I
=1.5 to 8mA depending of the pin
=-0.5 to -8mA depending of the pin
Load
V
OL
Load
V
I
2.4
-0.3
-0.3
2.1
V
OH
V
Except XTALI
XTALI
0.8
0.9
V
IL
V
V
Input High Voltage
Except XTALI
XTALI
V
V
+0.3
V
IH
DD
2.35
-5
+0.3
V
DD
I
Input Leakage Current
Input Capacitance
Output Capacitance
Clock Capacitance
Input, I/O
(Note 2)
5
µA
pF
pF
pF
LK
C
IN
C
(Note 2)
OUT
C
(Note 2)
CLK
Notes:
1. MHz ratings refer to CPU clock frequency.
2. Not 100% tested.
4.1 AC Characteristics
Table 4.4 through Table 4.9 list the AC character-
istics including output delays, input setup require-
ments, input hold requirements and output float
delays. These measurements are based on the
measurement points identified in Figure 4.1. The
rising clock edge reference level VREF , and other
reference levels are shown in Table 4.3 below for
the STPC Consumer-S. Input or output signals
must cross these levels during testing.
Figure 4.1 shows output delay (A and B) and input
setup and hold times (C and D). Input setup and
hold times (C and D) are specified minimums, de-
fining the smallest acceptable sampling window a
synchronous input signal must be stable for cor-
rect operation.
Table 4.3. Drive Level and Measurement Points for Switching Characteristics
Symbol
Value
1.5
Units
V
V
V
V
REF
V
3.0
IHD
V
0.0
ILD
Note: Refer to Figure 4.1.
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ELECTRICAL SPECIFICATIONS
Figure 4.1. Drive Level and Measurement Points for Switching Characteristics
Tx
V
V
IHD
CLK:
Ref
ILD
V
A
MAX
B
MIN
Valid
Output n
Valid
Output n+1
V
OUTPUTS:
Ref
C
D
V
V
IHD
Valid
Input
INPUTS:
LEGEND:
Ref
ILD
V
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
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ELECTRICAL SPECIFICATIONS
Table 4.4. PCI Bus AC Timing
Name
t1
Parameter
Min
2
Max
11
11
11
11
11
11
11
11
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCI_CLKI to AD[31:0] valid
PCI_CLKI to FRAME# valid
PCI_CLKI to CBE#[3:0] valid
PCI_CLKI to PAR valid
t2
2
t3
2
t4
2
t5
PCI_CLKI to TRDY# valid
PCI_CLKI to IRDY# valid
2
T6
T7
T8
T9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
2
PCI_CLKI to STOP# valid
PCI_CLKI to DEVSEL# valid
PCI_CLKI to PCI_GNT# valid
AD[31:0] bus setup to PCI_CLKI
AD[31:0] bus hold from PCI_CLKI
PCI_REQ#[2:0] setup to PCI_CLKI
PCI_REQ#[2:0] hold from PCI_CLKI
CBE#[3:0] setup to PCI_CLKI
CBE#[3:0] hold to PCI_CLKI
IRDY# setup to PCI_CLKI
IRDY# hold to PCI_CLKI
2
2
2
7
0
10
0
7
0
7
0
FRAME# setup to PCI_CLKI
FRAME# hold from PCI_CLKI
7
0
Table 4.5. IDE Bus AC Timing
Name
t20
Parameter
Min
15
Max
Max
Unit
ns
DD[15:0] setup to PIOR#/SIOR# falling
DD[15:0} hold to PIOR#/SIOR# falling
t21
12
ns
Table 4.6. SDRAM Bus AC Timing
Name
Parameter
Min
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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ELECTRICAL SPECIFICATIONS
Table 4.7. Video Input/TV Output AC Timing
Name
t35
Parameter
Min
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
VIDEO_D[7:0] setup to VCLK
VIDEO_D[7:0] hold from VCLK
VCLK to VTV_BT# valid
VCLK to VTV_HSYNC valid
VTV_BT# setup to VCLK
VTV_BT# hold from VCLK
VTV_HSYNC setup to VCLK
VTV_HSYNC hold from VCLK
t36
2
t37
15
15
t38
t39
10
5
t40
t41
10
5
t42
Table 4.8. Graphics Adapter (VGA) AC Timing
Name
t43
Parameter
Min
Min
Max
45
Unit
ns
DCLK to VSYNC valid
DCLK to HSYNC valid
t44
45
ns
Table 4.9. ISA Bus AC Timing
Name
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
Parameter
Max
60
60
62
35
28
60
62
50
50
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XTALO to LA[23:17] bus active
XTALO to SA[19:0] bus active
XTALO to BHE# valid
XTALO to SD[15:0] bus active
PCI_CLKI to ISAOE# valid
XTALO to GPIOCS# valid
XTALO to ALE valid
XTALO to MEMW# valid
XTALO to MEMR# valid
XTALO to SMEMW# valid
XTALO to SMEMR# valid
XTALO to IOR# valid
XTALO to IOW# valid
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MECHANICAL DATA
5. MECHANICAL DATA
5.1 388-PIN PACKAGE DIMENSION
The pin numbering for the STPC 388-pin Plastic
BGA package is shown in Figure 5-1.
Dimensions are shown in Figure 5-2, Table 5-1
and Figure 5-3, Table 5-2.
Figure 5-1. 388-Pin PBGA Package - Top View
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
A
A
B
B
C
C
D
D
E
E
F
F
G
H
G
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
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Release B
MECHANICAL DATA
Figure 5-2. 388-pin PBGA Package - PCB Dimensions
A1 Ball Pad Corner
A
B
A
D
E
F
Detail
G
C
Table 5-1. 388-pin PBGA Package - PCB Dimensions
mm
inches
Typ
Symbols
Min
34.95
1.22
0.58
1.57
0.15
0.05
0.75
Typ
35.00
1.27
0.63
1.62
0.20
0.10
0.80
Max
35.05
1.32
0.68
1.67
0.25
0.15
0.85
Min
Max
A
B
C
D
E
F
1.375
0.048
0.023
0.062
0.006
0.002
0.030
1.378
0.050
0.025
0.064
0.008
0.004
0.032
1.380
0.052
0.027
0.066
0.001
0.006
0.034
G
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Release B
MECHANICAL DATA
Figure 5-3. 388-pin PBGA Package - Dimensions
C
F
D
E
Solderball
Solderball after collapse
B
G
A
Table 5-2. 388-pin PBGA Package - Dimensions
mm
inches
Symbols
Min
0.50
1.12
0.60
0.52
0.63
0.60
Typ
0.56
1.17
0.76
0.53
0.78
0.63
30.0
Max
0.62
1.22
0.92
0.54
0.93
0.66
Min
Typ
Max
A
B
C
D
E
F
0.020
0.044
0.024
0.020
0.025
0.024
0.022
0.046
0.030
0.021
0.031
0.025
11.8
0.024
0.048
0.036
0.022
0.037
0.026
G
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Release B
MECHANICAL DATA
5.2 388-PIN PACKAGE THERMAL DATA
388-pin PBGA package has a Power Dissipation
Capability of 4.5W which increases to 6W when
used with a Heatsink.
Structure in shown in Figure 5-4.
Thermal dissipation options are illustrated in Fig-
ure 5-5 and Figure 5-6.
Figure 5-4. 388-Pin PBGA structure
Signal layers
Power & Ground layers
Thermal balls
Figure 5-5. Thermal dissipation without heatsink
Board
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Ambient
Case
Junction
Rca
Rjc
6
6
The PBGA is centered on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
Board
8.5
Case
125
Junction
Board
Rjb
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Ambient
Rba
Ambient
Airflow = 0
Rja = 13 °C/W
Board temperature taken at the center balls
36/51
Release B
MECHANICAL DATA
Figure 5-6. Thermal dissipation with heatsink
Board
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Ambient
Case
Junction
Rca
Rjc
The PBGA is centered on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
3
6
Board
8.5
Case
50
Junction
Board
Rjb
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Ambient
Rba
Airflow = 0
Ambient
Board temperature taken at the center balls
Heat sink is 11.1°C/W
Rja = 9.5 °C/W
37/51
Release B
BOARD LAYOUT
6 BOARD LAYOUT
6.1 Thermal dissipation
Thermal dissipation of the STPC depends mainly
on supply voltage. As a result, when the system
does not need to work at 3.3V, it is interresting to
reduce the voltage to 3.15V for example. This may
save few 100’s of mW.
With such configuration the Plastic BGA 388 pack-
age does 90% of the thermal dissipation through
the ground balls, and especially the central ther-
mal balls which are directly connected to the die,
the remaining 10% is dissipated through the case.
Adding a heat sink reduces this value to 85%.
The second area to look at is unused interfaces
and functions. Depending on the application,
some input signals can be grounded, and some
blocks not powered or shutdown. Clock speed dy-
namic adjustment is also a solution that can be
used along with the integrated power manage-
ment unit.
As a result, some basic rules has to be applied
when routing the STPC in order to avoid thermal
problems.
First of all, the whole ground layer acts as a heat
sink and ground balls must be directly connected
to it as illustrated in Figure 6-1.
The standard way to route thermal balls to internal
ground layer implements only one via pad for each
ball pad, connected using a 8-mil wire.
If one ground layer is not enough, a second
ground plane may be added on solder side.
Figure 6-1. Ground routing
Pad for ground ball
Thru hole to ground layer
Note: For better visibility, ground balls are not all routed.
38/51
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BOARD LAYOUT
When considering thermal dissipation, the most
important - and not the more obvious - part of the
layout is the connection between the ground balls
and the ground layer.
To avoid solder wicking over to the via pads during
soldering, it is important to have a solder mask of
4 mil around the pad (NSMD pad), this gives a di-
ameter of 33 mil for a 25 mil ground pad.
A 1-wire connection is shown in Figure 6-2. The
use of a 8-mil wire results in a thermal resistance
of 105°C/W assuming copper is used (418 W/
m.°K). This high value is due to the thickness (34
µm) of the copper on the external side of the PCB.
To obtain the optimum ground layout, place the
vias directly under the ball pads. In this case no lo-
cal boar d distortion is tolerated.
The thickness of the copper on PCB layers is typ-
ically 34 µm for external layers and 17 µm for inter-
nal layers. That means thermal dissipation is not
good and temperature of the board is concentrat-
ed around the devices and falls quickly with in-
creased distance.
Considering only the central matrix of 36 thermal
balls and one via for each ball, the global thermal
resistance is 2.9°C/W. This can be easily im-
proved using four 10 mil wires to connect to the
four vias around the ground pad link as in Figure
6-3. This gives a total of 49 vias and a global re-
sistance for the 36 thermal balls of 0.6°C/W.
When it is possible to place a metal layer inside
the PCB, this improves dramatically the heat
spreading and hence thermal dissipation of the
board.
The use of a ground plane like in Figure 6-4 is
even better.
Figure 6-2. Recommended 1-wire ground pad layout
Pad for ground ball (diameter = 25 mil)
Solder Mask (4 mil)
Connection Wire (width = 10 mil)
Via (diameter = 24 mil)
Hole to ground layer (diameter = 12 mil)
1 mil = 0.0254 mm
Figure 6-3. Recommended 4-wire ground pad layout
4 via pads for each ground ball
39/51
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BOARD LAYOUT
Figure 6-4. Optimum layout for central ground ball
Clearance = 6mil
External diameter = 37 mil
Via to Ground layer
hole diameter = 14 mil
Solder mask
diameter = 33 mil
Pad for ground ball
diameter = 25 mil
connections = 10 mil
The PBGA Package dissipates also through pe-
ripheral ground balls. When a heat sink is placed
on the device, heat is more uniformely spread
throughout the moulding increasing heat dissipa-
tion through the peripheral ground balls.
The more via pads are connected to each ground
ball, the more heat is dissipated . The only limita-
tion is the risk of lossing routing channels.
Figure 6-5 shows a routing with a good trade off
between thermal dissipation and number of rout-
ing channels.
Figure 6-5. Global ground layout for good thermal dissipation
Via to ground layer
Ground pad
40/51
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BOARD LAYOUT
Figure 6-6. Bottom side layout and decoupling
Ground plane for thermal dissipation
Via to ground layer
A local ground plane on opposite side of the board
as shown in Figure 6-6 improves thermal dissipa-
tion. It is used to connect decoupling capacitances
but can also be used for connection to a heat sink
or to the system’s metal box for better dissipation.
This possibility of using the whole system’s box for
thermal dissipation is very usefull in case of high
temperature inside the system and low tempera-
ture outside. In that case, both sides of the PBGA
should be thermally connected to the metal chas-
sis in order to propagate the heat flow through the
metal. Figure 6-7 illustrates such implementation.
Figure 6-7. Use of metal plate for thermal dissipation
Die
Board
Metal planes
Thermal conductor
41/51
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BOARD LAYOUT
6.2 High speed signals
Some Interfaces of the STPC run at high speed
and have to be carefully routed or even shielded.
All the clocks haves to be routed first and shielded
for speeds of 27MHz or more. The high speed sig-
nals follow the same contrainsts, like the memory
control signals and the PCI control signals.
Here is the list of these interfaces, in decreasing
speed order:
The next interfaces to be routed are Memory, Vid-
eo/graphics, and PCI.
1) Memory Interface.
2) Graphics and video interfaces
3) PCI bus
All the analog noise sensitive signals have to be
routed in a separate area and hence can be rout-
ed indepedently.
4) 14MHz oscillator stage
Figure 6-8. Shielding signals
ground ring
shielded signal line
ground pad
ground pad
shielded signal lines
42/51
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BOARD LAYOUT
6.3 Memory interface
6.3.1 Introduction
In order to achieve SDRAM memory interfaces
which work at clock frequencies of 66MHz and
above, careful consideration has to be given to the
timing of the interface with all the various electrical
and physical constraints taken into consideration.
The guidelines described below are related to
SDRAM components on DIMM modules. For ap-
plications where the memories are directly sol-
dered to the motherboard, the PCB should be laid
out such that the trace lengths fit within the con-
straints shown here. The traces could be slightly
longer since the extra routing on the DIMM PCB is
no longer present but it is then up to the user to
verify the timings.
6.3.2 SDRAM Clocking Scheme
The SDRAM Clocking Scheme deserves a special
mention here. Basically the memory clock is gen-
erated on-chip through a PLL and goes directly to
the MCLKO output pin of the STPC. The nominal
frequency is 66MHz. Because of the high load
presented to the MCLK on the board by the
DIMMs it is recommeded to rebuffer the MCLKO
signal on the board and balance the skew to the
clock ports of the different DIMMs and the MCLKI
input pin of STPC.
Figure 6-9. Clock scheme
MCLKO
PLL
MCLKI
PLL
MA[] +Control
MD[]
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BOARD LAYOUT
6.3.3 Board Layout Issues
The physical layout of the motherboard PCB as-
sumed in this presentation is as shown in Figure
6-10. Because all the memory interface signal
balls are located in the same region of the STPC
device it is possible to orientate the device to re-
duce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100mm.
Figure 6-10. DIMM placement
35mm
STPC
35mm
15mm
SDRAM I/F
DIMM4
DIMM3
DIMM2
DIMM1
116mm
10mm
Solid power and ground planes are amust in order
to provide good return paths for the signals and to
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power
and ground planes to provide a low impedance
path between the planes for the return paths for
signal routings which change layers. If possible
the traces should be routed adjacent to the same
power or ground plane for the length of the trace.
driver to the DIMM CKn pins should be matched
exactly. Since the propagation speed can vary be-
tween PCB layers the clocks should be routed in a
consistent way. The routing to the STPC memory
input should be longer by 75mm to compensate
for the extra clock routing on the DIMM. Also a
20pF capacitor should be placed as near as pos-
sible to the clock input of the STPC to compensate
for the DIMM’s higher clock load. The impedance
of the trace used for the clock routing should be
7m5aWtc)h.edTtoo mthieniDmIMiseMccrlooscsktatrlakcteheimcploecdkasncseho(6u0ld-
be routed with spacing to adjacent tracks of at
least twice the clock trace width. For designs
which use SDRAMs directly mounted on the moth-
erboard PCB all the clock trace lengths should be
matched exactly.
For the SDRAM interface the most critical signal is
the clock. Any skew between the clocks at the
SDRAM components and the memory controller
will impact the timing budget. In order to get well
matched clocks at all the components it is recom-
mended that all the DIMM clock pins, STPC mem-
ory clock input (MCLKI) and any other component
using the memory clock are individually driven
from a low skew clock driver with matched routing
lengths. This is shown in Figure 6-11.
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are 2 types of DIMM devices; sin-
gle row and dual row. The dual row devices re-
quire 2 chip select signals to select between the
two rows. A STPC device with 4 chip select control
lines could control either 4 single row DIMMs or 2
dual row DIMMs.
The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew be-
tween the outputs. The delay through the buffer is
not important so it does not have to be a zero de-
lay plltype buffer. The trace lengths from the clock
44/51
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BOARD LAYOUT
Figure 6-11. Clock routing
L
Lowskewclock driver:
DIMMCKn input
DIMMCKn input
DIMMCKn input
STPC MCLKI
MCLKO
L+75mm*
20pF
* Noadditionnal 75mm when SDRAM directly soldered on board
When using DIMM modules, schematics have to
be done carefully in order to avoid data busses
completely crossed on the board. This has to be
checked at the library level. In order to achive lay-
out shown in Figure 6-12, schematics have to im-
plement the crossing described on Figure 6-13.
The DQM signals must be exchanged using the
same order.
Figure 6-12. Optimum data bus layout for DIMM
STPC
SDRAM I/F
MD[31:00]
MD[63:32]
D[15:00]
D[47:32]
D[31:16]
D[63:48]
DIMM
Figure 6-13. Schematics for optimum data bus layout for DIMM
STPC
MD[15:00],DQM[1:0]
DIMM
D[15:00],DQM[1:0]
D[31:16],DQM[3:2]
D[47:32],DQM[5:4]
D[63:48],DQM[7:6]
MD[31:16],DQM[3:2]
MD[47:32],DQM[5:4]
MD[63:48],DQM[7:6]
45/51
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BOARD LAYOUT
6.3.4 Address & Control Signals
This group encompasses the memory address
MA[12:0], bank address BA[0,1], RAS, CAS and
write enable WE signals. The load of the DIMM
module on these signals is the most important
oneand depends upon the type of SDRAM com-
ponents used (x4, x8 or x16) and whether the
DIMM module is single or dual row. The capacitive
loading of the SDRAM inputs alone for an x8 sin-
gle row DIMM will be about 30-40pF. An equiva-
lent circuit for the timing simulation is shown in
Figure 6-14 Most of the delays are due to the PCB
traces and loading rather than the pad itself.
Figure 6-14. Address/control equivalent circuit
100mm
(0.7ns)
Rterm
10mm
ZØ
pcb
6.3.5 Chip Select Signals (CS#[3:0])
There are 4 chip select pins per DIMM. Chip se-
lects 0 and 2 are always used to select the first
row of SDRAMs and chip selects 1 and 3 select
the second row on dual bank SDRAMs. The chip
select outputs only have to drive one DIMM each
Figure 6-15. CS# equivalent circuit
130mm
(0.9ns)
CS[0]
CS[2]
6.3.6 Data Write (MD[63:0])
The load on the data signals is much lower than
the address/control signals for an unbuffered
DIMM. For a registered DIMM the data signals are
the only memory pins of the DIMM which are not
registered. For the design to get maximum benefit
from using registered DIMMs the timings should
be compared to the timings for registered DIMMs
for the other pins..
Figure 6-16. Data write equivalent circuit
125mm
(0.9ns)
10mm
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BOARD LAYOUT
6.3.7 Data Read (MD[63:0])
The data read simulation circuit is shown below..
Figure 6-17. Data read equivalent circuit
DIMM1
125mm
(0.9ns)
10W
SDRAM
DQ
10mm
6.3.8 Data Mask (DQM[7:0])
The data mask load is quite similar to that of the
data signals.
6.3.9 Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing unless the mem-
ory controller can be designed to set up these sig-
nals one cycle in advance. The simulations show
that for these signals the best way to drive them is
to use a parallel termination. For applications
where speed is not so critical series termination
can be used as this will save power. Using a low
impedance such as 50W for these critical traces is
recommended as it both reduces the delay and
the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals for
unbuffered DIMMs. When using registered DIMMs
the other signals will probably be just as critical as
the address/control signals so to gain maximum
benefit from using registered DIMMs the timings
should also be considered in that situation. Using
lower impedance traces is also beneficial for the
other signals but if their timing is not as critical as
the address/control signals they could use the de-
fault value. Using a lower impedance implies us-
ing wider traces which may have an impact on the
routing of the board.
47/51
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ORDERING DATA
7 ORDERING DATA
7.1 Ordering Codes
ST
PC
C03
66
BT
C
3
STMicroelectronics
Prefix
Product Family
PC: PC Compatible
Product ID
C03: Consumer-S
Core Speed
66: 66MHz
75: 75MHz
Package
BT: 388 Overmoulded BGA
Temperature Range
C: Commercial
Case Temperature (Tcase) = 0°C to +100°C
I: Industrial
Case Temperature (Tcase) = -40°C to +100°C
Operating Voltage
3 : 3.3V ± 0.3V
48/51
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ORDERING DATA
7.2 Available Part Numbers
Core Frequency
CPU Mode
( DX / DX2 )
Tcase Range
Operating Voltage
( V )
Part Number
( MHz )
( °C )
STPCC0366BTC3
STPCC0375BTC3
STPCC0390BTC3
STPCC0310BTC3
STPCC0366BTC3
66
DX
DX
DX
DX
DX
75
0°C to +100°
90
3.3V ± 0.3V
100
66
-40°C to +100°
49/51
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ORDERING DATA
50/51
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
1999 STMicroelectronics - All Rights Reserved
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
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