STPCC4 [ETC]
STPC CONSUMER-II DATASHEET / X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP ; STPC CONSUMER -II产品资料/ X86核心的PC兼容的信息家电系统级芯片\n型号: | STPCC4 |
厂家: | ETC |
描述: | STPC CONSUMER-II DATASHEET / X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
|
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®
STPC CONSUMER-II
X86 Core PC Compatible Information Appliance System-on-Chip
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POWERFUL x86 PROCESSOR
64-BIT SDRAM UMA CONTROLLER
VGA & SVGA CRT CONTROLLER
135 MHz RAMDAC
2D GRAPHICS ENGINE
VIDEO INPUT PORT
VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOUR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
PBGA388
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TV OUTPUT
- THREE-LINE FLICKER FILTER
- ITU-R 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO
Figure 0-1. Logic Diagram
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PCI MASTER / SLAVE / ARBITER
ISA MASTER / SLAVE
Host x86
I/F
Core
OPTIONAL 16-BIT LOCAL BUS INTERFACE
EIDE CONTROLLER
PCI Bus
PCI
m/s
PMU
I²C INTERFACE
IPC
IDE
I/F
ISA
m/s
PCI
m/s
IPC
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
ISA Bus
LB
CTR
Local Bus
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POWER MANAGEMENT UNIT
JTAG IEEE1149.1
Video
Pipeline
DESCRIPTION
C Key
K Key
LUT
Monitor
The STPC Consumer-II integrates a standard 5th
generation x86 core, a Synchronous DRAM
controller, a graphics subsystem, a video pipeline,
and support logic including PCI, ISA, and IDE
SVGA
CRTC
TVO
Cursor
GE
TV
Encoder
controllers to provide
a
single consumer
orientated PC compatible subsystem on a single
device.
VIP
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing memory
between the CPU, the graphics and the video.
SDRAM
CTRL
JTAG
The STPC Consumer-II is packaged in a 388
Plastic Ball Grid Array (PBGA).
Release 1.5 - January 29, 2002
1/93
®
STPC CONSUMER-II
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X86 Processor core
Fully static 32-bit five-stage pipeline, x86
processor fully PC compatible.
CRT Controller
Integrated 135 MHz triple RAMDAC allowing
for 1280 x 1024 x 75 Hz display.
Requires external frequency synthesizer and
reference sources.
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Can access up to 4 GB of external memory.
8 Kbyte unified instruction and data cache
with write back and write through capability.
Parallel processing integral floating point unit,
with automatic power down.
Runs up to 100 MHz (x1) or 133 MHz (x2).
Fully static design for dynamic clock control.
Low power and system management modes.
Optimized design for 2.5 V operation.
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8-bit, 16-bit, 24-bit pixels.
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Interlaced or non-interlaced output.
Requires no external frequency synthesizer.
Requires only external reference source.
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Video Input port
Accepts video inputs in ITU-R 601 mode.
Optional 2:1 decimator
Stores captured video in off setting area of
the onboard frame buffer.
Video pass through to the TV output for full
screen video images.
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SDRAM Controller
64-bit data bus.
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Up to 100 MHz SDRAM clock speed.
Integrated system memory, graphic frame
memory and video frame memory.
Supports 2 MB up to 128 MB system
memory.
Supports 16-, 64-, and 128-Mbit SDRAMs.
Supports 8, 16, 32, 64, and 128 MB DIMMs.
Supports buffered, non buffered, and
registered DIMMs
Four-line write buffers for CPU to SDRAM
and PCI to SDRAM cycles.
Four-line read prefetch buffers for PCI
masters.
HSYNC and B/T generation or lock onto
external video timing source.
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Video Pipeline
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Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Colour space conversion (RGB to YUV and
YUV to RGB).
Programmable window size.
Chroma and colour keying for integrated
video overlay.
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Programmable latency
Programmable timing for SDRAM
parameters.
Supports -8, -10, -12, -13, -15 memory parts
Supports memory hole between 1 MB and
8 MB for PCI/ISA busses.
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Video Output
NTSC-M; PAL-B, D, G, H, I, M, N encoding.
ITU-R 601 encoding with programmable
colour subcarrier frequencies.
ITU-R 656 video output signal interface.
Four analog outputs in two configurations:
- R,G,B + CVBS
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2D Graphics Controller
64-bit windows accelerator.
- C,YS,CVBS1 + CVBS2
Flicker-free interlaced output.
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Backward compatibility to SVGA standards.
Hardware acceleration for text, bitblts,
transparent blts and fills.
Up to 64 x 64 bit graphics hardware cursor.
Up to 4MB long linear frame buffer.
8-, 16-, 24- and 32-bit pixels.
Programmable two tap filter with gamma
correction or three tap flicker filter.
Interlaced or non-interlaced operation mode.
Progressive to interlaced scan converter.
Cross colour reduction by specific trap
filtering on luma within CVBS flow.
Power down mode available on each DAC.
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Drivers availables for various OSes.
2/93
Release 1.5 - January 29, 2002
®
STPC CONSUMER-II
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PCI Controller
IDE Interface
Supports PIO
Fully compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3
masters can connect directly. External PAL
allows for greater than 3 masters.
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
PCI.
Transfer Rates to 22 MBytes/sec
Supports up to 4 IDE devices
Concurrent channel operation (PIO modes) -
4 x 32-Bit Buffer FIFOs per channel
Support for PIO mode 3 & 4.
Individual drive timing for all four IDE devices
Supports both legacy & native IDE modes
Supports hard drives larger than 528MB
Support for CD-ROM and tape peripherals
Backward compatibility with IDE (ATA-1).
Drivers for Windows and other Operating
Systems
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Support for burst read/write from PCI master.
PCI clock is 1/2, 1/3 or 1/4 cpu bus clock.
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ISA master/slave
Generates the ISA clock from either
14.318 MHz oscillator clock or PCI clock
Supports programmable extra wait state for
ISA cycles
Supports I/O recovery time for back to back
I/O cycles.
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
Supports flash ROM.
Supports ISA hidden refresh.
Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host
bus.
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Inte
grated Peripheral Controller
2X8237/AT compatible 7-channel DMA
controller.
2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
Three 8254 compatible Timer/Counters.
Co-processor error support logic.
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Power Management
Four power saving modes: On, Doze,
Standby, Suspend.
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Programmable system activity detector
Supports Intel & Cyrix SMM and APM.
Supports STOPCLK.
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Local Bus interface
Multiplexed with ISA/DMA interface.
Low latency asynchronous bus
Supports IO trap & restart.
22-bit address bus.
Independent peripheral time-out timer to
monitor hard disk, serial & parallel port.
128K SM_RAM address space from
0xA0000 to 0xB0000
16-bit data bus with word steering capability.
Programmable timing (Host clock granularity)
Two Programmable Flash Chip Select.
Four Programmable I/O Chip Select.
Supports 32-bit Flash burst.
Two-level hardware key protection for Flash
boot block protection.
Supports two banks of 16 MB flash devices
with boot block shadowed to 0x000F0000.
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JTAG
Boundary Scan compatible IEEE1149.1.
Scan Chain control.
Bypass register compatible IEEE1149.1.
ID register compatible IEEE1149.1.
RAM BIST control.
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The STPC Consumer-II has undergone an errata fix upgrade. The different versions can be differenciated by the part
number. Both versions are pin to pin compatible and there are some software extensions that have been added to the
upgraded parts. The parts labeled STPCC5 are the upgraded parts and the differences are identified in both the Datash-
eet and Programming Manual. All parts labeled STPCC4 do not support the new features outlined in the documentation.
Where nor C4 nor C5 are specified, the information or feature applies to both versions.
Release 1.5 - January 29, 2002
3/93
®
STPC CONSUMER-II
4/93
Release 1.5 - January 29, 2002
GENERAL DESCRIPTION
1. GENERAL DESCRIPTION
At the heart of the STPC Consumer-II is an
advanced 64-bit x86 processor block. It includes a
Configuration is done by ‘strap options’. It is a set
of pull-up or pull-down resistors on the memory
data bus, checked on reset, which auto-configure
the STPC Consumer-II.
64-bit SDRAM controller, advanced
64-bit
accelerated graphics and video controller, a high
speed PCI local-bus controller and Industry
standard PC chip set functions (Interrupt
controller, DMA Controller, Interval timer and ISA
bus).
1.2. GRAPHICS FEATURES
Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
The STPC Consumer-II has in addition, an EIDE
2
Controller, I C Interface, a Local Bus interface and
a JTAG interface.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include
hardware acceleration of text, bitblts, transparent
blts and fills. The results of these operations
change the contents of the on-screen or off-
screen frame buffer areas of SDRAM memory.
The frame buffer can occupy a space up to 4
Mbytes anywhere in the physical main memory.
1.1. ARCHITECTURE
The STPC Consumer-II makes use of a tightly
coupled Unified Memory Architecture (UMA),
where the same memory array is used for CPU
main memory and graphics frame-buffer. This
means a reduction in total system memory for
system performances that are equal to that of a
comparable frame buffer and system memory
based system, and generally much better, due to
the higher memory bandwidth allowed by
attaching the graphics engine directly to the 64-bit
processor host interface running at the speed of
the processor bus rather than the traditional PCI
bus. The 64-bit wide memory array provides the
system with 528MB/s peak bandwidth. This allows
for higher resolution screens and greater color
depth.
The graphics resolution supported is a maximum
of 1280x1024 in 16M colors and 16M colors at
75Hz refresh rate, VGA and SVGA compatible.
Horizontal timing fields are VGA compatible while
the vertical fields are extended by one bit to
accommodate above display resolution.
1.3. VIDEO FUNCTIONS
The STPC Consumer-II provides several
additional functions to handle MPEG or similar
video streams. The Video Input Port accepts an
encoded digital video stream in one of a number of
industry standard formats, decodes it, optionally
decimates it, and deposits it into an off screen
area of the frame buffer. An interrupt request can
be generated when an entire field or frame has
been captured. The video output pipeline
incorporates a video-scaler and color space
converter function and provisions in the CRT
controller to display a video window. While
repainting the screen the CRT controller fetches
both the video as well as the normal non-video
frame buffer in two separate internal FIFOs. The
video stream can be color-space converted
(optionally) and smooth scaled. Smooth
interpolative scaling in both horizontal and vertical
direction are implemented. Color and Chroma key
functions are also implemented to allow mixing
video stream with non-video frame buffer.
The ‘standard’ PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated together with the x86
processor core; additional functions such as
communications ports are accessed by the STPC
Consumer-II via internal ISA bus.
The PCI bus is the main data communication link
to the STPC Consumer-II chip. The STPC
Consumer-II translates appropriate host bus I/O
and Memory cycles onto the PCI bus. It also
supports generation of Configuration cycles on the
PCI bus. The STPC Consumer-II, as a PCI bus
agent (host bridge class), fully complies with PCI
specification 2.1. The chip-set also implements
the PCI mandatory header registers in Type 0 PCI
configuration space for easy porting of PCI aware
system BIOS. The device contains a PCI
arbitration function for three external PCI devices.
The STPC Consumer-II has two functional blocks
sharing the same balls : The ISA / IPC / IDE block
and the Local Bus / IDE block (see Table 3). Any
board with the STPC Consumer-II should be built
using only one of these two configurations. The
IDE pins are dynamically multiplexed in each of
the blocks in ISA mode only.
The video output passes directly to the RAMDAC
for monitor output or through another optional
color space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
Release 1.5 - January 29, 2002
5/93
GENERAL DESCRIPTION
or a 3 line flicker filter (primarily designed for
Windows type displays). The fliker filter is optional
and can be software disabled for use with large
screen area’s of video.
Table 1-1. Memory configurations
Memory
Organisa
tion
Device
Number
Bank size
Size
4Mx64
4
8
2Mx16x2
4Mx8x2
8Mx4x2
1Mx16x4
2Mx8x4
4Mx4x4
2Mx16x2
4Mx8x4
The Video output pipeline of the STPC Consumer-
II interfaces directly to the internal digital TV
encoder. It takes a 24 bit RGB non-interlaced pixel
stream and converts to a multiplexed 4:2:2 YCrCb
8Mx64
16Mx64
4Mx64
16
4
64Mbits
8 bit output stream, the logic includes
a
progressive to interlaced scan converter and logic
to insert appropriate CCIR656 timing reference
codes into the output stream. It facilitates the high
quality display of VGA or full screen video streams
received via the Video input port to standard
NTSC or PAL televisions.
8Mx64
8
32Mx64
16Mx64
32Mx64
16
8
128Mbits
16
The digital PAL/NTSC encoder outputs interlaced
or non-interlaced video in PAL-B,D,G,H,I PAL-N,
PAL-M or NTSC-M standards and “NTSC- 4.43” is
also possible.
The SDRAM Controller supports buffered or
unbuffered SDRAM but not EDO or FPM modes.
SDRAMs must support Full Page Mode Type
access.
The four frame (for PAL) or 2 frame (for NTSC)
burst sequences are internally generated,
The STPC Memory Controller provides various
programmable SDRAM parameters to allow the
SDRAM interface to be optimized for different
processor bus speeds SDRAM speed grades and
CAS Latency.
subcarrier
generation
being
performed
numerically with CKREF as reference. Rise and
fall times of synchronisation tips and burst
envelope are internally controlled according to the
relevant ITU-R and SMPTE recommendations.
1.5. IDE INTERFACE
Video output signals are directed to four analog
output pins through internal D/A converters giving,
simultaneous R,G,B and composite CVBS
outputs.
An industry standard EIDE (ATA 2) controller is
built into the STPC Consumer-II. The IDE port is
capable of supporting a total of four devices.
1.4. MEMORY CONTROLLER
1.6. POWER MANAGEMENT
The STPC Consumer-II core is compliant with the
The STPC handles the memory data (DATA) bus
directly, controlling from 2 to 128 MBytes. The
SDRAM controller supports accesses to the
Memory Banks to/from the CPU (via the host),
from the VMI, to/from the CRTC, to the VIDEO &
to/from the GE. (Banks 0 to 3) which can be
populated with either single or double sided 72-bit
(4 bit parity) DIMMs. Parity is not supported.
Advanced
Power
Management
(APM)
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management
Unit module (PMU) controls the power
consumption providing a comprehensive set of
features that control the power usage and
supports compliance with the United States
Environmental Protection Agency's Energy Star
Computer Program. The PMU provides following
hardware structures to assist the software in
managing the power consumption by the system.
The SDRAM controller only supports 64 bit wide
Memory Banks.
Four Memory Banks (if DIMMS are used; Single
sided or two double-sided DIMMs) are supported
in the following configurations (see Table 1-1)
- System Activity Detection.
- Three power down timers.
- Doze timer for detecting lack of system activity
for short durations.
Table 1-1. Memory configurations
- Stand-by timer for detecting lack of system
activity for medium durations
Memory
Bank size
Organisa
tion
Device
Size
Number
- Suspend timer for detecting lack of system
activity for long durations.
1Mx64
2Mx64
4Mx64
4
8
1Mx16
2Mx8
4Mx4
- House-keeping activity detection.
- House-keeping timer to cope with short bursts
of house-keeping activity while dozing or in stand-
by state.
16Mbits
16
6/93
Release 1.5 - January 29, 2002
GENERAL DESCRIPTION
- Peripheral activity detection.
- Peripheral timer for detecting lack of peripheral
activity
- SUSP# modulation to adjust the system
performance in various power down states of the
system including full power on state.
- Power control outputs to disable power from
different planes of the board.
execution of the current instruction, any pending
decoded instructions and associated bus cycles.
During the suspend mode, internal clocks are
stopped. Removing power down, the processor
resumes instruction fetching and begins execution
in the instruction stream at the point it had
stopped. Because of the static nature of the core,
no internal data is lost.
Lack of system activity for progressively longer
period of times is detected by the three power
down timers. These timers can generate SMI
interrupts to CPU so that the SMM software can
put the system in decreasing states of power
consumption. Alternatively, system activity in a
power down state can generate SMI interrupt to
allow the software to bring the system back up to
full power on state. The chip-set supports up to
three power down states: Doze state, Stand-by
state and Suspend mode. These correspond to
decreasing levels of power savings.
1.7. JTAG
JTAG stands for Joint Test Action Group and is the
popular name for IEEE Std. 1149.1, Standard Test
Access Port and Boundary-Scan Architec-ture.
This built-in circuitry is used to assist in the test,
maintenance and support of functional circuit
blocks. The circuitry includes a standard interface
through which instructions and test data are
communicated. A set of test features is defined,
including a boundary-scan register so that a
component is able to respond to a minimum set of
test instructions.
Power down puts the STPC Consumer-II into
suspend mode. The processor completes
Release 1.5 - January 29, 2002
7/93
GENERAL DESCRIPTION
Figure 1-1. Functional description.
Host
I/F
x86
Core
PCI BUS
PCI m/s
PMU
IDE
ISA
m/s
IPC
82C206
PCI m/s
I/F
ISA Bus
Local
Bus I/F
Local Bus
Video Pipeline
- Pixel formating
- Scaler
- Colour Space CVT
Colour Key
Chroma Key
LUT
Monitor
SVGA
CRTC
TVO
- CSC
- FF
- CCIR
HW Cursor
GE
NTSC/PAL
Encoder
TV
CCIR Input
VIP
JTAG
SDRAM
I/F
8/93
Release 1.5 - January 29, 2002
GENERAL DESCRIPTION
The speed of the PLLs is either fixed (DEVCLK),
either programmable by strap option (HCLK)
either programmable by software (DCLK, MCLK).
When in synchronized mode, MCLK speed is fixed
to HCLKO speed and HCLKI is generated from
MCLKI.
1.8. CLOCK TREE
The STPC Atlas integrates many features and
generates all its clocks from a single 14MHz
oscillator. This results in multiple clock domains as
described in Figure 1-2.
Figure 1-2. STPC Consumer-II clock architecture
MCLKO
MCLKI
VCLK
DCLK
SDRAM controller
GE
VIP
CRTC,Video,TV
HCLKO
DEVCLK
PLL
DCLK
PLL
MCLK
PLL
HCLK
PLL
HCLKI
x1
x2
CPU
ISA
IPC
North Bridge
Host
Local Bus
South Bridge
1/2
1/3
1/2
1/4
DEVCLK
(24MHz)
OSC14M ISACLK
(14MHz)
HCLK
PCICLKO
XTALO
XTALI
PCICLKI
14.31818 MHz
Release 1.5 - January 29, 2002
9/93
GENERAL DESCRIPTION
Figure 1-3. Typical ISA-based Application.
Keyboard / Mouse
Serial Ports
Parallel Port
Floppy
Super I/O
RTC
Flash
DMUX
2x EIDE
ISA
MUX
IRQ
Monitor
SVGA
MUX
DMA.REQ
TV
S-VHS
RGB
PAL
STPC Consumer-II
DMA.ACK
NTSC
DMUX
Video
CCIR601
CCIR656
PCI
4x 16-bit SDRAMs
10/93
Release 1.5 - January 29, 2002
PIN DESCRIPTION
2. PIN DESCRIPTION
2.1. INTRODUCTION
Table 2-1. Signal Description
Group name
Basic Clocks reset & Xtal (SYS)
SDRAM Controller
PCI interface
Qty
The STPC Consumer-II integrates most of the
functionality of the PC architecture. As a result,
many of the traditional interconnections between
the host PC microprocessor and the peripheral
devices are totally internal to the STPC
Consumer-II. This offers improved performance
due to the tight coupling of the processor core and
these peripherals. As a result, many of the
external pin connections are made directly to the
on-chip peripheral functions.
7
95
56
ISA
79
34
49
IDE
89
Local Bus
Video Input
9
12
8
TV Output
VGA Monitor interface
Grounds
Figure 2-1 shows the STPC Consumer-II external
interfaces. It defines the main buses and their
functions. Table 2-1 describes the physical
71
26
9
V
DD
implementation,
listing
signal
type
and
Miscellaneous
Unconnected
Total Pin Count
functionality. Table 2-2 provides a full pin listing
and description of pins. Table 2-7 provides a full
listing of pin locations of the STPC Consumer-II
package by physical connection.
6
388
Note: Several interface pins are multiplexed with
other functions, refer to Table 2-4 and Table 2-5
for further details
Figure 2-1. STPC Consumer-II External Interfaces
STPC CONSUMER-II
x86
PCI
VIP
TV
12
SYS
SDRAM VGA
ISA/IDE/LB
7
95
8
9
56
89
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11/93
PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
2
Signal Name
BASIC CLOCKS AND RESETS
SYSRSETI#
Dir
Buffer Type
Description
Qty
I
SCHMITT_FT
System Power Good Input
System Reset Output
1
1
SYSRSTO#
O
BD8STRP_FT
ANA
14.3 MHz Crystal Input- External
Oscillator Input
XTALI
I
1
XTALO
HCLK
I/O
I/O
O
OSCI13B
14.3 MHz Crystal Output
1
1
1
1
BD4STRP_FT
BT8TRP_TC
BD4STRP_FT
VDDCO
Host Clock (Test)
DEV_CLK
24 MHz Peripheral Clock (floppy drive)
27-135 MHz Graphics Dot Clock
Power Supply for PLL Clocks
DCLK
I/O
1
V
_xxx_PLL
DD
SDRAM CONTROLLER
MCLKI
I
TLCHT_TC
Memory Clock Input
Memory Clock Output
DIMM Chip Select
1
1
2
1
MCLKO
O
O
O
BT8TRP_TC
BD8STRP_TC
CS#[1:0]
CS2# / MA11
BD16STARUQP_TC DIMM Chip Select / Memory Address
DIMM Chip Select / Memory Address /
CS3# / MA12 / BA1
O
BD16STARUQP_TC
Bank Address
1
BA[0]
O
O
BD8STRP_TC
Bank Address
1
12
15
48
1
MA[10:0]
MD[63:49]
MD[48:1]
MD[0]
BD16STARUQP_TC Memory Row & Column Address
I/O
I/O
I/O
O
BD8STRUP_FT
BD8TRP_TC
Memory Data
Memory Data
Memory Data
BD8STRUP_FT
RAS#[1:0]
CAS#[1:0]
MWE#
BD16STARUQP_TC Row Address Strobe
BD16STARUQP_TC Column Address Strobe
BD16STARUQP_TC Write Enable
2
O
2
O
1
DQM[7:0]
O
BD8STRP_TC
Data Input/Output Mask
8
PCI CONTROLLER
PCI_CLKI
PCI_CLKO
AD[31:0]
I
TLCHT_FT
33 MHz PCI Input Clock
33 MHz PCI O/P Clk (from internal PLL)
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
1
1
32
4
1
1
1
1
1
1
1
1
3
3
4
O
BT8TRP_TC
I/O
I/O
I/O
I/O
I/O
I
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
TLCHT_FT
CBE[3:0]
FRAME#
IRDY#
Initiator Ready
TRDY#
Target Ready
LOCK#
PCI Lock
DEVSEL#
STOP#
I/O
I/O
I/O
O
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD4STRUP_FT
Device Select
Stop Transaction
Parity Signal Transactions
System Error
PAR
SERR#
PCIREQ#[2:0]
PCIGNT#[2:0]
PCI_INT#[3:0]
I
PCI Request
O
PCI Grant
I
PCI Interrupt Request
1
Note : These pins are must be connected to the 2.5 V power supply. They must not be connected to the 3.3 V supply.
2
Note : See
for buffer type descriptions
Table 2-3
12/93
Release 1.5 - January 29, 2002
PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
2
Signal Name
ISA INTERFACE
Dir
Buffer Type
Description
Qty
ISA Clock Output
Multiplexer Select Line For IPC
ISA_CLK
O
O
BT8TRP_TC
1
1
ISA Clock x2 Output
Multiplexer Select Line For IPC
ISA_CLK2X
BT8TRP_TC
OSC14M
O
O
BD8STRP_FT
BD8STRUP_FT
BD8STRUP_FT
BD8STRP_FT
BD4STRP_FT
BD8STRUP_FT
BD8STRP_FT
BD8STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD8STRP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
ISA bus synchronisation clock
Unlatched Address
1
7
20
16
1
2
2
2
2
1
1
1
1
1
1
1
1
1
4
2
3
1
1
1
1
1
1
LA[23:17]
SA[19:0]
I/O
I/O
O
Latched Address
SD[15:0]
Data Bus
ALE
Address Latch Enable
Memory Read and Write
System MemoryRead and Write
I/O Read and Write
MEMR#, MEMW#
SMEMR#, SMEMW#
IOR#, IOW#
MCS16#, IOCS16#
BHE#
I/O
O
I/O
I
Memory and I/O ChipSelect16
System Bus High Enable
Zero Wait State
O
ZWS#
I
REF#
O
Refresh Cycle.
MASTER#
AEN
I
Add On Card Owns Bus
Address Enable
O
IOCHCK#
IOCHRDY
ISAOE#
I
I/O Channel Check.
I/O
O
I/O Channel Read
ISA/IDE Selection
GPIOCS#
IRQ_MUX[3:0]
DREQ_MUX[1:0]
DACK_ENC[2:0]
TC
I/O
I
General Purpose Chip Select
Time-Multiplexed Interrupt Request
Time-Multiplexed DMA Request
Encoded DMA Acknowledge
ISA Terminal Count
I
O
O
RTCAS
O
Real Time Clock Address Strobe
ROM/RTC Chip Select
Keyboard Chip Select
RTC Read/Write
RMRTCCS#
KBCS#
I/O
I/O
I/O
I/O
RTCRW#
RTCDS#
RTC Data Strobe
LOCAL BUS INTERFACE
PA[23:0]
O
I/O
O
O
I
BD4STRP_FT
BD8STRP_FT
BD4STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD8STRUP_FT
Address Bus
24
16
2
PD[15:0]
Data Bus
PRD1#,PRD0#
PWR1#,PWR0#
PRDY
Peripheral Read Control
Peripheral Write Control
Data Ready
2
1
FCS1#, FCS0#
IOCS#[3:0]
O
O
Flash Chip Select
I/O Chip Select
2
4
IDE CONTROLLER
DA[2:0]
O
BD8STRUP_FT
BD8STRUP_FT
Address Bus
Data Bus
3
DD[15:0]
I/O
16
1
Note : These pins are must be connected to the 2.5 V power supply. They must not be connected to the 3.3 V supply.
2
Note : See
for buffer type descriptions
Table 2-3
Release 1.5 - January 29, 2002
13/93
PIN DESCRIPTION
Table 2-2. Definition of Signal Pins
2
Signal Name
PCS3#,PCS1#,SCS3#,SCS1#
DIORDY
Dir
O
O
I
Buffer Type
BD8STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD4STRP_FT
BD8STRP_FT
BD8STRUP_FT
BD8STRUP_FT
Description
Qty
4
Primary & Secondary Chip Selects
Data I/O Ready
1
PIRQ, SIRQ
Primary & Secondary Interrupt Request
Primary & Secondary DMA Request
Primary & Secondary DMA Acknowledge
Primary & Secondary I/O Channel Read
Primary & Secondary I/O Channel Write
2
PDRQ, SDRQ
I
2
PDACK#, SDACK#
PDIOR#, SDIOR#
PDIOW#, SDIOW#
O
O
O
2
2
2
VGA CONTROLLER
RED, GREEN, BLUE
VSYNC
O
O
O
I
VDDCO
Analog Red, Green, Blue
Vertical Sync
3
1
1
1
1
1
1
BD4STRP_FT
BD4STRP_FT
ANA
HSYNC
Horizontal Sync
DAC Voltage reference
Resistor Set
1
VREF_DAC
RSET
I
ANA
COMP
I
ANA
Compensation
COL_SEL
O
BD4STRP_FT
Colour Select
VIDEO INPUT PORT
VCLK
I
I
BD8STRP_FT
BD4STRP_FT
27-33 MHz Video Input Port Clock
1
8
VIN[7:0]
CCIR 601 or 656 YUV Video Data Input
ANALOG TV OUTPUT PORT
RED_TV, GREEN_TV, BLUE_TV
CVBS
O
O
I
VDDCO
VDDCO
ANA
Analog RGB or S-VHS outputs
Analog video composite output
Reference current of CVBS DAC
Reference voltage of CVBS DAC
Reference current of RGB DAC
Reference voltage of RGB DAC
Analog Vss for DAC
3
1
1
1
1
1
1
1
IREF1_TV
VREF1_TV
I
ANA
IREF2_TV
I
ANA
VREF2_TV
I
ANA
VSSA_TV
I
VDDA_TV
I
Analog Vdd for DAC
VDDCO
Composite Synchro
Horizontal Line Synchro
VCS
I/O
I/O
BD4STRP_FT
BD4STRP_FT
1
1
ODD_EVEN
Frame Synchronisation
Speaker Device Output
MISCELLANEOUS
SPKRD
O
BD4STRP_FT
1
1
I²C Interface - Clock
Can be used for VGA DDC[1] signal
SCL
SDA
I/O
BD4STRUP_FT
I²C Interface - Data
Can be used for VGA DDC[0] signal
I/O
BD4STRUP_FT
1
SCAN_ENABLE
I
I
TLCHTD_TC
TLCHT_FT
TLCHT_FT
TLCHT_FT
BT8TRP_TC
Reserved (Test pin)
Test Clock
1
1
1
1
1
TCLK
TDI
I
Test Data Input
Test Mode Set
Test Data output
TMS
I
TDO
O
1
Note : These pins are must be connected to the 2.5 V power supply. They must not be connected to the 3.3 V supply.
2
Note : See
for buffer type descriptions
Table 2-3
14/93
Release 1.5 - January 29, 2002
PIN DESCRIPTION
Table 2-3. Buffer Type Descriptions
Buffer
ANA
Description
Analog pad buffer
OSCI13B
Oscillator, 13 MHz, HCMOS
BT8TRP_TC
Tri-State output buffer, 8 mA drive capability, Schmitt trigger with slew rate control and P, TC
BD4STRP_FT
BD4STRUP_FT
BD8STRP_FT
BD8STRUP_FT
BD8STRP_TC
BD8TRP_TC
LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, 5V tolerant
LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, 5V tolerant
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger
BD8PCIARP_FT
LVTTL Bi-Directional, 8 mA drive capability, PCI compatible, 5V tolerant
BD16STARUQP_TC LVTTL Bi-Directional, 16 mA drive capability, Schmitt trigger
SCHMITT_FT
TLCHT_FT
LVTTL Input, Schmitt trigger, 5V tolerant
LVTTL Input, 5V tolerant
LVTTL Input
TLCHT_TC
TLCHTD_TC
LVTTL Input, Pull-Down
Internal supply for core only power pad
VDDCO
Release 1.5 - January 29, 2002
15/93
PIN DESCRIPTION
2.2. SIGNAL DESCRIPTIONS
2.2.2. SDRAM CONTROLLER
MCLKO Memory Clock Output. This clock is
driving the DIMMs on board and is generated from
an internal PLL. The default value is 66 MHz.
2.2.1. BASIC CLOCKS AND RESETS
SYSRSTI# System Reset/Power good. This input
is low when the reset switch is depressed.
Otherwise, it reflects the power supply power
good signal. This input is asynchronous to all
clocks, and acts as a negative active reset. The
reset circuit initiates a hard reset on the rising
edge of this signal.
MCLKI Memory Clock Input. This clock is driving
the SDRAM controller, the graphics engine and
display controller. This input should be a buffered
version of the MCLKO signal with the track lengths
between the buffer and the pin matched with the
track lengths between the buffer and the DIMMs.
SYSRSTO# Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted
buffered version of this output and the PCI bus
reset is an externally buffered version of this
output.
CS#[1:0] Chip Select These signals are used to
disable or enable device operation by masking or
enabling all SDRAM inputs except MCLK, CKE,
and DQM.
CS#[2]/MA[11] Chip Select/Bank Address This
pin is CS#[2] in the case when 16-Mbit devices are
used. For all other densities, it becomes MA[11].
XTALI 14.3 MHz Crystal Input
XTALO 14.3 MHz Crystal Output. These pins are
provided for the connection of an external 14.318
MHz crystal to provide the reference clock for the
internal frequency synthesizer, from which all
other clock signals are generated.
CS#[3]/MA[12]/BA[1]
Chip
Select/Memory
Address/Bank Address
This pin is CS#[3] in the
case when 16-Mbit devices are used. For all other
densities, it becomes MA[12] when two internal
banks devices are used and BA[1] when four
internal bank devices are used.
The 14.318 MHz series-cut fundamental (not
overtone) mode quartz crystal must have an
Equivalent Series Resistance (ESR, sometimes
referred to as Rm) of less then 50 Ohms (typically
8 Ohms) and a shunt capacitance (Co) of less
than 7 pF. Balance capacitors of 16 pF should
also be added, one connected to each pin.
MA[10:0] Memory Address. Multiplexed row and
column address lines.
BA[0] Memory Bank Address.
MD[63:0] Memory Data. This is the 64-bit memory
data bus. MD[40-0] are read by the device strap
option registers during rising edge of SYSRSTI#.
In the event of an external oscillator providing the
master clock signal to the STPC Consumer-II
device, the LVTTL signal should be connected to
XTALI.
RAS#[1:0] Row Address Strobe. There are two
active-low row address strobe output signals. The
RAS# signals drive the memory devices directly
without any external buffering.
HCLK Host Clock. This clock supplies the CPU
and the host related blocks. This clock can be
doubled inside the CPU and is intended to operate
in the range of 25 MHz to 100 MHz. This clock is
generated internally from a PLL but can be driven
directly from the external system.
CAS#[1:0] Column Address Strobe. There are
two active-low column address strobe output
signals. The CAS# signals drive the memory
devices directly without any external buffering.
DEV_CLK 24 MHz Peripheral Clock. This 24 MHz
signal is provided as a convenience for the system
integration of a Floppy Disk driver function in an
external chip.
MWE# Write Enable. Write enable specifies
whether the memory access is a read (MWE# = H)
or a write (MWE# = L).
DCLK 135 MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can go from 8 MHz (using internal PLL) up to 135
MHz, and it is required to have a worst case duty
cycle of 60-40.
This signal is driven either by the internal pll (VGA)
or by an external 27 MHz oscillator (when the
composite video output is enabled). The direction
can be controlled by a strap option or an internal
register bit.
DQM#[7:0] Data Mask. Makes data output Hi-Z
after the clock and masks the SDRAM outputs.
Blocks SDRAM data input when DQM active.
2.2.3. PCI CONTROLLER
PCI_CLKI 33 MHz PCI Input Clock. This signal is
the PCI bus clock input and should be driven from
the PCI_CLKO pin.
16/93
Release 1.5 - January 29, 2002
PIN DESCRIPTION
33 MHz PCI Output Clock. This is the
guarantee even parity across AD[31:0],
CBE#[3:0], and PAR. This signal is driven by the
master during the address phase and data phase
of write transactions. It is driven by the target
during data phase of read transactions (its
assertion is identical to that of the AD bus delayed
by one PCI clock cycle).
PCI_CLKO
master PCI bus clock output.
AD[31:0]
PCI Address/Data. This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and the data phase of write transactions. It
is driven by the target during the data phase of
read transactions.
SERR# System Error. This is the system error
signal of the PCI bus. It may, if enabled, be
asserted for one PCI clock cycle if target aborts a
STPC Consumer-II initiated PCI transaction. Its
assertion by either the STPC Consumer-II or by
another PCI bus agent will trigger the assertion of
NMI to the host CPU. This is an open drain output.
CBE#[3:0]
Bus Commands/Byte Enables. These
are the multiplexed command and byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the byte enable information.
These pins are inputs when a PCI master other
than the STPC Consumer-II owns the bus and
outputs when the STPC Consumer-II owns the
bus.
PCIREQ#[2:0]
PCI Request. These are the three
external PCI master request pins. They indicates
to the PCI arbiter that external agents desire use
of the bus.
FRAME#
Cycle Frame. This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Consumer-II
owns the PCI bus.
PCIGNT#[2:0] PCI Grant. These pins indicate that
the PCI bus has been granted to the master
requesting it on its PCIREQ#.
IRDY# Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Consumer-II initiates a bus cycle on the
PCI bus. It is used as an input during the PCI
cycles targeted to the STPC Consumer-II to
determine when the current PCI master is ready to
complete the current transaction.
PCI_INT#[3:0] PCI Interrupt Request. These are
the PCI bus interrupt signals.
2.2.4. ISA INTERFACE
ISA_CLK, ISA_CLKX2
ISA Clock x1, x2. These
pins generate the Clock signal for the ISA bus and
a Doubled Clock signal. They are also used as the
multiplexer control lines for the Interrupt Controller
Interrupt input lines. ISA_CLK is generated from
either PCICLK/4 or OSC14M/ 2.
TRDY#
Target Ready. This is the target ready
signal of the PCI bus. It is driven as an output
when the STPC Consumer-II is the target of the
current bus transaction. It is used as an input
when STPC Consumer-II initiates a cycle on the
PCI bus.
OSC14M
ISA bus synchronisation clock Output.
This is the buffered 14.318 MHz clock for the ISA
bus.
LOCK#
PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
LA[23:17]
Unlatched Address. When the ISA bus
is active, these pins are ISA Bus unlatched
address for 16-bit devices. When ISA bus is
accessed by any cycle initiated from PCI bus,
these pins are in output mode. When an ISA bus
master owns the bus, these pins are in input
mode.
DEVSEL# I/O Device Select. This signal is used
as an input when the STPC Consumer-II initiates
a bus cycle on the PCI bus to determine if a PCI
slave device has decoded itself to be the target of
the current transaction. It is asserted as an output,
either when the STPC Consumer-II is the target of
the current PCI transaction, or when no other
device asserts DEVSEL# prior to the subtractive
decode phase of the current PCI transaction.
SA[19:0]
ISA Address Bus. System address bus
of ISA on 8-bit slot. These pins are used as an
input when an ISA bus master owns the bus and
are outputs at all other times.
STOP#
Stop Transaction. Stop is used to
SD[15:0]
I/O Data Bus. These pins are the
implement the disconnect, retry and abort protocol
of the PCI bus. It is used as an input for the bus
cycles initiated by the STPC Consumer-II and is
used as an output when a PCI master cycle is
targeted to the STPC Consumer-II.
external data bus to the ISA bus.
ALE
Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Consumer-II to indicate that LA23-
17, SA19-0, AEN and SBHE# signals are valid.
The ALE is driven high during refresh, DMA
PAR
Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to
Release 1.5 - January 29, 2002
17/93
PIN DESCRIPTION
master or an ISA master cycles by the STPC
Consumer-II. ALE is driven low after reset.
an ISA master owns the bus and is used to trigger
a refresh cycle.
The STPC Consumer-II performs a pseudo
hidden refresh. It requests the host bus for two
host clocks to drive the refresh address and
capture it in external buffers. The host bus is then
relinquished while the refresh cycle continues on
the ISA bus.
MEMR# Memory Read. This is the memory read
command signal of the ISA bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW# Memory Write. This is the memory write
command signal of the ISA bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
MASTER# Add On Card Owns Bus. This signal is
active when an ISA device has been granted bus
ownership.
AEN Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to
indicate that a DMA transfer will occur. The
enabling of the signal indicates to IO devices to
ignore the IOR#/IOW# signal during DMA
transfers.
SMEMR# System Memory Read. The STPC
Consumer-II generates SMEMR# signal of the
ISA bus only when the address is below one
megabyte or the cycle is a refresh cycle.
SMEMW# System Memory Write. The STPC
Consumer-II generates the SMEMW# signal of
the ISA bus only when the address is below one
megabyte.
IOCHCK#
IO Channel Check.
IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. The NMI
signal becomes active on seeing IOCHCK# active
if the corresponding bit in Port B is enabled.
IOR# I/O Read. This is the IO read command
signal of the ISA bus. It is an input when an ISA
master owns the bus and is an output at all other
times.
IOCHRDY
Channel Ready.
IOCHRDY is the IO
channel ready signal of the ISA bus and is driven
as an output in response to an ISA master cycle
targeted to the host bus or an internal register of
the STPC Consumer-II. The STPC Consumer-II
monitors this signal as an input when performing
an ISA cycle on behalf of the host CPU, DMA
master or refresh.
IOW# I/O Write. This is the IO write command
signal of the ISA bus. It is an input when an ISA
master owns the bus and is an output at all other
times.
MCS16# Memory Chip Select16. This is the
decode of LA23-17 address pins of the ISA
address bus without any qualification of the
command signal lines. MCS16# is always an
input. The STPC Consumer-II ignores this signal
during IO and refresh cycles.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Consumer-
II since the access to the system memory can be
considerably delayed due UMA architecture.
ISAOE#
Bidirectional OE Control.
This signal
controls the OE signal of the external transceiver
that connects the IDE DD bus and ISA SA bus.
IOCS16# IO Chip Select16. This signal is the
decode of SA15-0 address pins of the ISA
address bus without any qualification of the
command signals. The STPC Consumer-II does
not drive IOCS16# (similar to PC-AT design). An
ISA master access to an internal register of the
STPC Consumer-II is executed as an extended 8-
bit IO cycle.
GPIOCS#
I/O General Purpose Chip Select.
This
output signal is used by the external latch on ISA
bus to latch the data on the SD[7:0] bus. The latch
can be use by PMU unit to control the external
peripheral devices or any other desired function.
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They
have to be encoded before connection to the
STPC Consumer-II using ISACLK and ISACLKX2
as the input selection strobes.
Note that IRQ8B, which by convention is
connected to the RTC, is inverted before being
sent to the interrupt controller, so that it may be
connected directly to the IRQ pin of the RTC.
BHE# System Bus High Enable. This signal, when
asserted, indicates that a data byte is being
transferred on SD15-8 lines. It is used as an input
when an ISA master owns the bus and is an
output at all other times.
ZWS# Zero Wait State. This signal, when assert-
ed by an addressed device, indicates that the cur-
rent cycle can be shortened.
DREQ_MUX[1:0] ISA Bus Multiplexed DMA
REF# Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Consumer-II performs a refresh
cycle on the ISA bus. It is used as an input when
Request.
These are the ISA bus DMA request
signals. They are to be encoded before
connection to the STPC Consumer-II using
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Release 1.5 - January 29, 2002
PIN DESCRIPTION
ISACLK and ISACLKX2 as the input selection
strobes.
PRDY Data Ready input. This signal is used to
create wait states on the bus. When high, it
completes the current cycle.
DACK_ENC[2:0]
DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Consumer-II before output
and should be decoded externally using ISACLK
and ISACLKX2 as the control strobes.
FCS#[1:0] Flash Chip Select output. These are
the Programmable Chip Select signals for up to
two banks of Flash memory.
IOCS#[3:0]
I/O Chip Select output. These are the
TC
ISA Terminal Count. This is the terminal count
Programmable Chip Select signals for up to four
external I/O devices.
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the byte count expires.
2.2.6. IDE INTERFACE
RTCAS
Real time clock address strobe. This sig-
SCS1#, SCS3#
Secondary Chip Select. These
nal is asserted for any I/O write to port 70H.
signals are used as the active high secondary
master & slave IDE chip select signals. These
signals must be externally ANDed with the
ISAOE# signal before driving the IDE devices to
guarantee it is active only when ISA bus is idle.
RMRTCCS#
ROM/Real Time clock chip select.
This signal is asserted if a ROM access is
decoded during a memory cycle. It should be
combined with MEMR# or MEMW# signals to
properly access the ROM. During a IO cycle, this
signal is asserted if access to the Real Time Clock
(RTC) is decoded. It should be combined with IOR
or IOW# signals to properly access the real time
clock.
DA[2:0]
Address. These signals are connected to
DA[2:0] of IDE devices directly or through a buffer.
If the toggling of signals are to be masked during
ISA bus cycles, they can be externally ORed with
ISAOE# before being connected to the IDE
devices.
KBCS#
Keyboard Chip Select. This signal is
asserted if a keyboard access is decoded during a
I/O cycle.
DD[15:0]
Databus. When the IDE bus is active,
they serve as IDE signals DD[11:0]. IDE devices
are connected to SA[19:8] directly and ISA bus is
connected to these pins through two LS245
transceivers as described in Figure 6-10.
RTCRW#
Real Time Clock RW. This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCRW#. This signal is asserted for any
I/O write to port 71H.
PCS1#, PCS3#
Primary Chip Select. These
signals are used as the active high primary master
& slave IDE chip select signals. These signals
must be externally ANDed with the ISAOE# signal
before driving the IDE devices to guarantee it is
active only when ISA bus is idle.
RTCDS#
Real Time Clock DS. This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCDS#. This signal is asserted for any I/
O read to port 71H. Its polarity complies with the
DS pin of the MT48T86 RTC device when
configured with Intel timings.
DIORDY
Busy/Ready. This pin serves as IDE
signal DIORDY.
Note: RMRTCCS#, KBCS#, RTCRW# and
RTCDS# signals must be ORed externally with
ISAOE# and then connected to the external
device. An LS244 or equivalent function can be
used if OE# is connected to ISAOE# and the
output is provided with a weak pull-up resistor as
shown in Figure 6-10.
PIRQ
SIRQ
Primary Interrupt Request.
Secondary Interrupt Request.
Interrupt request from IDE channels.
PDRQ
SDRQ
Primary DMA Request.
Secondary DMA Request.
DMA request from IDE channels.
2.2.5. LOCAL BUS INTERFACE
PDACK#
SDACK#
Primary DMA Acknowledge.
PA[23:0]
PD[15:0]
Address Bus Output.
Secondary DMA Acknowledge.
DMA acknowledge to IDE channels.
Data Bus. This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
PDIOR#, PDIOW#
SDIOR#, SDIOW#
Primary I/O Read & Write.
Secondary I/O Read & Write.
PRD#[1:0]
Read Control output. PRD0# is used to
Primary & Secondary channel read & write.
read the LSB and PRD1# to read the MSB.
PWR#[1:0]
Write Control output. PWR0# is used
to write the LSB and PWR1# to write the MSB.
Release 1.5 - January 29, 2002
19/93
PIN DESCRIPTION
2.2.7. VGA CONTROLLER
recommended. In S-VHS mode, this is the
Luminance Output.
RED, GREEN, BLUE RGB Video Outputs. These
are the three analog colour outputs from the
RAMDACs. These signals are sensitive to
interference, therefore they need to be properly
shielded.
BLUE_TV
/
CVBS
Analog video outputs
This output is current-
synchronized with CVBS.
driven and must be connected to analog ground
over a load resistor (R ). Following the load
LOAD
resistor, a simple analog low pass filter is
recommended. In S-VHS mode, this is a second
composite output.
VSYNC Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
CVBS Analog video composite output (luminance/
chrominance). CVBS is current-driven and must
be connected to analog ground over a load
HSYNC Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
resistor (R
). Following the load resistor, a
LOAD
simple analog low pass filter is recommended.
VREF_DAC DAC Voltage reference. An external
voltage reference is connected to this pin to bias
the DAC.
IREF1_TV
IREF2_TV Reference current for RGB 10-bit DAC.
Ref. voltage
Ref. current
for CVBS 10-bit DAC.
RSET Resistor Current Set. This reference
current input to the RAMDAC is used to set the
full-scale output of the RAMDAC.
VREF1_TV
Connect to analog ground.
for CVBS 10-bit DAC.
COMP Compensation. This is the RAMDAC
compensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
VREF2_TV Reference voltage for RGB 10-bit
DAC. Connect to analog ground.
Analog V
V
to damp oscillations.
VSSA_TV
for DACs.
SS
DD
VDDA_TV Analog V for DACs.
2.2.8. VIDEO INPUT PORT
DD
JTAG Signals
VCLK Pixel Clock Input.This signal is used to
synchronise data being transferred from an
external video device to either the frame buffer, or
alternatively out the TV output in bypass mode.
This pin can be sourced from STPC if no external
VCLK is detected, or can be input from an external
video clock source.
VCS Line synchronisation Output. This pin is an
input in ODDEV+HSYNC or VSYNC + HSYNC or
VSYNC slave modes and an output in all other
modes (master/slave)
ODD_EVEN Frame Synchronisation Output. This
pin supports the Frame synchronisation signal. It
is an input in slave modes, except when sync is
extracted from YCrCbdata, and an output in
master mode and when sync is extracted from
YCrCb data
The signal is synchronous to rising edge of DCLK.
The default polarity for this pin is:
- odd (not-top) field: LOW level
- even (bottom) field: HIGH level
VIN[7:0] YUV Video Data Input CCIR 601 or 656.
Time
multiplexed
4:2:2
luminance
and
chrominance data as defined in ITU-R Rec601-2
and Rec656 (except for TTL input levels). This bus
typically carries a stream of Cb,Y,Cr,Y digital
video at VCLK frequency, clocked on the rising
edge (by default) of VCLK.
2.2.9. ANALOG TV OUTPUT PORT
2.2.10. MISCELLANEOUS
RED_TV
/
C_TV Analog video outputs
This output is current-
driven and must be connected to analog ground
over a load resistor (R ). Following the load
synchronized with CVBS.
SPKRD Speaker Drive. This the output to the
speaker. It is an AND of the counter 2 output with
bit 1 of Port 61, and drives an external speaker
driver. This output should be connected to 7407
type high voltage driver.
LOAD
resistor, a simple analog low pass filter is
recommended. In S-VHS mode, this is the
Chrominance Output.
SCL, SDA I²C Interface. These bidirectional pins
GREEN_TV
/
Y_TV Analog video outputs
This output is current-
driven and must be connected to analog ground
over a load resistor (R ). Following the load
are connected to CRTC register 3Fh to implement
synchronized with CVBS.
2
DDC capabilities. They conform to I C electrical
specifications, they have open-collector output
LOAD
drivers which are internally connected to V
through pull-up resistors.
resistor, a simple analog low pass filter is
DD
20/93
Release 1.5 - January 29, 2002
PIN DESCRIPTION
They can be used for the DDC1 (SCL) and DDC0
(SDA) lines of the VGA interface.
VDD_CORE 2.5 V Power Supply. These power
pins are necessary to supply the core with 2.5 V.
SCAN_ENABLE
Reserved. The pin is reserved
TCLK
Test clock
for Test and Miscellaneous functions.
TDI
Test data input
COL_SEL
Colour Select. Can be used for Picture
in Picture function. Note however that this signal,
brought out from the video pipeline, is not in sync
with the VGA output signals, i.e. the VGA signals
run four clock cycles after the Col_Sel signal.
Test mode input
Test data output
TMS
TDO
Release 1.5 - January 29, 2002
21/93
PIN DESCRIPTION
.
.
Table 2-4. ISA / IDE Dynamic Multiplexing
Table 2-5. ISA / Local Bus Pin Sharing
ISA BUS
(ISAOE# = 0)
IDE
(ISAOE# = 1)
ISA / IPC
SD[15:0]
LOCAL BUS
PD[15:0]
RMRTCCS#
DD[15]
DD[14]
DD[13]
DD[12]
DREQ_MUX[1:0]
SMEMR#
PA[21:20]
PA[19]
KBCS#
RTCRW#
RTCDS#
SA[19:8]
LA[23]
MEMW#
PA[18]
BHE#
PA[17]
DD[11:0]
SCS3#
SCS1#
PCS3#
PCS1#
DA[2:0]
DIORDY
AEN
PA[16]
ALE
PA[15]
LA[22]
MEMR#
PA[14]
SA[21]
IOR#
PA[13]
SA[20]
IOW#
PA[12]
LA[19:17]
IOCHRDY
REF#
PA[11]
IOCHCK#
GPIOCS#
ZWS#
PA[10]
PA[9]
PA[8]
SA[7:4]
PA[7:4]
PA[3:0]
PRDY
TC, DACK_ENC[2:0]
SA[3]
ISAOE#,SA[2:0]
DEV_CLK, RTCAS
IOCS16#, MASTER#
SMEMW#, MCS16#
IOCS#[3:0]
FCS#[1:0]
PRD#[1:0]
PWR#[1:0]
Table 2-6. Signal value on Reset
SYSRSTI# inactive
SYSRSTI# active
Signal Name
release of SYSRSTO#
SYSRSTO# active
BASIC CLOCKS AND RESETS
XTALO
14MHz
ISA_CLK
Low
7MHz
ISA_CLK2X
OSC14M
DEV_CLK
14MHz
14MHz
24MHz
HCLK
PCI_CLKO
DCLK
Oscillating at the speed defined by the strap options.
HCLK divided by 2 or 3, depending on the strap options.
17MHz
MEMORY CONTROLLER
MCLKO
66MHz if asynchonous mode, HCLK speed if synchronized mode.
CS#[3:1]
CS#[0]
High
High
MA[10:0], BA[0]
RAS#[1:0], CAS#[1:0]
MWE#, DQM[7:0]
MD[63:0]
0x00
High
High
Input
SDRAM init sequence:
Write Cycles
PCI INTERFACE
AD[31:0]
0x0000
CBE[3:0], PAR
FRAME#, TRDY#, IRDY#
STOP#, DEVSEL#
PERR#, SERR#
Low
Input
Input
Input
First prefetch cycles
when not in Local Bus mode.
22/93
Release 1.5 - January 29, 2002
PIN DESCRIPTION
Table 2-6. Signal value on Reset
SYSRSTI# inactive
SYSRSTO# active
Signal Name
SYSRSTI# active
release of SYSRSTO#
PCI_GNT#[2:0]
High
ISA BUS INTERFACE
ISAOE#
High
Low
RMRTCCS#
LA[23:17]
SA[19:0]
SD[15:0]
BHE#, MEMR#
Hi-Z
Unknown
0xFFFXX
Unknown
Unknown
0x00
First prefetch cycles
when in ISA or PCMCIA mode.
Address start is 0xFFFFF0
0xFFF03
0xFF
High
MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown
High
REF#
ALE, AEN
Unknown
Low
High
DACK_ENC[2:0]
TC
Input
Input
0x04
Low
GPIOCS#
Hi-Z
High
RTCDS#, RTCRW#, KBCS#
RTCAS
Hi-Z
Unknown
Low
LOCAL BUS INTERFACE
PA[24:0]
PD[15:0]
Unknown
Unknown
Unknown
High
High
High
0xFF
High
First prefetch cycles
PRD#
PBE#[1:0], FCS0#, FCS_0H#
FCS_0L#, FCS1#, FCS_1H#, FCS_1L#
PWR#, IOCS#[7:0]
IDE CONTROLLER
DD[15:0]
0xFF
DA[2:0]
Unknown
Unknown
High
Low
Low
PCS1, PCS3, SCS1, SCS3
PDACK#, SDACK#
PDIOR#, PDIOW#, SDIOR#, SDIOW#
VGA CONTROLLER
RED, GREEN, BLUE
VSYNC, HSYNC
COL_SEL
High
Black
Low
Unknown
TV OUTPUT
RED_TV, GREEN_TV, BLUE_TV
CVBS
VCS
Black
Black
Low
ODD_EVEN
Low
I2C INTERFACE
SCL / DDC[1]
SDA / DDC[0]
Input
Input
JTAG
TDO
High
Low
MISCELLANEOUS
SPKRD
Release 1.5 - January 29, 2002
23/93
PIN DESCRIPTION
Table 2-7. Pinout.
Pin #
T25
Pin name
Pin #
U3
Pin name
3
MD[10]
MD[11]
MD[12]
MD[13]
MD[14]
MD[15]
MD[16]
MD[17]
MD[18]
MD[19]
MD[20]
MD[21]
MD[22]
MD[23]
MD[24]
MD[25]
MD[26]
MD[27]
MD[28]
MD[29]
MD[30]
MD[31]
MD[32]
MD[33]
MD[34]
MD[35]
MD[36]
MD[37]
MD[38]
MD[39]
MD[40]
MD[41]
MD[42]
MD[43]
MD[44]
MD[45]
MD[46]
MD[47]
MD[48]
MD[49]
MD[50]
MD[51]
MD[52]
MD[53]
MD[54]
MD[55]
MD[56]
MD[57]
MD[58]
MD[59]
MD[60]
MD[61]
MD[62]
MD[63]
Pin #
AF3
Pin name
SYSRSETI#
3
3
3
3
V1
U24
T26
R25
R26
F24
D25
B20
C20
B19
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
B15
A15
C16
B14
D15
A14
B13
D13
A13
C14
B12
C13
A12
C12
A11
D12
B10
C11
A10
D10
C10
A9
W2
AE4
SYSRSETO#
XTALI
V3
A3
Y2
C4
XTALO
HCLK
W4
PCI_CLKI
PCI_CLKO
AD[0]
G23
Y1
H24
DEV_CLK
DCLK
W3
AD11
AF15
AB23
AE16
AD15
AF16
AE17
AD16
AF17
AE18
AD17
AF18
AE19
AE20
AC19
AF22
AD21
AE24
AD23
AF23
AD22
AE21
AC20
AF20
AD19
AF21
AD20
AE22
AE23
AF19
AD18
AC22
R1
AA2
Y4
AD[1]
MCLKI
MCLKO
MA[0]
AD[2]
AA1
Y3
AD[3]
AD[4]
MA[1]
AB2
AB1
AA3
AB4
AC1
AB3
AD2
AC3
AD1
AF2
AF24
AE26
AD25
AD26
AC25
AC24
AC26
AB25
AB24
AB26
AA25
Y23
AA24
AA26
Y25
Y26
Y24
W25
V23
W26
W24
V25
V26
U25
V24
U26
U23
AD[5]
MA[2]
AD[6]
MA[3]
AD[7]
MA[4]
AD[8]
MA[5]
AD[9]
MA[6]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
CBE[0]
CBE[1]
CBE[2]
CBE[3]
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
PAR
MA[7]
3
MA[8]
3
MA[9]
MA[10]
MA[11]/BA[0]
CS#[0]
CS#[1]
CS#[2]/MA[11]
CS#[3]/MA[12]/BA[1]
RAS#[0]
RAS#[1]
CAS#[0]
CAS#[1]
DQM#[0]
DQM#[1]
DQM#[2]
DQM#[3]
DQM#[4]
DQM#[5]
DQM#[6]
DQM#[7]
MWE#
3
3
3
3
3
3
3
3
3
3
3
MD[0]
3
T2
MD[1]
R3
MD[2]
MD[3]
MD[4]
MD[5]
MD[6]
MD[7]
MD[8]
MD[9]
B8
T1
A8
R4
B7
U2
D8
T3
A7
U1
C8
U4
B6
V2
24/93
Release 1.5 - January 29, 2002
PIN DESCRIPTION
Pin #
D7
Pin name
Pin #
J24
Pin name
Pin #
E24
Pin name
IRQ_MUX[2]
IRQ_MUX[3]
DREQ_MUX[0]
DREQ_MUX[1]
DACK_ENC[0]
DACK_ENC[1]
DACK_ENC[2]
TC
SERR#
LOCK#
SD[9]
A6
G25
H23
D24
C26
A25
B24
SD[10]
SD[11]
SD[12]
SD[13]
SD[14]
SD[15]
C25
A24
B23
C23
A23
B22
D22
N3
D20
C21
A21
C22
A22
B21
A5
PCI_REQ#[0]
PCI_REQ#[1]
PCI_REQ#[2]
PCI_GNT#[0]
PCI_GNT#[1]
PCI_GNT#[2]
PCI_INT#[0]
PCI_INT#[1]
PCI_INT#[2]
PCI_INT#[3]
AD4
AF4
C9
ISA_CLK
ISA_CLK2X
OSC14M
ALE
KBCS#
C6
B4
AF9
RED
D5
P25
AE8
R23
P26
R24
N25
N23
N26
P24
N24
M26
M25
L25
M24
L26
T24
M23
A4
AE9
AD8
AC5
AE5
AC10
AE10
AD7
GREEN
BLUE
ZWS#
F2
LA[17]/DA[0[
LA[18]/DA[1]
LA[19]/DA[2]
LA[20]/PCS1#
LA[21]/PCS3#
LA[22]/SCS1#
LA[23]/SCS3#
SA[0]
BHE#
VSYNC
HSYNC
VREF_DAC
RSET
G4
F3
MEMR#
MEMW#
SMEMR#
SMEMW#
IOR#
F1
G2
G1
H2
J4
COMP
IOW#
AE15
AD5
AF7
AF5
AE6
AC7
AD6
AF6
AE7
VCLK
VIN[0]
VIN[1]
VIN[2]
VIN[3]
VIN[4]
VIN[5]
VIN[6]
VIN[7]
MCS16#
IOCS16#
MASTER#
REF#
H1
H3
J2
SA[1]
SA[2]
SA[3]
J1
SA[4]
AEN
K2
SA[5]
IOCHCK#
IOCHRDY
ISAOE#
RTCAS
J3
SA[6]
K1
SA[7]
K4
SA[8]
L2
SA[9]
P3
RTCDS#
RTCRW#
RMRTCCS#
GPIOCS#
AD10
AF11
AE12
AE13
AC12
AF14
AE11
AF12
AE14
AC14
RED_TV
K3
SA[10]
R2
GREEN_TV
BLUE_TV
VCS
L1
SA[11]
P1
M2
M1
L3
SA[12]
AE3
SA[13]
ODD_EVEN
CVBS
3
SA[14]
G26
A20
B1
PA[22]
3
N2
M4
M3
P2
SA[15]
PA[23]
IREF1_TV
VREF1_TV
IREF2_TV
VREF2_TV
SA[16]
PIRQ
SA[17]
C2
C1
D2
D3
D1
E2
SIRQ
SA[18]
PDRQ
P4
SA[19]
SDRQ
K25
L24
K26
K23
J25
K24
J26
H25
H26
SD[0]
PDACK#
SDACK#
PDIOR#
PDIOW#
SDIOR#
SDIOW#
SD[1]
C5
B5
SPKRD
SCL
SD[2]
SD[3]
E4
C7
B3
SDA
SD[4]
E3
SCAN_ENABLE
COL_SEL
TCLK
SD[5]
E1
C15
G3
N1
W1
SD[6]
SD[7]
E23
D26
IRQ_MUX[0]
IRQ_MUX[1]
TMS
SD[8]
TDI
Release 1.5 - January 29, 2002
25/93
PIN DESCRIPTION
Pin #
AC2
Pin name
Pin #
P11:16
P23
Pin name
TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD12
AF8
VDDA_TV
R11:16
T11:16
V4
VDD_DAC1
1
G24
VDD_CPUCLK_PLL
1
AD13
F25
VDD_DCLK_PLL
W23
1
VDD_DEVCLK_PLL
AC4
1
AC17
AC15
F26
VDD_MCLKI_PLL
AC8
1
VDD_MCLKO_PLL
AC13
AC18
AC23
AD3
1
VDD_HCLK_PLL
1
E25
VDD_SKEW_PLL
1
D11
L23
T4
VDD_CORE
AD14
AD24
AE1:2
AE25
AF1
COMPENSATION_VS
1
VDD_CORE
VSS
VSS
VSS
VSS
VSS
VSS
1
VDD_CORE
1
AC6
VDD_CORE
D6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AF25
AF26
D16
D21
F4
A16
B9
Unconnected
Unconnected
Unconnected
Unconnected
Unconnected
Unconnected
Unconnected
F23
AC11
AC16
AC21
AA4
AA23
T23
L4
B11
D18
E26
AD9
AF10
1
Note ; These pins must be
connected to the 2.5 V power
supply. They must not be
connected to the 3.3 V supply.
AF13
AC9
A1:2
A26
VSSA_TV
VSS_DAC1
VSS
VSS
B2
VSS
B25:26
C3
VSS
VSS
C24
D4
VSS
VSS
D9
VSS
D14
D19
D23
H4
VSS
VSS
VSS
VSS
J23
VSS
L11:16
M11:16
N4
VSS
VSS
VSS
N11:16
VSS
26/93
Release 1.5 - January 29, 2002
STRAP OPTIONS
3. STRAP OPTIONS
This chapter defines the STPC Consumer-II Strap
Options and their location. Some strap options are
left programmable for future versions of silicon. .
Table 3-1. Strap Options
1
Signal
MD1
Designation
Actual Settings
Set to ’0’
Set to ’1’
Reserved
Pull up
User defined
User defined
User defined
User defined
User defined
Pull down
Pull down
Pull down
Pull up
-
-
MD2
see
bit 6
bit 7
bit 1
Section 3.1.4.
Section 3.1.4.
Section 3.1.3.
HCLK PLL Speed
PCICLKO Division
MD3
see
see
MD4
MD5
MCLK/HCLK Sync (see
)
Async
see
Sync
Section 3.1.1.
MD6
PCICLKO frequency
Reserved
bit 6
Section 3.1.1.
MD7
-
-
MD10
MD11
MD14
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
TC
Reserved
-
-
-
-
-
Reserved
-
Reserved
-
Reserved
Pull up
-
PCI_CLKO Divisor
Reserved
User defined
Pull-up
see
bit 1
Section 3.1.3.
-
-
-
Reserved
Pull-up
-
DCLK Pad Direction
Reserved
User defined
Pull up
Input
Output
-
-
-
-
-
-
Reserved
Pull up
Reserved
Pull up
User defined
User defined
User defined
Pull down
Pull down
Pull down
Pull down
User defined
Pull down
Pull up
see
bit 3
Section 3.1.4.
Section 3.1.4.
Section 3.1.4.
HCLK PLL Speed
see
see
bit 4
bit 5
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
CPU Mode (see
)
X1
X2
Section 3.1.3.
Reserved
Reserved
Reserved
-
-
-
-
Pull down
User defined
Pull down
Pull up
-
-
Bus select (see
)
ISA
Local Bus
Section 3.1.1.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
Pull down
Pull up
Pull up
DACK_ENC[2:0]
Pull up
1
Note : Where a strap is represented by a ’Pull up’ or ’Pull down’, these have to be adhered to. If it is represented as a ’-
’ it can be left unconnected. Where ’User defined’, the strap is set by the user.
Release 1.5 - January 29, 2002
27/93
STRAP OPTIONS
3.1. POWER-ON STRAP REGISTER DESCRIPTIONS
3.1.1. ADPC STRAP REGISTER 0 CONFIGURATION
Strap0
Access = 0022h/0023h
Regoffset = 04Ah
0
7
6
5
4
3
2
1
See Table
below
See Table
below
See Table
below
See Table
belowl
MD[7]
MD[6]
MD[4]
Rsv
This register defaults to the values sampled on MD[7:4] pins after reset
Bit Number Sampled
Mnemonic
Description
PCICLK PLL set-up:
The value sampled on MD[7:6] controls the
PCICLK PLL programming according to PCICLK frequency.
MD7 MD6
Bits 7-6
MD[7:6]
0
0
1
0
1
X
PCICLK frequency between 16 & 32 MHz
PCICLK frequency between 32 & 64 MHz
Reserved
MD[5]
For the parts referenced STPCC4, see section
bit 2.
Section 3.1.1.
For the parts referenced STPCC5, this s
trap selects betwen Local
Bus or ISA mode.
0 = ISA Mode
Bit 5
MD[44]
1 = Local Bus Mode
This strap is not readable in a register for the STPCC4.
PCICLK division: This bit reflects the value sampled on [MD4] and is
used together with MD[17] to select the PCICLK frequency.
MD4 MD17
Bit 4
MD[4]
0
1
1
X
0
1
PCI Clock output = HCLK / 4
PCI Clock output = HCLK / 3
PCI Clock output = HCLK / 2
Rsv
MD[5]
Rsv
For the parts referenced STPCC4 These bits are reserved
Host Memory synchronization. This bit reflects the value sampled on
MD[5] and controls the MCLK/HCLK synchronization.
0: MCLK and HCLK not synchronized
Bits 2
1: MCLK and HCLK synchronized for improved system performance.
For the parts referenced STPCC4 These bits are reserved
For the parts referenced STPCC5.
These bits reflect the values sampled on MD[17] pin and
controls the PCI clock output in conjunction with MD[4], as
follows:
MD4 MD17
Bit 1-0
MD[4,17]
0
1
1
X
0
1
PCI Clock output = HCLK / 4
PCI Clock output = HCLK / 3
PCI Clock output = HCLK / 2
28/93
Release 1.5 - January 29, 2002
STRAP OPTIONS
3.1.2. ADPC STRAP REGISTER 1 CONFIGURATION
Strap1
Access = 0022h/0023h
Regoffset = 04Bh
7
6
5
4
3
2
1
0
Rsv
Rsv
Rsv
Rsv
Rsv
This register defaults to the values sampled on MD[13:10] pins after reset
Bit Number Sampled
Bits 7-6
Mnemonic
Rsv
Description
Reserved
Reserved
Reserved
Bits 5-2
MD[13:10]
Rsv
Bits 1-0
Release 1.5 - January 29, 2002
29/93
STRAP OPTIONS
3.1.3. ADPC STRAP REGISTER 2 CONFIGURATION
Strap2
Access = 0022h/0023h
Regoffset = 04Ch
0
7
6
5
4
3
2
1
See Table
below
See Table
below
Rsv
MD[20]
MD[19]
MD[18]
Rsv
This register defaults to the values sampled on MD pins after reset
Bit Number Sampled
Mnemonic
Description
Rsv
For the parts referenced STPCC4, Reserved
For the parts referenced STPCC5, this bit reflects the value sampled on
MD[40] is used is used to set the clock multiplication factor of the 486
core, as follows:
Bits 7
MD[40]
MD[40]
0
1
DX (X1)
DX2 (X2)
This strap is not readable in a register for the STPCC4.
Bit 6-5
Bits 4
Rsv
Reserved
This bit reflects the value sampled on MD[20] pin and controls
the Dot clock (DCLK) source as follows:
0: External. DCLK pin is an input.
1: Internal. DCLK pin is an output and is connected to the
internal frequency synthesizer output. Note this bit is writeable
as well as readable.
MD[20]
Bit 3
Bit 2
Rsv
Rsv
Reserved
Reserved
MD[17]
Rsv
For the parts referenced STPCC4, see section
bits 1:0.
Section 3.1.1.
Bit 1
Bit 0
For the parts referenced STPCC5.This bit is reserved and not connected
Rsv
Reserved
30/93
Release 1.5 - January 29, 2002
STRAP OPTIONS
3.1.4. CPC STRAP REGISTER 0 CONFIGURATION
HCLK_Strap
Access = 0022h/0023h
Regoffset = 05Fh
7
6
5
4
3
2
1
0
MD[3}
MD[2]
MD[26]
MD[25]
MD[24]
Rsv
This register defaults to the values sampled on MD pins after reset
Bit Number Sampled
Bits 7-3
Mnemonic
Description
These pins reflect the values sampled on MD[3:2] and
MD[3:2] & MD[26:24] MD[26:24] pins respectively and control the Host clock
frequency synthesizer as shown in Table 3-1
Bits 2-0
Rsv
Reserved
Table 3-1. HCLK Frequency Programming
MD[3]
MD[2]
MD[26]
MD[25]
MD[24]
HCLK Speed
25 MHz
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
50 MHz
60 MHz
66 MHz
75 MHz
90 MHz
100 MHz
Release 1.5 - January 29, 2002
31/93
STRAP OPTIONS
32/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
4. ELECTRICAL SPECIFICATIONS
4.1. INTRODUCTION
4.2.3. RESERVED DESIGNATED PINS
Pins designated as reserved should be left dis-
connected. Connecting a reserved pin to a pull-up
resistor, pull-down resistor, or an active signal
could cause unexpected results and possible
circuit malfunctions.
The electrical specifications in this chapter are
valid for the STPC Consumer-II.
4.2. ELECTRICAL CONNECTIONS
4.2.1.
POWER/GROUND
CONNECTIONS/
4.3. ABSOLUTE MAXIMUM RATINGS
DECOUPLING
The following table lists the absolute maximum
ratings for the STPC Consumer-II device.
Stresses beyond those listed under Table 4-1
limits may cause permanent damage to the
device. These are stress ratings only and do not
imply that operation under any conditions other
than those specified in section "Operating
Conditions".
Due to the high frequency of operation of the
STPC Consumer-II, it is necessary to install and
test this device using standard high frequency
techniques. The high clock frequencies used in
the STPC Consumer-II and its output buffer
circuits can cause transient power surges when
several output buffers switch output levels
simultaneously. These effects can be minimized
by filtering the DC power leads with low-
inductance decoupling capacitors, using low
impedance wiring, and by utilizing all of the VSS
and VDD pins.
Exposure to conditions beyond those outlined in
Table 4-1 may (1) reduce device reliability and (2)
result in premature failure even when there is no
immediately apparent sign of failure. Prolonged
exposure to conditions at or near the absolute
maximum ratings (Table 4-1) may also result in
reduced useful life and reliability.
4.2.2. UNUSED INPUT PINS
No unused input pin should be left unconnected
unless they have an integrated pull-up or pull-
down. Connect active-low inputs to VDD through a
20 kΩ (±10%) pull-up resistor and active-high
inputs to VSS. For bi-directionnal active-high
inputs, connect to VSS through a 20 kΩ (±10%)
pull-up resistor to prevent spurious operation.
4.3.1. 5V TOLERANCE
The STPC is capable of running with I/O systems
that operate at 5 V such as PCI and ISA devices.
Certain pins of the STPC tolerate inputs up to
5.5 V. Above this limit the component is likely to
sustain permanent damage. .
Table 4-1. Absolute Maximum Ratings
Symbol
Parameter
Minimum
Maximum
4.0
Units
V
V
DC Supply Voltage
-0.3
-0.3
-0.3
-0.3
-
DDx
V
DC Supply Voltage for Core
Digital Input and Output Voltage
5Volt Tolerance
2.7
V
CORE
V , V
VDD + 0.3
5.5
V
I
O
V
V
5T
V
T
ESD Capacity (Human body mode)
Storage Temperature
2000
+150
+85
°C
ESD
STG
-40
0
°C
°C
W
T
Operating Temperature (Note 1)
OPER
-40
-
+115
4.8
P
Maximum Power Dissipation (package)
TOT
Note 1: The figures specified apply to the Tcase of a
STPC device that is soldered to a board, as detailed in
the Design Guidelines Section, for Commercial and In-
dustrial temperature ranges.
Release 1.5 - January 29, 2002
33/93
ELECTRICAL SPECIFICATIONS
4.4. DC CHARACTERISTICS
Table 4-2. DC Characteristics
Test conditions
Symbol
Parameter
Operating Voltage
Operating Voltage
Supply Power
Min
3.0
Typ
3.3
2.5
Max
3.6
Unit
V
V
DD
V
2.45
2.7
V
CORE
P
3.0V < V < 3.6V
0.18
2.90
0.8
W
W
V
DD
DD
P
Supply Power
2.45V < V
< 2.7V
CORE
CORE
Except XTALI
XTALI
-0.3
-0.3
2.1
V
Input Low Voltage
Input High Voltage
IL
0.8
V
Except XTALI
XTALI
V
V
+0.3
V
DD
V
IH
2.35
-5
+0.3
V
DD
I
Input Leakage Current
Integrated Pull up/down
Input, I/O
5
µA
KΩ
LK
50
Table 4-3. PAD buffers DC Characteristics
I/O
count
V
min V max V min
V
max I min I max C
max Derating
C
(pF)
IH
IL
OH
OL
OL
OH
load
IN
Buffer Type
1
(V)
(V)
(V)
(V)
(mA)
(mA)
(pF)
(ps/pF)
ANA
8
2.35
2.1
-
0.9
0.8
-
-
-
-
2
8
4
4
8
8
8
8
1.5
16
-
-
- 2
- 8
- 4
- 4
- 8
- 8
- 8
- 8
- 0.5
-16
-
-
-
-
OSCI13B
1
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
50
-
-
BT8TRP_TC
5
200
100
100
200
200
200
200
200
400
-
21
42
41
23
23
21
21
15
12
-
6.89
5.97
5.97
5.96
5.96
7.02
7.03
6.97
9.34
5.97
5.97
5.97
5.97
BD4STRP_FT
BD4STRUP_FT
BD8STRP_FT
BD8STRUP_FT
BD8STRP_TC
BD8TRP_TC
BD8PCIARP_FT
BD16STARUQP_TC
SCHMITT_FT
TLCHT_FT
50
10
26
40
10
60
2
0.8
0.8
0.8
0.8
0.8
0.8
0.3*V
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
49 0.5*V
0.9*V
0.1*V
DD
DD
DD
DD
19
1
2
2
2
2
2
2.4
0.4
-
-
-
-
-
-
-
-
5
-
-
-
-
TLCHT_TC
1
-
-
-
-
TLCHTD_TC
1
-
-
-
-
Note 1: time to output variation depending on the capacitive load.
Table 4-4. RAMDAC DC Specification
Parameter
Symbol
Vref_dac
INL
DNL
BLC
Min
1.00 V
Max
1.24 V
3 LSB
1 LSB
2.0 mA
18.50 mA
Voltage Reference
Integrated Non Linear Error
Differentiated Non Linear Error
Black Level Current
-
-
1.0 mA
15.00 mA
WLC
White Level Current
34/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
Table 4-5. VGA RAMDAC Power Consumption
DCLK
DAC mode
P
(mW)
Max
VDD_DAC = 2.45V
VDD_DAC = 2.7V
(MHz)
-
6.25 - 135
(State)
Shutdown
Active
0
150
0
180
Table 4-6. 2.5V Power Consumptions (V
+ VDD_x_PLL + VDD_DAC)
CORE
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
DCLK
(MHz)
PMU
P
(W)
Max
Mode
V
=2.45V
V
=2.7V
2.5V
(State)
2.5V
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
0.6
1.4
0.9
1.7
0.8
1.5
1.5
2.1
0.7
1.7
0.9
1.9
0.8
1.6
1.5
2.3
0.9
Stopped
135
1.8
1.2
2.3
1.1
2.0
1.9
2.7
0.9
2.1
1.2
2.5
1.1
2.1
1.9
2.9
66
100
66
66 (x1)
100 (x1)
133 (x2)
133 (x2)
66
100
66
SYNC
Stopped
135
SYNC
SYNC
Stopped
135
Stopped
135
66
100
ASYNC
Note 1: PCI clock at 33MHz
Table 4-7. 3.3V Power Consumptions (V
)
DD
HCLK
(MHz)
CPUCLK
MCLK
(MHz)
DCLK
PMU
P
Max
(mW)
(MHz)
(MHz)
6.26
135
6.26
135
6.26
135
6.26
135
(State)
90
66
100
66
66 (x1)
66
100
66
Full Speed
Full Speed
Full Speed
Full Speed
160
115
180
100
165
115
180
100 (x1)
133 (x2)
133 (x2)
66
100
Table 4-8. PLL Power Consumptions
P
(mW)
Max
PLL name
VDD_PLL = 2.45V
VDD_PLL = 2.7V
VDD_DCLK_PLL
VDD_DEVCLK_PLL
VDD_HCLKI_PLL
VDD_HCLKO_PLL
VDD_MCLKI_PLL
VDD_MCLKO_PLL
VDD_PCICLK_PLL
5
5
5
5
5
5
5
10
10
10
10
10
10
10
Release 1.5 - January 29, 2002
35/93
ELECTRICAL SPECIFICATIONS
4.5. AC CHARACTERISTICS
are shown in Table 4-9 below. Input or output
signals must cross these levels during testing.
This section lists the AC characteristics of the
STPC interfaces including output delays, input
setup requirements, input hold requirements and
output float delays. These measurements are
based on the measurement points identified in
Figure 4-1 and Figure 4-2. The rising clock edge
reference level VREF and other reference levels
Figure 4-1 shows output delay (A and B) and input
setup and hold times (C and D). Input setup and
hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window
a synchronous input signal must be stable for
correct operation.
Table 4-9. Drive Level and Measurement Points for Switching Characteristics
Symbol
Value
1.5
Units
V
V
V
V
REF
V
2.5
IHD
V
0.0
ILD
Note: Refer to Figure 4-1.
Figure 4-1. Drive Level and Measurement Points for Switching Characteristics
Tx
V
V
IHD
CLK:
Ref
ILD
V
A
MAX
B
MIN
Valid
Output n
Valid
Output n+1
V
OUTPUTS:
Ref
C
D
V
V
IHD
Valid
Input
INPUTS:
LEGEND:
Ref
ILD
V
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
36/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
Figure 4-2. CLK Timing Measurement Points
T1
T2
V
IH (MIN)
V
V
Ref
IL (MAX)
CLK
T5
T3
T4
T1 - One Clock Cycle
T2 - Minimum Time at V
LEGEND:
IH
IL
T3 - Minimum Time at V
T4 - Clock Fall Time
T5 - Clock Rise Time
NOTE; All sIgnals are sampled on the rising edge of the CLK.
Release 1.5 - January 29, 2002
37/93
ELECTRICAL SPECIFICATIONS
4.5.1. POWER ON SEQUENCE
Strap Options are continuously sampled during
SYSRSTI# low and must remain stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# goes high.
Figure 4-3 describes the power-on sequence of
the STPC, also called cold reset.
There is no dependency between the different
power supplies and there is no constraint on their
rising time.
Bus activity starts only few clock cycles after the
release of SYSRSTO#. The toggling signals
depend on the STPC configuration.
In ISA mode, activity is visible on PCI prior to the
ISA bus as the controller is part of the south
bridge.
In Local Bus mode, the PCI bus is not accessed
and the Flash Chip Select is the control signal to
monitor.
SYSRSTI# as no constraint on its rising edge but
must stay active until power supplies are all within
µ
margin of 10 s is even
specifications,
a
recommended to let the STPC PLLs and strap
options stabilize.
Figure 4-3. Power-on timing diagram
Power Supplies
14 MHz
> 10 us
1.6 V
SYSRSTI#
ISACLK
VALID CONFIGURATION
Strap Options
HCLK
PCI_CLK
2.3 ms
SYSRSTO#
38/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
4.5.2 RESET SEQUENCE
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
Figure 4-4 describes the reset sequence of the
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
Figure 4-4. Reset timing diagram
14 M Hz
1.6 V
SYSRSTI#
ISACLK
M D[63:0]
Strap Options
HCLK
VALID CONFIGURATION
PCI_CLK
SYSRSTO#
2.3 ms
Release 1.5 - January 29, 2002
39/93
ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure 4-5, Table 4-10 lists the AC characteristics
of the SDRAM interface.
Figure 4-5. SDRAM Timing Diagram
MCLKx
MCLKI
T
delay
T
T
low
high
T
cycle
STPC.output
STPC.input
T
T
output (min)
output (max)
T
T
setup
hold
Table 4-10. SDRAM Bus AC Timing
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Name
Tcycle
Thigh
Tlow
Parameter
Min
10
4
Typ
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
4
MCLKI Rising Time
1
1
MCLKI Falling Time
-0.9
Tdelay
MCLKx to MCLKI delay
MCLKI to Outputs Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MD[63:0] setup to MCKLI
MD[63:0] hold from MCKLI
5.2
6.5
7
8.8
8.8
4.0
2.5
Toutput
6.5
3.75
1.3
Tsetup
Thold
Note: These timing are for a load of 50pF.
For correct operation, the programmable read
clock delay (RDCLK) must be activated for the
CRTC and the delay set to the minimum. This is
done by setting the Latch_CRTC_Data_In bit in
the SDRAM Controller register 0 and clear the
bits[3:0] in register 1.
The PC133 memory is recommended to reach
100MHz operation.
40/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
4.5.4. PCI INTERFACE
Table 4-11 lists the AC characteristics of the PCI
interface.
Table 4-11. PCI Bus AC Timing
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Name
Parameter
HCLK to PCICLKO delay (MD[30:27] = 0000)
HCLK to PCICLKI delay
PCICLKO Cycle Time
PCICLKO High Time
2.9
30
4.3
5.8
PCICLKO Low Time
PCICLKI Cycle Time
30
PCICLKI High Time
PCICLKI Low Time
PCICLKI Rising Time
PCICLKI Falling Time
PCICLKI to any output
PCICLKI to PCI_GNT#[2:0]
Setup to PCICKLI
5.9
6.8
2.2
2.9
7.2
4.8
-
-
-
-
-
-
15.8
16.8
-
-
-
-
FRAME# Setup to PCICKLI
PCI_REQ#[2:0] Setup to PCICKLI
Hold from PCICLKI
Release 1.5 - January 29, 2002
41/93
ELECTRICAL SPECIFICATIONS
4.5.5 IPC INTERFACE
Table 4-12 lists the AC characteristics of the IPC
interface.
Figure 4-6. IPC timing diagram
ISACLK2X
ISACLK
T
dly
T
T
setup
setup
IRQ_MUX[3:0]
DREQ_MUX[1:0]
Table 4-12. IPC Interface AC Timings
Name
Parameter
ISACLK2X to ISACLK delay
Min
Max
Unit
nS
T
dly
ISACLK2X to DACK_ENC[2:0] valid
ISACLK2X to TC valid
nS
nS
T
T
IRQ_MUX[3:0] Input setup to ISACLK2X
DREQ_MUX[1:0] Input setup to ISACLK2X
0
0
-
-
nS
nS
setup
setup
42/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS
Table 4-7 and Table 4-13 list the AC characteris-
tics of the ISA interface.
Table 4-13
Figure 4-7 ISA Cycle (ref
)
2
15
38
37
14
13
9
12
25
56
29
18
ALE
AEN
22
Valid AENx
3
34
33
LA [23:17]
SA [19:0]
Valid Address
42
11
24
41
57
27
10
Valid Address, SBHE*
26
23
55
58
59
28
64
48
47
61
CONTROL (Note 1)
IOCS16#
MCS16#
54
IOCHRDY
READ DATA
WRITE DATA
V.Data
VALID DATA
Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
The clock has not been represented as it is dependent on the ISA Slave mode.
Table 4-13. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
2
LA[23:17] valid before ALE# negated
5T
Cycles
3
LA[23:17] valid before MEMR#, MEMW# asserted
3a Memory access to 16-bit ISA Slave
3b Memory access to 8-bit ISA Slave
5T
5T
1T
Cycles
Cycles
Cycles
9
SA[19:0] & SBHE valid before ALE# negated
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
10a Memory access to 16-bit ISA Slave
10b Memory access to 8-bit ISA Slave
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
10c Memory access to 16-bit ISA Slave
10
2T
2T
Cycles
Cycles
10
2T
Cycle
Table 4-7
Note: The signal numbering refers to
Release 1.5 - January 29, 2002
43/93
ELECTRICAL SPECIFICATIONS
Table 4-13. ISA Bus AC Timing
Name
Parameter
10d Memory access to 8-bit ISA Slave
Min
2T
Max
Units
Cycle
Cycles
10e
SA[19:0] & SBHE valid before IOR#, IOW# asserted
ISACLK2X to IOW# valid
2T
11
11a Memory access to 16-bit ISA Slave - 2BCLK
11b Memory access to 16-bit ISA Slave - Standard 3BCLK
11c Memory access to 16-bit ISA Slave - 4BCLK
11d Memory access to 8-bit ISA Slave - 2BCLK
Memory access to 8-bit ISA Slave - Standard 3BCLK
ALE# asserted before ALE# negated
2T
2T
2T
2T
2T
1T
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
11e
12
13
ALE# asserted before MEMR#, MEMW# asserted
13a Memory Access to 16-bit ISA Slave
13b Memory Access to 8-bit ISA Slave
ALE# asserted before SMEMR#, SMEMW# asserted
13c Memory Access to 16-bit ISA Slave
13d Memory Access to 8-bit ISA Slave
ALE# asserted before IOR#, IOW# asserted
ALE# asserted before AL[23:17]
2T
2T
Cycles
Cycles
13
2T
2T
2T
Cycles
Cycles
Cycles
13e
14
14a Non compressed
15T
15T
Cycles
Cycles
14b Compressed
15
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
15a Memory Access to 16-bit ISA Slave- 4 BCLK
15e Memory Access to 8-bit ISA Slave- Standard Cycle
ALE# negated before LA[23:17] invalid (non compressed)
ALE# negated before LA[23:17] invalid (compressed)
MEMR#, MEMW# asserted before LA[23:17]
11T
11T
14T
14T
Cycles
Cycles
Cycles
Cycles
18a
18a
22
22a Memory access to 16-bit ISA Slave.
13T
13T
Cycles
Cycles
22b Memory access to 8-bit ISA Slave.
23
23
23
24
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
23b Memory access to 16-bit ISA Slave Standard cycle
23e Memory access to 8-bit ISA Slave Standard cycle
9T
9T
Cycles
Cycles
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
23h Memory access to 16-bit ISA Slave Standard cycle
23l Memory access to 16-bit ISA Slave Standard cycle
IOR#, IOW# asserted before IOR#, IOW# negated
23o Memory access to 16-bit ISA Slave Standard cycle
23r Memory access to 8-bit ISA Slave Standard cycle
MEMR#, MEMW# asserted before SA[19:0]
9T
9T
Cycles
Cycles
9T
9T
Cycles
Cycles
24b Memory access to 16-bit ISA Slave Standard cycle
24d Memory access to 8-bit ISA Slave - 3BLCK
24e Memory access to 8-bit ISA Slave Standard cycle
24f Memory access to 8-bit ISA Slave - 7BCLK
SMEMR#, SMEMW# asserted before SA[19:0]
10T
10T
10T
10T
Cycles
Cycles
Cycles
Cycles
24
24h
24i
Memory access to 16-bit ISA Slave Standard cycle
Memory access to 16-bit ISA Slave - 4BCLK
Memory access to 8-bit ISA Slave - 3BCLK
Memory access to 8-bit ISA Slave Standard cycle
10T
10T
10T
10T
Cycles
Cycles
Cycles
Cycles
24k
24l
Table 4-7
Note: The signal numbering refers to
44/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
Table 4-13. ISA Bus AC Timing
Name
24
Parameter
IOR#, IOW# asserted before SA[19:0]
Min
Max
Units
24o
24r
I/O access to 16-bit ISA Slave Standard cycle
I/O access to 16-bit ISA Slave Standard cycle
19T
19T
Cycles
Cycles
25
25
MEMR#, MEMW# asserted before next ALE# asserted
25b
25d
Memory access to 16-bit ISA Slave Standard cycle
Memory access to 8-bit ISA Slave Standard cycle
10T
10T
Cycles
Cycles
SMEMR#, SMEMW# asserted before next ALE# asserted
25e
25f
Memory access to 16-bit ISA Slave - 2BCLK
Memory access to 16-bit ISA Slave Standard cycle
Memory access to 8-bit ISA Slave Standard cycle
10T
10T
10T
Cycles
Cycles
Cycles
25h
25
26
26
26
28
28
IOR#, IOW# asserted before next ALE# asserted
25i
I/O access to 16-bit ISA Slave Standard cycle
I/O access to 16-bit ISA Slave Standard cycle
10T
10T
Cycles
Cycles
25k
MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted
26b
26d
Memory access to 16-bit ISA Slave Standard cycle
Memory access to 8-bit ISA Slave Standard cycle
12T
12T
Cycles
Cycles
SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted
26f
Memory access to 16-bit ISA Slave Standard cycle
Memory access to 8-bit ISA Slave Standard cycle
12T
12T
Cycles
Cycles
26h
IOR#, IOW# asserted before next IOR#, IOW# asserted
26i
I/O access to 16-bit ISA Slave Standard cycle
I/O access to 8-bit ISA Slave Standard cycle
12T
12T
Cycles
Cycles
26k
Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted
28a
28b
Memory access to 16-bit ISA Slave
Memory access to 8-bit ISA Slave
3T
3T
Cycles
Cycles
Any command negated to IOR#, IOW# asserted
28c I/O access to ISA Slave
3T
1T
1T
1T
Cycles
Cycles
Cycles
Cycles
29a
29b
29c
33
MEMR#, MEMW# negated before next ALE# asserted
SMEMR#, SMEMW# negated before next ALE# asserted
IOR#, IOW# negated before next ALE# asserted
LA[23:17] valid to IOCHRDY negated
33a
33b
Memory access to 16-bit ISA Slave - 4 BCLK
Memory access to 8-bit ISA Slave - 7 BCLK
8T
Cycles
Cycles
14T
34
37
LA[23:17] valid to read data valid
34b
34e
Memory access to 16-bit ISA Slave Standard cycle
Memory access to 8-bit ISA Slave Standard cycle
8T
Cycles
Cycles
14T
ALE# asserted to IOCHRDY# negated
37a
37b
37c
37d
Memory access to 16-bit ISA Slave - 4 BCLK
Memory access to 8-bit ISA Slave - 7 BCLK
I/O access to 16-bit ISA Slave - 4 BCLK
I/O access to 8-bit ISA Slave - 7 BCLK
6T
12T
6T
Cycles
Cycles
Cycles
Cycles
12T
38
ALE# asserted to read data valid
38b
38e
38h
38l
Memory access to 16-bit ISA Slave Standard Cycle
Memory access to 8-bit ISA Slave Standard Cycle
I/O access to 16-bit ISA Slave Standard Cycle
I/O access to 8-bit ISA Slave Standard Cycle
4T
10T
4T
Cycles
Cycles
Cycles
Cycles
10T
Table 4-7
Note: The signal numbering refers to
Release 1.5 - January 29, 2002
45/93
ELECTRICAL SPECIFICATIONS
Table 4-13. ISA Bus AC Timing
Name
41
Parameter
SA[19:0] SBHE valid to IOCHRDY negated
Min
Max
Units
41a
41b
41c
41d
Memory access to 16-bit ISA Slave
Memory access to 8-bit ISA Slave
I/O access to 16-bit ISA Slave
I/O access to 8-bit ISA Slave
6T
12T
6T
Cycles
Cycles
Cycles
Cycles
12T
42
47
48
54
SA[19:0] SBHE valid to read data valid
42b
42e
42h
42l
Memory access to 16-bit ISA Slave Standard cycle
Memory access to 8-bit ISA Slave Standard cycle
I/O access to 16-bit ISA Slave Standard cycle
I/O access to 8-bit ISA Slave Standard cycle
4T
10T
4T
Cycles
Cycles
Cycles
Cycles
10T
MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated
47a
47b
47c
47d
Memory access to 16-bit ISA Slave
Memory access to 8-bit ISA Slave
I/O access to 16-bit ISA Slave
I/O access to 8-bit ISA Slave
2T
5T
2T
5T
Cycles
Cycles
Cycles
Cycles
MEMR#, SMEMR#, IOR# asserted to read data valid
48b
48e
48h
48l
Memory access to 16-bit ISA Slave Standard Cycle
Memory access to 8-bit ISA Slave Standard Cycle
I/O access to 16-bit ISA Slave Standard Cycle
I/O access to 8-bit ISA Slave Standard Cycle
2T
5T
2T
5T
Cycles
Cycles
Cycles
Cycles
IOCHRDY asserted to read data valid
54a
54b
54c
54d
Memory access to 16-bit ISA Slave
Memory access to 8-bit ISA Slave
I/O access to 16-bit ISA Slave
I/O access to 8-bit ISA Slave
1T(R)/2T(W)
1T(R)/2T(W)
1T(R)/2T(W)
1T(R)/2T(W)
Cycles
Cycles
Cycles
Cycles
IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, SMEMW#,
IOR#, IOW# negated
55a
1T
Cycles
55b
56
57
58
59
61
IOCHRY asserted to MEMR#, SMEMR# negated (refresh)
IOCHRDY asserted to next ALE# asserted
1T
2T
2T
0T
0T
Cycles
Cycles
Cycles
Cycles
Cycles
IOCHRDY asserted to SA[19:0], SBHE invalid
MEMR#, IOR#, SMEMR# negated to read data invalid
MEMR#, IOR#, SMEMR# negated to data bus float
Write data before MEMW# asserted
61a
Memory access to 16-bit ISA Slave
2T
2T
Cycles
Cycles
Memory access to 8-bit ISA Slave (Byte copy at end of
start)
61b
61
61
Write data before SMEMW# asserted
61c
61d
Memory access to 16-bit ISA Slave
Memory access to 8-bit ISA Slave
2T
2T
Cycles
Cycles
Write Data valid before IOW# asserted
61e
61f
I/O access to 16-bit ISA Slave
I/O access to 8-bit ISA Slave
2T
2T
1T
1T
1T
1T
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
64a
MEMW# negated to write data invalid - 16-bit
MEMW# negated to write data invalid - 8-bit
SMEMW# negated to write data invalid - 16-bit
SMEMW# negated to write data invalid - 8-bit
64b
64c
64d
Table 4-7
Note: The signal numbering refers to
46/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
Table 4-13. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
64e
IOW# negated to write data invalid
1T
Cycles
MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte
by ISA Master
64f
1T
1T
Cycles
Cycles
IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by
ISA Master
64g
Table 4-7
Note: The signal numbering refers to
Release 1.5 - January 29, 2002
47/93
ELECTRICAL SPECIFICATIONS
4.5.7. LOCAL BUS INTERFACE
Figure 4-3 to Figure 4-11 and Table 4-15 list the
AC characteristics of the Local Bus interface.
Figure 4-8. Synchronous Read Cycle
HCLK
PA[ ] bus
CSx#
T
T
T
hold
setup
active
PRD#[1:0]
PD[15:0]
Figure 4-9. Asynchronous Read Cycle
HCLK
PA[ ] bus
CSx#
T
T
T
hold
setup
end
PRD#[1:0]
PD[15:0]
PRDY
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Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
Figure 4-10. Synchronous Write Cycle
HCLK
PA[ ] bus
CSx#
T
T
T
hold
setup
active
PWR#[1:0]
PD[15:0]
Figure 4-11. Asynchronous Write Cycle
HCLK
PA[ ] bus
CSx#
T
T
T
hold
setup
end
PWR#[1:0]
PD[15:0]
PRDY
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ELECTRICAL SPECIFICATIONS
The Table 4-14 below refers to Vh, Va, Vs which
are the register value for Setup time, Active Time
and Hold time, as described in the Programming
Manual.
Table 4-14. Local Bus cycle lenght
Cycle
T
T
T
T
Unit
setup
active
hold
end
Memory (FCSx#)
Peripheral (IOCSx#)
4 + Vh
8 + Vh
2 + Va
3 + Va
4 + Vs
4 + Vs
4
4
HCLK
HCLK
Table 4-15. Local Bus Interface AC Timing
Name
Parameters
HCLK to PA bus
HCLK to PD bus
HCLK to FCS#[1:0]
HCLK to IOCS#[3:0]
HCLK to PWR#[1:0]
HCLK to PRD#[1:0]
PD[15:0] Input setup to HCLK
PD[15:0] Input hold to HCLK
PRDY Input setup to HCLK
PRDY Input hold to HCLK
Min
-
-
-
-
-
-
-
2
-
Max
15
15
15
15
15
15
4
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
-
4
-
2
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Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
4.5.8 VGA INTERFACE
Table 4-16 lists the AC characteristics of the VGA
interface.
Table 4-16. Graphics Adapter (VGA) AC Timing
Name
Parameter
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DCLK (input) Cycle Time
DCLK (input) High Time
DCLK (input) Low Time
DCLK (input) Rising Time
DCLK (input) Falling Time
DCLK (input) to R,G,B valid
DCLK (input) to HSYNC valid
DCLK (input) to VSYNC valid
DCLK (input) to COL_SEL valid
DCLK (output) Cycle Time
DCLK (output) High Time
DCLK (output) Low Time
DCLK (output) to R,G,B valid
DCLK (output) to HSYNC valid
DCLK (output) to VSYNC valid
DCLK (output) to COL_SEL valid
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ELECTRICAL SPECIFICATIONS
4.5.9 VIDEO INPUT PORT
Table 4-17 lists the AC characteristics of the VIP
interface.
Table 4-17. Video Input AC Timings
Name
Parameter
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCLK Cycle Time
VCLK High Time
VCLK Low Time
VCLK Rising Time
VCLK Falling Time
VIN[7:0] setup to VCLK
VIN[7:0] hold from VCLK
ODD_EVEN setup to VCLK
ODD_EVEN hold from VCLK
VCS setup to VCLK
VCS hold from VCLK
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Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
4.5.10 IDE INTERFACE
Table 4-18 lists the AC characteristics of the IDE
interface.
Table 4-18. IDE Interface Timing
Name
Parameters
DD[15:0] setup to PIOR#/SIOR# falling
DD[15:0} hold to PIOR#/SIOR# falling
Min
15
0
Max
-
-
Units
ns
ns
4.5.11 JTAG INTERFACE
Figure 4-12 and Table 4-17 list the AC
characteristics of the JTAG interface.
Figure 4-12. JTAG timing diagram
T
reset
TRST
T
cycle
TCK
TMS,TDI
TDO
T
T
jset
jhld
T
jout
STPC.input
STPC.output
T
T
pset
phld
T
pout
Table 4-19. JTAG AC Timings
Name
Treset
Tcycle
Parameter
Min
1
Max
Unit
Tcycle
ns
TRST pulse width
TCLK period
400
TCLK rising time
TCLK falling time
20
20
ns
ns
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ELECTRICAL SPECIFICATIONS
Table 4-19. JTAG AC Timings
Tjset
Tjhld
Tjset
Tjhld
Tjout
Tpset
Tphld
Tpout
TMS setup time
200
200
200
200
ns
ns
ns
ns
ns
ns
ns
ns
TMS hold time
TDI setup time
TDI hold time
TCLK to TDO valid
STPC pin setup time
STPC pin hold time
TCLK to STPC pin valid
30
30
30
30
54/93
Release 1.5 - January 29, 2002
ELECTRICAL SPECIFICATIONS
4.5.12 INTENSIONNALY BLANK
Release 1.5 - January 29, 2002
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ELECTRICAL SPECIFICATIONS
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Release 1.5 - January 29, 2002
MECHANICAL DATA
5. MECHANICAL DATA
Dimensions are shown in Figure 5-2, Table 5-1
and Figure 5-3, Table 5-2.
5.1. 388-PIN PACKAGE DIMENSION
The pin numbering for the STPC 388-pin Plastic
BGA package is shown in Figure 5-1.
Figure 5-1. 388-Pin PBGA Package - Top View
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
A
A
B
B
C
C
D
D
E
E
F
F
G
H
G
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
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MECHANICAL DATA
Figure 5-2. 388-pin PBGA Package - PCB Dimensions
A1 Ball Pad Corner
A
B
A
D
E
F
Detail
G
C
Table 5-1. 388-pin PBGA Package - PCB Dimensions
mm
Typ
inches
Symbols
Min
34.95
1.22
0.58
1.57
0.15
0.05
0.75
Max
35.05
1.32
0.68
1.67
0.25
0.15
0.85
Min
Typ
Max
A
B
C
D
E
F
35.00
1.27
0.63
1.62
0.20
0.10
0.80
1.375
0.048
0.023
0.062
0.006
0.002
0.030
1.378
0.050
0.025
0.064
0.008
0.004
0.032
1.380
0.052
0.027
0.066
0.001
0.006
0.034
G
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Release 1.5 - January 29, 2002
MECHANICAL DATA
Figure 5-3. 388-pin PBGA Package - Dimensions
C
F
D
E
Solderball
Solderball after collapse
B
G
A
Table 5-2. 388-pin PBGA Package - Dimensions
mm
inches
Symbols
Min
0.50
1.12
0.60
0.52
0.63
0.60
Typ
0.56
1.17
0.76
0.53
0.78
0.63
30.0
Max
0.62
1.22
0.92
0.54
0.93
0.66
Min
Typ
Max
A
B
C
D
E
F
0.020
0.044
0.024
0.020
0.025
0.024
0.022
0.046
0.030
0.021
0.031
0.025
11.8
0.024
0.048
0.036
0.022
0.037
0.026
G
Release 1.5 - January 29, 2002
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MECHANICAL DATA
5.2. 388-PIN PACKAGE THERMAL DATA
The structure in shown in Figure 5-4.
Thermal dissipation options are illustrated in
Figure 5-5 and Figure 5-6.
The 388-pin PBGA package has a Power
Dissipation Capability of 4.5W. This increases to
6W when used with a Heatsink.
Figure 5-4. 388-Pin PBGA structure
Signal layers
Power & Ground layers
Thermal balls
Figure 5-5. Thermal Dissipation Without Heatsink
Board
Board dimensions:
Junction
Ambient
Case
- 10.2 cm x 12.7 cm
Rca
Rjc
- 4 layers (2 for signals, 1 GND, 1VCC)
6
6
The PBGA is centred on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
Board
8.5
Case
125
Junction
Board
Rjb
Rba
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Ambient
Ambient
Airflow = 0
Rja = 13 °C/W
Board temperature taken at the centrecentre ba
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Release 1.5 - January 29, 2002
MECHANICAL DATA
Figure 5-6. Thermal Dissipation With Heatsink
Board
Board dimensions:
Junction
Ambient
Case
- 10.2 cm x 12.7 cm
Rca
Rjc
- 4 layers (2 for signals, 1 GND, 1VCC)
The PBGA is centred on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
3
6
Board
8.5
Case
50
Junction
Board
Rjb
Rba
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Ambient
Airflow = 0
Ambient
Board temperature taken at the centre balls
Heat sink is 11.1°C/W
Rja = 9.5 °C/W
Release 1.5 - January 29, 2002
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MECHANICAL DATA
5.3. SOLDERING RECOMMENDATIONS
Dryout section is used primarily to ensure that
the solder paste is fully dried before hitting reflow
temperatures.
High quality, low defect soldering requires
identifying the optimum temperature profile for
reflowing the solder paste, therefore optimizing
the process. The heating and cooling rise rates
must be compatible with the solder paste and
components. A typical profile consists of a
preheat, dryout, reflow and cooling sections.
Solder reflow is accomplished in the reflow zone,
where the solder paste is elevated to
a
temperature greater than the melting point of the
solder. Melting temperature must be exceeded by
°
approximately 20 C to ensure quality reflow.
In reality the profile is not a line, but rather a range
of temperatures all solder joints must be
exposed. The total temperature deviation from
component thermal mismatch, oven loading and
oven uniformity must be within the band.
The most critical parameter in the preheat
section is to minimize the rate of temperature rise
to less than C / second, in order to minimize
thermal shock on the semi-conductor
components.
2°
Figure 5-7. Reflow soldering temperature range
Temperature ( °C )
250
200
150
100
50
PREHEAT
DRYOUT
REFLOW
COOLING
0
Time ( s )
0
240
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Release 1.5 - January 29, 2002
DESIGN GUIDELINES
6. DESIGN GUIDELINES
6.1. TYPICAL APPLICATIONS
6.1.1. WEB BOX
A web box is an analog set top box providing
internet browsing capability to a TV set. It has a
TV output for connecting to the TV set, a modem
for internet connection, a smartcard interface for
the ISP access control, and an infrared interface
for the remote control or the keyboard.
The STPC Consumer-II is well suited for many
applications.
Some
of
the
possible
implementations are described below.
Figure 6-1. Web Box
SDRAM
64
R,G,B, CSYNC
S-VHS
CVBS
TV OUTPUT
FLASH
MODEM
AUDIO
16
PCI
STPC
CONSUMER-II
microphone
IDE / PCI
SmartCard
Infrared
glue logic
ISA Bus
or
Local Bus
SCART 1
SCART 2
Printer port
VIP
STV2310
Release 1.5 - January 29, 2002
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DESIGN GUIDELINES
6.2. STPC CONFIGURATION
Table 6-2. Main STPC modes
HCLK
MHz
CPU clock MCLK
The STPC is a very flexible product thanks to
decoupled clock domains and to strap options
enabling a user-optimized configuration.
C
Mode
clock ratio
133 (x2)
133 (x2)
100 (x1)
MHz
1
2
3
Synchronous
Asynchronous
Synchronous
66
66
66
100
100
As some trade off are often necessary, it is
important to do an analysis of the application
needs prior to design a system based on this
product. The applicative constraints are usually
the following:
100
The advantage of the synchronous mode
compared to the asynchronous mode is a lower
latency when accessing SDRAM from the CPU or
the PCI (saves 4 MCLK cycles for the first access
of the burst). For the same CPU to Memory
transfer performance, MCLK as to be roughly
higher by 20MHz between SYNC and ASYNC
modes (example: 66MHz SYNC
ASYNC).
In all cases, use SDRAM with CAS Latency
equals to 2 (CL2) for the best performances.
- CPU performance
- graphics / video performances
- power consumption
- PCI bandwidth
- booting time
=
96MHz
- EMC
Some other elements can help to tune the choice:
- Code size of CPU Consuming tasks
- Data size and location
The advantage of the asynchronous mode is the
capability to reprogram the MCLK speed on the
fly. This could help for applications were power
consumption must be optimized.
On the STPC side, the configurable parameters
are the following:
- synchronous / asynchronous mode
- HCLK speed
- MCLK speed
- CPU clock ratio (x1, x2)
- Local Bus / ISA bus
Regarding PCI bandwidth, the best is to have
HCLK at 100MHz as it gives twice the bandwidth
compared to HCLK at 66MHz.
The last, and more complex, information to
consider is the behaviour of the software. In case
high CPU or FPU computation is needed, it is
sometime better to be in DX2-133/MCLK=66
synchronous mode than DX2-133/MCLK=100
asynchronous mode. This depends on the locality
of the number crunching code and the amount of
data manipulated.
6.2.1. LOCAL BUS / ISA BUS
The selection between the ISA bus and the Local
Bus is relatively simple. The first one is a standard
bus but slow. The Local Bus is fast and
programmable but doesn't support any DMA nor
external master mechanisms. The Table 6-1
below summarize the selection:
Table 6-1. Bus mode selection
The Table 6-3 below gives some examples. The
right column correspond to the configuration
number as described in Table 6-2:
Need
Legacy I/O device (Floppy, ...), Super I/O
DMA capability (Soundblaster)
Flash, SRAM, basic I/O device
Fast boot
Selection
ISA Bus
Table 6-3. Clock mode selection
ISA Bus
Constraints
C
Local Bus
Local Bus
Local Bus
Local Bus
Need CPU power
Critical code fits into L1 cache
1
Boot flash of 4MB or more
Programmable Chip Select
Need CPU power
Code or data does not fit into L1 cache
3
Need high PCI bandwitdh
3
2
Before implementing a function requiring DMA
capability on the ISA bus, it is recommended to
check if it exists on PCI, or if it can be
implemented differently, in order to use the local
bus mode.
Need flexible SDRAM speed
Obviously, the values for HCLK or MCLK can be
reduced compared to Table 6-2 in case there is no
need to push the device at its limits, or when
avoiding to use specific frequency ranges (FM
radio band for example).
6.2.2. CLOCK CONFIGURATION
The CPU clock and the memory clock are
independent unless the "synchronous mode"
strap option is set (see the STRAP OPTIONS
chapter). The potential clock configurations are
then relatively limited as listed in Table 6-2.
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6.3. ARCHITECTURE RECOMMENDATIONS
This section describes the recommend
6.3.1.2. Decoupling of 3.3V and Vcore
A power plane for each of these supplies with one
decoupling capacitance for each power pin is the
minimum. The use of multiple capacitances with
values in decade is the best (for example: 10pF,
1nF, 100nF, 10uF), the smallest value, the closest
to the power pin. Connecting the various digital
power planes through capacitances will reduce
furthermore the overall impedance and electrical
noise.
implementations for the STPC interfaces. For
more
details,
download
the
Reference
from the STPC web site.
Schematics
6.3.1. POWER DECOUPLING
An appropriate decoupling of the various STPC
power pins is mandatory for optimum behaviour.
When insufficient, the integrity of the signals is
deteriorated, the stability of the system is reduced
and EMC is increased.
6.3.2. 14MHZ OSCILLATOR STAGE
The 14.31818 MHz oscillator stage can be
implemented using a quartz, which is the
preferred and cheaper solution, or using an
external 3.3V oscillator.
6.3.1.1. PLL decoupling
This is the most important as the STPC clocks are
generated from a single 14MHz stage using
multiple PLLs which are highly sensitive analog
cells. The frequencies to filter are the 25-50 KHz
range which correspond to the internal loop
bandwidth of the PLL and the 10 to 100 MHz
frequency of the output. PLL power pins can be
tied together to simplify the board layout.
The crystal must be used in its series-cut
fundamental mode and not in overtone mode. It
must have an Equivalent Series Resistance (ESR,
sometimes referred to as Rm) of less than 50
Ohms (typically 8 Ohms) and a shunt capacitance
(Co) of less than 7 pF. The balance capacitors of
16 pF must be added, one connected to each pin,
as described in Figure 6-3.
Figure 6-2. PLL decoupling
In the event of an external oscillator providing the
master clock signal to the STPC Atlas device, the
LVTTL signal should be connected to XTALI, as
described in Figure 6-3.
PWR
VDD_PLL
As this clock is the reference for all the other on-
100nF 47uF
VSS_PLL
chip
generated
clocks,
it
is
strongly
, including
recommended to shield this stage
the 2 wires going to the STPC balls, in order to
reduce the jitter to the minimum and reach the
optimum system stability.
GND
Connections must be as short as possible
Figure 6-3. 14.31818 MHz stage
XTALI
XTALO
XTALI
XTALO
3.3V
15pF
15pF
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6.3.3. SDRAM
memory and extends to the top of populated
SDRAM. Bank 0 must always be populated.
The STPC provides all the signals for SDRAM
control. Up to 128 MBytes of main memory are
supported. All Banks must be 64 bits wide. Up to 4
memory banks are available when using 16Mbit
devices. Only up to 2 banks can be connected
when using 64Mbit and 128Mbit components due
to the reallocation of CS2# and CS3# signals. This
is described in Table 6-4 and Table 6-5.
Figure 6-4, Figure 6-5 and Figure 6-6 show some
typical implementations.
The purpose of the serial resistors is to reduce
signal oscillation and EMI by filtering line
reflections. The capacitance in Figure 6-4 has a
filtering effect too, while it is used for propagation
delay compensation in the 2 other figures.
Graphics memory resides at the beginning of
Bank 0. Host memory begins at the top of graphics
Figure 6-4. One Memory Bank with 4 Chips (16-bit)
MCLKI
Length(MCLKI) = Length(MCLKy) with y = {A,B,C,D}
MCLKO
10pF
MCLKA
MCLKD
MCLKC
MCLKB
Reference Knot
CS0#
MA[12:0]
BA[1:0]
RAS0#
CAS0#
WE#
DQM[7:6]
MD[63:48]
DQM[5:4]
MD[47:32]
DQM[3:2]
MD[31:16]
DQM[1:0]
MD[15:0]
DQM[7:0]
MD[63:0]
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Figure 6-5. One Memory Banks with 8 Chips (8-bit)
MCLKI
10pF
Length(MCLKI) = Length(MCLKy) with y = {A,B,C,D,E,F,G,H}
MCLKO
CY2305
H
G
F
E
D
C
B
A
CS0#
MA[12:0]
BA[1:0]
RAS0#
CAS0#
WE#
DQM[7:0]
MD[63:0]
DQM[7]
MD[63:56]
DQM[1]
MD[15:8]
DQM[0]
MD[7:0]
Figure 6-6. Two Memory Banks with 8 Chips (8-bit)
MCLKI
y = {A,B,C,D,E,F,G,H}
x = {0,1}
x
22pF
Length(MCLKI) = Length(MCLKy ) with
MCLKO
CY2305
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
H
H
G
G F
F
E
E D
D C
C B
B A
A
CS1#
CS0#
MA[12:0]
BA[1:0]
RAS0#
CAS0#
WE#
DQM[7:0]
MD[63:0]
DQM[7]
MD[63:56]
DQM[1] DQM[0]
MD[15:8]
MD[7:0]
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For other implementations like 32-bit SDRAM
devices, refers to the SDRAM controller signal
multiplexing and address mapping described in
the following Table 6-4 and Table 6-5.
Table 6-4. DIMM Pinout
SDRAM Density
16 Mbit
64/128 Mbit
2 Banks
64/128 Mbit
4 Banks
STPC I/F
Internal Banks
2 Banks
DIMM Pin Number
...
MA[10:0]
MA[10:0]
MA11
MA[10:0]
MA11
MA[10:0]
CS2# (MA11)
CS3# (MA12)
CS3# (BA1)
BA0
123
126
39
-
-
MA12
-
-
-
BA1 (MA12)
BA0 (MA13)
122
BA0 (MA11)
BA0 (MA13)
Table 6-5. Address Mapping
Address Mapping: 16 Mbit - 2 internal banks
STPC I/F BA0 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
RAS Address A11
CAS Address A11
A22
0
A21 A2
A19 A18 A17 A16 A15 A14 A13 A12
A8 A7 A6 A5 A4 A3
A24 A23 A10 A9
Address Mapping: 64/128 Mbit - 2 internal banks
STPC I/F BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
RAS Address A11 A24
CAS Address A11
A23
0
A22
0
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
A26 A25 A10 A9 A8 A7 A6 A5 A4 A3
0
Address Mapping: 64/128 Mbit - 4 internal banks
STPC I/F BA0 BA1 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
RAS Address A11 A12
CAS Address A11 A12
A24
0
A23
0
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13
A26 A25 A10 A9 A8 A7 A6 A5 A4 A3
6.3.4. PCI BUS
PCI_CLKO must be connected to PCI_CLKI
through a 10 to 33 Ohms resistor. Figure 6-7
shows a typical implementation.
The PCI bus is always active and the following
control signals must be pulled-up to 3.3V or 5V
through 2K2 resistors even if this bus is not
connected to an external device: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,
SERR#, PCI_REQ#[2:0].
For more information on layout constraints, go to
the place and route recommendations section.
Figure 6-7. Typical PCI clock routing
PCICLKI
0 - 33pF
PCICLKA
Device A
PCICLKB
Device B
PCICLKO
PCICLKC
Device C
0 - 22
10 - 33
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In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure 6-8. This approach is also recommended
when implementing the delay on PCICLKI
according to the PCI section of the Electrical
Specifications chapter.
Figure 6-8. PCI clock routing with zero-delay clock buffer
PCICLKI
PCICLKI
PLL
PLL
PCICLKO
PCICLKO
Device A
Device A
Device B
Device C
Device D
Device B
Device C
Device D
CY2305
CY2305
Implementation 1
Implementation 2
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6.3.5. LOCAL BUS
Figure 6-9 describes how to connect a 16-bit boot
flash (the corresponding strap options must be set
accordingly).
The local bus has all the signals to connect flash
devices or I/O devices with the minimum glue
logic.
Figure 6-9. Typical 16-bit boot flash implementation
22
PA[22:1]
A[22:1]
FCS0#
CE
3V3
PRD0#
PRD1#
OE
PWR0#
PWR1#
W
B
CLK
16
RB
DQ[15:0]
LE
PD[15:0]
SYSRSTI#
RP
R
GND
STPC
M58LW064A
RESET#
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6.3.6. IPC
When an interrupt line is used internally, the
corresponding input can be grounded. In most of
the embedded designs, only few interrupts lines
are necessary and the glue logic can be simplified.
Most of the IPC signals are multiplexed: Interrupt
inputs, DMA Request inputs, DMA Acknowledge
outputs. The figure below describes a complete
implementation of the IRQ[15:0] time-multiplexing.
Figure 6-10. Typical IRQ multiplexing
74x153
1C0
IRQ[0]
Timer 0
IRQ[1]
IRQ[2]
IRQ[3]
IRQ[4]
IRQ[5]
IRQ[6]
IRQ[7]
Keyboard
Slave PIC
COM2/COM4
COM1/COM3
LPT2
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
1Y
IRQ_MUX[0]
IRQ_MUX[1]
2Y
Floppy
LPT1
B
1G 2G
74x153
1C0
Floppy
IRQ[8]
IRQ[9]
IRQ[10]
IRQ[11]
IRQ[12]
IRQ[13]
IRQ[14]
IRQ[15]
RTC
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
1Y
IRQ_MUX[2]
IRQ_MUX[3]
Mouse
FPU
PCI / IDE
PCI / IDE
2Y
B
1G 2G
ISA_CLK2X
ISA_CLK
When the interface is integrated into the STPC,
the corresponding interrupt line can be grounded
as it is connected internally.
For example, if the integrated IDE controller is
activated, the IRQ[14] and IRQ[15] inputs can be
grounded.
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The figure below describes
a
complete
logic can be simplified when only few DMA
channels are used in the application.
This glue logic is not needed in Local bus mode as
it does not support DMA transfers.
implementation of the external glue logic for DMA
Request time-multiplexing and DMA Acknowledge
demultiplexing. Like for the interrupt lines, this
Figure 6-11. Typical DMA multiplexing and demultiplexing
74x153
1C0
DRQ[0]
DRQ[1]
DRQ[2]
DRQ[3]
ISA, Refresh
ISA, PIO
ISA, FDC
ISA, PIO
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
1Y
DREQ_MUX[0]
DREQ_MUX[1]
DRQ[4]
Slave DMAC
DRQ[5]
DRQ[6]
DRQ[7]
ISA
ISA
ISA
2Y
B
1G 2G
ISA_CLK2X
ISA_CLK
74x138
Y0#
DACK0#
DACK1#
DACK2#
DACK3#
Y1#
Y2#
Y3#
Y4#
Y5#
Y6#
Y7#
DMA_ENC[0]
DMA_ENC[1]
DMA_ENC[2]
A
B
C
DACK5#
DACK6#
DACK7#
G1
G2A G2B
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6.3.7. IDE / ISA DYNAMIC DEMULTIPLEXING
describes how to implement the external glue
logic to demultiplex the IDE and ISA interfaces. In
Local Bus mode the two buffers are not needed
and the NAND gates can be simplified to inverters.
Some of the ISA bus signals are dynamically
multiplexed to optimize the pin count. Figure 6-12
Figure 6-12. Typical IDE / ISA Demultiplexing
A
B
STPC bus / DD[15:0]
RMRTCCS#
KBCS#
RTCRW#
RTCDS
74xx245
MASTER#
ISAOE#
DIR
OE
SA[19:8]
PCS1#
PCS3#
SCS1#
SCS3#
LA[22]
LA[23]
LA[24]
LA[25]
6.3.8. BASIC AUDIO USING IDE INTERFACE
low cost solution is not CPU consuming thanks to
the DMA controller implemented in the IDE
controller and can generate 16-bit stereo sound.
The clock speed is programmable when using the
speaker output.
When the application requires only basic audio
capabilities, an audio DAC on the IDE interface
can avoid using a PCI-based audio device. This
Figure 6-13. Basic audio on IDE
16
DD[15:0]
PCS1
D[15:0]
Right
CS#
*
Audio Out
PDIOW#
PDRQ
WR#
A/B
Left
SYSRSTO#
Stereo DAC
Vcc
Vcc
PR
PR
D
Q
Q
D
Q
Q
Speaker
RST
RST
74xx74
STPC
Vcc
Note * : the inverter can be removed when the DAC CS# is directly connected to GND
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6.3.9. VGA INTERFACE
COL_SEL can be used when implementing the
Picture-In-Picture function outside the STPC, for
example when multiplexing an analog video
source. In that case, the CRTC of the STPC has to
be genlocked to this analog source.
The STPC integrates a voltage reference and
video buffers. The amount of external devices is
then limited to the minimum as described in the
Figure 6-14.
DCLK is usually used by the TFT display which
has RGB inputs in order to synchronise the picture
at the level of the pixel.
All the resistors and capacitors have to be as
close as possible to the STPC while the circuit
protector DALC112S1 must be close to the VGA
connector.
When the VGA interface is not needed, the signals
R, G, B, HSYNC, VSYNC, COMP, RSET can be
left unconnected, VSS_DAC and VDD_DAC must
then be connected to GND.
The DDC[1:0] lines, not represented here, have
also to be protected when they are used on the
VGA connector.
Figure 6-14. Typical VGA implementation
VDD_DAC
COMP
2.5V
10nF
VREF_DAC
RSET
143
1%
100nF 100nF 47uF
VSS_DAC
AGND
COL_SEL
DCLK
HSYNC
VSYNC
R
G
B
75 1%
DALC112S1
3.3V AGND
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6.3.10. TV INTERFACE
VDDA_TV and VSSA_TV up to the decoupling
capacitances.
The STPC integrates a voltage reference and
video DACs. The amount of external devices is
then limited to video buffers as described in the
Figure 6-15.
The resistors and capacitors of the amplifier stage
have to be as close as possible to the video buffer.
When the TV interface is not needed, the signals
RED, GREEN, BLUE, CVBS, IREF1, IREF2 can
be left unconnected, VDDA_TV must then be
connected to GND.
The connection from IREFx and VREFx up to the
20 ohms resistors must be as short as possible.
The constraint is the same for the connection from
Figure 6-15. Typical VGA implementation
20 1%
IREF1
VREF1
IREF2
AGND
AGND
5V
R
= 20K 1%
ref
VCCA
FBEAD
VREF2
100nF 22uF
2.5V
VDDA_TV
VSSA_TV
RED
AGND
AGND
GND
FBEAD
FBEAD
100nF 22uF
VCCA
AGND
TSH74
15uH
To the connector
AGND
75 1%
47pF
AGND
GREEN
BLUE
526
1%
326
1%
478 1%
316 1%
AGND
same
as for
RED
CVBS
10
1%
10nF
AGND
3.3V
FBEAD
33
DCLK
27MHz
100nF
GND
GND
GND
R,G,B,CVBS outputs:
. Iout
= 80.704 / R < 5mA
Fine tuning of the maximum output level must be
done using the gain control registers 0x11 to 0x13
of the integrated Digital Encoder (write the value
0x0B for a gain of 109%).
max
ref
. R
= 274 ohms
load
. Vout = {10-bit code} x R
x 0.079 / R
ref
load
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6.3.11. JTAG INTERFACE
device needed are the pull up resistors. Figure 6-
16 describes a typical implementation using these
devices.
The STPC integrates a JTAG interface for scan-
chain and on-board testing. The only external
Figure 6-16. Typical JTAG implementation
3V3
3V3
3V3
3V3
Connector
10
8
9
7
5
3
1
TCLK
TDO
6
4
TMS
TDI
2
TRST
STPC
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All clock signals have to be routed first and
shielded for speeds of 27MHz or higher. The high
speed signals follow the same constraints, as for
the memory and PCI control signals.
6.4. PLACE AND ROUTE
RECOMMENDATIONS
6.4.1. GENERAL RECOMMENDATIONS
The next interfaces to be routed are Memory, PCI,
and Video/graphics.
Some STPC Interfaces run at high speed and
need to be carefully routed or even shielded like:
All the analog noise-sensitive signals have to be
routed in a separate area and hence can be
routed indepedently.
1) Memory Interface
2) PCI bus
3) Graphics and video interfaces
4) 14 MHz oscillator stage
Figure 6-17. Shielding signals
ground ring
shielded signal line
ground pad
ground pad
shielded signal lines
6.4.2. PLL DEFINITION AND IMPLIMENTATION
or one wire for each, or any solution in between
which help the layout of the board can be used.
PLLs are analog cells which supply the internal
STPC Clocks. To get the cleanest clock, the jitter
on the power supply must be reduced as much as
possible. This will result in a more stable system.
Powering these pins with one Ferrite
+
capacitances is enough. We recommend at least
2 capacitances: one 'big' (few uF) for power
storage, and one or 2 smalls (100nF + 1nF) for
noise filtering.
Each of the integrated PLL has a dedicated power
pin so a single power plane for all of these PLLs,
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6.4.3. MEMORY INTERFACE
6.4.3.1. Introduction
DIMM PCB is no longer present but it is then up to
the user to verify the timings.
6.4.3.2. SDRAM Clocking Scheme
In order to achieve SDRAM memory interfaces
which work at clock frequencies of 100 MHz and
above, careful consideration has to be given to the
timing of the interface with all the various electrical
and physical constraints taken into consideration.
The guidelines described below are related to
SDRAM components on DIMM modules. For
applications where the memories are directly
soldered to the motherboard, the PCB should be
laid out such that the trace lengths fit within the
constraints shown here. The traces could be
slightly shorter since the extra routing on the
The SDRAM Clocking Scheme deserves a special
mention here. Basically the memory clock is
generated on-chip through a PLL and goes
directly to the MCLKO output pin of the STPC. The
nominal frequency is 100 MHz. Because of the
high load presented to the MCLK on the board by
the DIMMs it is recommended to rebuffer the
MCLKO signal on the board and balance the skew
to the clock ports of the different DIMMs and the
MCLKI input pin of STPC.
Figure 6-18. Clock Scheme
MCLKO
MCLKI
PLL
PLL
MA[ ] + Control
MD[63:0]
SDRAM
CONTROLLER
6.4.3.3. Board Layout Issues
and ground planes to provide a low impedance
path between the planes for the return paths for
signal routings which change layers. If possible,
the traces should be routed adjacent to the same
power or ground plane for the length of the trace.
The physical layout of the motherboard PCB
assumed in this presentation is as shown in Figure
6-19. Because all of the memory interface signal
balls are located in the same region of the STPC
device, it is possible to orientate the device to
reduce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100 mm.
For the SDRAM interface, the most critical signal
is the clock. Any skew between the clocks at the
SDRAM components and the memory controller
will impact the timing budget. In order to get well
matched clocks at all components it is
recommended that all the DIMM clock pins, STPC
Solid power and ground planes are a must in order
to provide good return paths for the signals and to
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power
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Figure 6-19. DIMM placement
35mm
STPC
35mm
15mm
SDRAM I/F
DIMM2
DIMM1
10mm
116mm
memory clock input (MCLKI) and any other
component using the memory clock are
individually driven from a low skew clock driver
with matched routing lengths. In other words, all
clock line lengths that go from the buffer to the
memory chips (MCLKx) and from the buffer to the
STPC (MCLKI) must be identical.
This is shown in Figure 6-20.
Figure 6-20. Clock Routing
L
Low skew clock driver:
MCLKO
DIMM CKn input
DIMM CKn input
DIMM CKn input
STPC MCLKI
L+75mm*
20pF
* No additional 75mm when SDRAM directly soldered on board
The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew
between the outputs. The delay through the buffer
is not important so it does not have to be a zero
delay PLL type buffer. The trace lengths from the
clock driver to the DIMM CKn pins should be
matched exactly. Since the propagation speed
can vary between PCB layers, the clocks should
be routed in a consistent way. The routing to the
STPC memory input should be longer by 75 mm to
compensate for the extra clock routing on the
DIMM. Also a 20 pF capacitor should be placed as
near as possible to the clock input of the STPC to
compensate for the DIMM’s higher clock load. The
impedance of the trace used for the clock routing
should be matched to the DIMM clock trace
impedance (60-75 ohms)
To minimise crosstalk
.
the clocks should be routed with spacing to
adjacent tracks of at least twice the clock trace
width. For designs which use SDRAMs directly
mounted on the motherboard PCB all the clock
trace lengths should be matched exactly.
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DESIGN GUIDELINES
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single-row and dual-row. The dual-row devices
require two chip select signals to select between
the two rows. A STPC device with 4 chip select
control lines could control either 4 single-row
DIMMs or 2 dual-row DIMMs. When only 2 chip
select control lines are activated, only two single-
row DIMMs or one dual-row DIMM can be
controlled.
When using DIMM modules, schematics have to
be done carefully in order to avoid data buses
completely crossing on the board. This has to be
checked at the library level. In order to achieve the
layout shown in Figure 6-21, schematics have to
implement the crossing described in Figure 6-22.
The DQM signals must be exchanged using the
same order.
Figure 6-21. Optimum Data Bus Layout for DIMM
STPC
MD[31:00]
MD[63:32]
SDRAM I/F
D[15:00]
D[47:32]
D[31:16]
D[63:48]
DIMM
Figure 6-22. Schematics for Optimum Data Bus Layout for DIMM
STPC
MD[15:00],DQM[1:0]
DIMM
D[15:00],DQM[1:0]
D[31:16],DQM[3:2]
D[47:32],DQM[5:4]
D[63:48],DQM[7:6]
MD[31:16],DQM[3:2]
MD[47:32],DQM[5:4]
MD[63:48],DQM[7:6]
6.4.3.4. Summary
for the other signals but if their timing is not as
critical as the address/control signals they could
use the default value. Using a lower impedance
implies using wider traces which may have an
impact on the routing of the board.
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For
applications where speed is not so critical series
termination can be used as this will save power.
The layout of this interface can be validated by an
electrical simulation using the IBIS model
available on the STPC web site.
Ω
Using a low impedance such as 50 for these
critical traces is recommended as it both reduces
the delay and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals.
Using lower impedance traces is also beneficial
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6.4.4. PCI INTERFACE
6.4.4.1. Introduction
6.4.4.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
In order to achieve a PCI interface which work at
clock frequencies up to 33MHz, careful
consideration has to be given to the timing of the
interface with all the various electrical and
physical constraints taken into consideration.
some additionnal constraints on T and T .
0
1
Figure 6-23. Clock Scheme
HCLK
HCLK PLL
T
0
1
PCICLKO
1/2
1/3
1/4
clock
delay
T
2
MD[30:27]
MD[17,4]
T
Strap Options
MD[7:6]
PCICLKI
AD[31:0]
Deskewer
South
Bridge
MUX
North
Bridge
STPC
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DESIGN GUIDELINES
6.4.4.3. Board Layout Issues
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
The physical layout of the motherboard PCB
assumed in this presentation is as shown in Figure
6-24. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
The figure below is for PCI devices soldered on-
board. In the case of a PCI slot, the wire length
must be shortened by 2.5" to compensate the
clock layout on the PCI board. The maximum
clock skew between all devices is 2ns according
to PCI specifications.
Figure 6-24. Typical PCI clock routing
Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}
PCICLKI
PCICLKA
Device A
PCICLKB
Device B
PCICLKO
PCICLKC
Device C
Note: The value of 22 Ohms corresponds to tracks with Z = 70 Ohms.
0
The Figure 6-25 describes a typical clock delay
implementation. The exact timing constraints are
listed in the PCI section of the Electrical
Specifications Chapter.
Figure 6-25. Clocks relationships
HCLK
PCICLKO
PCICLKI
PCICLKx
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6.4.5. THERMAL DISSIPATION
6.4.5.1. Power saving
With such configuration the Plastic BGA package
does 90% of the thermal dissipation through the
ground balls, and especially the central thermal
balls which are directly connected to the die. The
remaining 10% is dissipated through the case.
Adding a heat sink reduces this value to 85%.
Thermal dissipation of the STPC depends mainly
on supply voltage. When the system does not
need to work at the upper voltage limit, it may
therefore be beneficial to reduce the voltage to the
lower voltage limit, where possible. This could
save a few 100’s of mW.
As a result, some basic rules must be followed
when routing the STPC in order to avoid thermal
problems.
As the whole ground layer acts as a heat sink, the
ground balls must be directly connected to it, as
illustrated in Figure 6-26. If one ground layer is not
enough, a second ground plane may be added.
The second area to look at is unused interfaces
and functions. Depending on the application,
some input signals can be grounded, and some
blocks not powered or shutdown. Clock speed
dynamic adjustment is also a solution that can be
used along with the integrated power
management unit.
When possible, it is important to avoid other
devices on-board using the PCB for heat
dissipation, like linear regulators, as this would
heat the STPC itself and reduce the temperature
range of the whole system, In case these devices
can not use a separate heat sink, they must not be
located just near the STPC
6.4.5.2. Thermal balls
The standard way to route thermal balls to ground
layer implements only one via pad for each ball
pad, connected using a 8-mil wire.
Figure 6-26. Ground routing
Pad for ground ball
Thru hole to ground layer
Note: For better visibility, ground balls are not all routed.
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DESIGN GUIDELINES
When considering thermal dissipation, one of the
most important parts of the layout is the
connection between the ground balls and the
ground layer.
A 1-wire connection is shown in Figure 6-27. The
use of a 8-mil wire results in a thermal resistance
of 105°C/W assuming copper is used (418 W/
m.°K). This high value is due to the thickness (34
µm) of the copper on the external side of the PCB.
Figure 6-27. Recommended 1-wire Power/Ground Pad Layout
Pad for ground ball (diameter = 25 mil)
Solder Mask (4 mil)
Connection Wire (width = 12.5 mil)
Via (diameter = 24 mil)
Hole to ground layer (diameter = 12 mil)
1 mil = 0.0254 mm
Considering only the central matrix of 36 thermal
balls and one via for each ball, the global thermal
resistance is 2.9°C/W. This can be easily
improved using four 12.5 mil wires to connect to
the four vias around the ground pad link as in
Figure 6-28. This gives a total of 49 vias and a
global resistance for the 36 thermal balls of 0.5°C/
W.
Figure 6-28. Recommended 4-wire Ground Pad Layout
4 via pads for each ground ball
The use of a ground plane like in Figure 6-29 is
even better.
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DESIGN GUIDELINES
To avoid solder wicking over to the via pads during
soldering, it is important to have a solder mask of
4 mil around the pad (NSMD pad). This gives a
diameter of 33 mil for a 25 mil ground pad.
To obtain the optimum ground layout, place the
vias directly under the ball pads. In this case no
local board distortion is tolerated.
Figure 6-29. Optimum Layout for Central Ground Ball - top layer
Clearance = 6mil
External diameter = 37 mil
Via to Ground layer
hole diameter = 14 mil
Solder mask
diameter = 33 mil
Pad for ground ball
diameter = 25 mil
connections = 10 mil
6.4.5.3. Heat dissipation
heat and hence the thermal dissipation of the
board.
The thickness of the copper on PCB layers is
typically 34 µm for external layers and 17 µm for
internal layers. This means that thermal
dissipation is not good; high board temperatures
are concentrated around the devices and these
fall quickly with increased distance.
The possibility of using the whole system box for
thermal dissipation is very useful in cases of high
internal
temperatures
and
low
outside
temperatures. Bottom side of the PBGA should be
thermally connected to the metal chassis in order
to propagate the heat flow through the metal.
Thermally connecting also the top side will
improve furthermore the heat dissipation. Figure
6-30 illustrates such an implementation.
Where possible, place a metal layer inside the
PCB; this improves dramatically the spread of
Figure 6-30. Use of Metal Plate for Thermal Dissipation
Die
Board
Metal planes
Thermal conductor
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DESIGN GUIDELINES
As the PCB acts as a heat sink, the layout of top
and ground layers must be done with care to
maximize the board surface dissipating the heat.
The only limitation is the risk of losing routing
channels. Figure 6-31 and Figure 6-32 show a
routing with a good thermal dissipation thanks to
an optimized placement of power and signal vias.
The ground plane should be on bottom layer for
the best heat spreading (thicker layer than internal
ones) and dissipation (direct contact with air). .
Figure 6-31. Layout for Good Thermal Dissipation - top layer
1
A
STPC ball
Via
GND ball
3.3V ball
Not Connected ball
2.5V ball (Core / PLLs)
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DESIGN GUIDELINES
Figure 6-32. Recommend signal wiring (top & ground layers) with corresponding heat flow
GND
Power
Power
Internal row
STPC balls
External row
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DESIGN GUIDELINES
6.5. DEBUG METHODOLOGY
must not be more than 100MHz. In x2 CPU clock
mode, this clock must be limited to 66MHz.
In order to bring a STPC-based board to life with
the best efficiency, it is recommended to follow the
check-list described in this section.
PCI_CLKI and PCI_CLKO must be connected as
described in Figure 6-19 and not be higher than
33MHz. Their speed depends on HCLK and on
MD[4] and MD[17]
the divider ratio defined by the
6.5.1. POWER SUPPLIES
strap options as described in Section 3.
To ensure a correct behaviour of the device, the
PCI deskewing logic must be configured properly
by the MD[7:6] strap options according to Section
3. For timings constraints, refers to Section 4.
In parallel with the assembly process, it is useful to
get a bare PCB to check the potential short-
circuits between the various power and ground
planes. This test is also recommended when the
first boards are back from assembly. This will
avoid bad surprises in case of a short-circuit due
to a bad soldering.
MCLKI and MCLKO must be connected as
described in Figure 6-3 to Figure 6-5 depending
on the SDRAM implementation. The memory
clock must run at HCLK speed when in
synchronous mode and must not be higher than
100MHz in any case.
When the system is powered, all power supplies,
including the PLL power pins must be checked to
be sure the right level is present. See Table 4-2 for
the exact supported voltage range:
6.5.2.4. Reset output
VDD_CORE: 2.5V
VDD_xxxPLL: 2.5V
VDD: 3.3V
If SYSRSTI# and all clocks are correct, then the
SYSRSTO# output signal should behave as
described in Figure 4-3
.
6.5.2. BOOT SEQUENCE
6.5.2.1. Reset input
6.5.3. ISA MODE
Prior to check the ISA bus control signals,
PCI_CLKI, ISA_CLK, ISA_CLK2X, and DEV_CLK
must be running properly. If it is not the case, it is
probably because one of the previous steps has
not been completed.
The checking of the reset sequence is the next
step. The waveform of SYSRSTI# must complies
with the timings described in Figure 4-3. This
signal must not have glitches and must stay low
until the 14.31818MHz output (OSC14M) is at the
right frequency and the strap options are
stabilized to a valid configuration.
6.5.3.1. First code fetches
When booting on the ISA bus, the two key signals
to check at the very beginning are RMRTCCS#
and FRAME#.
In case this clock is not present, check the 14MHz
oscillator stage (see Figure 6-3).
The first one is a Chip Select for the boot flash
and is multiplexed with the IDE interface. It should
toggle together with ISAOE# and MEMRD# to
fetch the first 16 bytes of code. This corresponds
to the loading of the first line of the CPU cache.
6.5.2.2. Strap options
The STPC has been designed in a way to allow
configurations for test purpose that differs from the
functional configuration. In many cases, the
troubleshootings at this stage of the debug are the
resulting of bad strap options. This is why it is
mandatory to check they are properly setup and
sampled during the boot sequence.
In case RMRTCCS# does not toggle, it is then
necessary to check the PCI FRAME# signal.
Indeed the ISA controller is part of the South
Bridge and all ISA bus cycles are visible on the
PCI bus.
The list of all the strap options is summarized at
the beginning of Section 3.
If there is no activity on the PCI bus, then one of
the previous steps has not been checked properly.
If there is activity then there must be something
conflicting on the ISA bus or on the PCI bus.
6.5.2.3. Clocks
Once OSC14M is checked and correct, the next
signals to measure are the Host clock (HCLK),
PCI clocks (PCI_CLKO, PCI_CLKI) and Memory
clock (MCLKO, MCLKI).
6.5.3.2. Boot Flash size
The ISA bus supports 8-bit and 16-bit memory
devices. In case of a 16-bit boot flash, the signal
HCLK must run at the speed defined by the
corresponding strap options (see Table 3-1) and
MEMCS16#
must
be
activated
during
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DESIGN GUIDELINES
RMRTCCS# cycle to inform the ISA controller of a
16-bit device.
6.5.4.1. First code fetches
When booting on the Local Bus, the key signal to
check at the very beginning is FCS0#. This signal
is a Chip Select for the boot flash and should
toggle together with PRD# to fetch the first 16
bytes of code. This corresponds to the loading of
the first line of the CPU cache.
In case FCS0# does not toggle, then one of the
previous steps has not been done properly, like
HCLK speed and CPU clock multiplier (x1, x2).
6.5.3.3. POST code
Once the 16 first bytes are fetched and decoded,
the CPU core continue its execution depending on
the content of these first data. Usually, it
corresponds to a JUMP instruction and the code
fetching continues, generating read cycles on the
ISA bus.
Most of the BIOS and boot loaders are reading the
content of the flash, decompressing it in SDRAM,
and then continue the execution by jumping to the
entry point in RAM. This boot process ends with a
JUMP to the entry point of the OS launcher.
These various steps of the booting sequence are
codified by the so-called POST codes (Power-On
Self-Test). A 8-bit code is written to the port 80H at
the beginning of each stage of the booting process
(I/O write to address 0080H) and can be displayed
on two 7-segment display, enabling a fast visual
check of the booting completion level.
6.5.4.2. Boot Flash size
The Local Bus support 16-bit boot memory
devices only.
6.5.4.3. POST code
Like in ISA mode, POST codes can be
implemented on the Local Bus. The difference is
that an IOCS# must be programmed at I/O
address 80H prior to writing these code, the POST
display being connected to this IOCS# and to the
lower 8 bits of the bus.
Usually, the last POST code is 0x00 and
corresponds to the jump into the OS launcher.
6.5.5. SUMMARY
When the execution fails or hangs, the lastest
written code stays visible on that display,
indicating either the piece of code to analyse,
either the area of the hardware not working
properly.
Here is a check-list for the STPC board debug
from power-on to CPU execution.
For each step, in case of failure, verify first the
corresponding balls of the STPC:
- check if the voltage or activity is correct
- search for potential shortcuts.
For troubleshooting in steps 5 to 10, verify the
related strap options:
- value & connection. Refer to Section 3.
- see Figure 4-3 for timing constraints
6.5.4. LOCAL BUS MODE
As the Local Bus controller is located into the Host
interface, there is no access to the cycles on the
PCI, reducing the amount of signals to check.
Steps 8a and 9a are for debug in ISA mode while
steps 8b and 9b are for Local Bus mode.
Check:
How?
Troubleshooting
Verify that voltage is within specs:
- this must include HF & LF noise
- avoid full range sweep
Measure voltage near STPC balls:
- use very low GND connection.
Add some decoupling capacitor:
- the smallest, the nearest to STPC balls.
Power
supplies
1
2
Refer to Table 4-1 for values
The 2 capacitors used with the quartz must
match with the capacitance of the crystal.
Try other values.
14.318 MHz
Verify OSC14M speed
Verify reset generation circuit:
- device reference
- components value
Measure SYSRSTI# of STPC
SYSRSTI#
(Power Good)
3
5
See
for waveforms.
Figure 4-3
Measure HCLK is at selected frequency
25MHz < HCLK < 100MHz
HCLK
HCLK wire must be as short as possible
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DESIGN GUIDELINES
Check:
How?
Measure PCICLKO:
Troubleshooting
Verify PCICLKO loops to PCICLKI.
Verify maximum skew between any PCI clock
branch is below 2ns.
- maximum is 33MHz by standard
- check it is at selected frequency
- it is generated from HCLK by a division
(1/2, 1/3 or 1/4)
6
PCI clocks
In Synchronous mode, check MCLKI.
Check PCICLKI equals PCICLKO
Measure MCLKO:
- use a low-capacitance probe
- maximum is 100MHz
- check it is at selected frequency
- In SYNC mode MCLK=HCLK
- in ASYNC mode, default is 66MHz
Check MCLKI equals MCLKO
Verify load on MCLKI.
Verify MCLK programming (BIOS setting).
Memory
clocks
7
4
Verify SYSRSTI# duration.
Verify SYSRSTI# has no glitch
Verify clocks are running.
Measure SYSRSTO# of STPC
SYSRSTO#
PCI cycles
See
for waveforms.
Figure 4-3
Check PCI signals are toggling:
Verify PCI slots
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
- FRAME#, IRDY#, TRDY#, DEVSEL#
- these signals are active low.
Check, with a logic analyzer, that first
PCI cycles are the expected ones:
memory read starting at address with
lower bits to 0xFFF0
8a
Verify MEMCS16#:
- must not be asserted for 8-bit memory
Verify IOCHRDY is not be asserted
ISA
cycles
to
Check RMRTCCS# & MEMRD#
Check directly on boot memory pin
9a
Verify ISAOE# pin:
- it controls IDE / ISA bus demultiplexing
boot memory
Check FCS0# & PRD#
Check directly on boot memory pin
8b
9b
Verify HCLK speed and CPU clock mode.
Local Bus
cycles
Check, with a logic analyzer, that first
Local Bus cycles are the expected one:
memory read starting at the top of boot
memory less 16 bytes
If the STPC don’t boot
to
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
boot memory
The CPU fills its first cache line by fetching 16 bytes from boot memory.
Then, first instructions are executed from the CPU.
10
Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU
=> Minimum hardware is correctly set, CPU executes code.
Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.
6.6.
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ORDERING DATA
7. ORDERING DATA
7.1. ORDERING CODES
ST
PC
C4
E
E
B
C
STMicroelectronics
Prefix
Product Family
PC: PC Compatible
Product ID
C4: Consumer-II
Core Speed
E: 100 MHz
H: 133 MHz
Memory Interface Speed
D: 90 MHz
E: 100 MHz
Package
B: 388 Overmoulded BGA
Temperature Range
C: Commercial
Case Temperature (Tcase) = 0°C to +85°C
I: Industrial
Case Temperature (Tcase) = -40°C to +115°C
Release 1.5 - January 29, 2002
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ORDERING DATA
7.2. AVAILABLE PART NUMBERS
Core Frequency
CPU Mode
( X1 / X2 )
Interface
Speed (MHz)
Tcase Range
( °C )
Part Number
( MHz )
STPCC4HEBC
STPCC4HEBI
STPCC5HEBC
STPCC5HEBI
133
X2
X2
X2
X2
100
100
100
100
0°C to +85°
-40°C to +115°
0°C to +85°
133
133
133
-40°C to +115°
7.3. CUSTOMER SERVICE
More
STMicroelectronics
www.st.com/stpc
information
is
available
on
the
http://
Internet
site
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Release 1.5 - January 29, 2002
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
© 2000 STMicroelectronics - All Rights Reserved
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
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93
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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