STPCATLAS_技术文档

®

STPC ATLAS

X86 Core PC Compatible System-on-Chip for Terminals

■

POWERFUL x86 PROCESSOR

64-BIT SDRAM UMA CONTROLLER

GRAPHICS CONTROLLER

- VGA & SVGA CRT CONTROLLER

- 135MHz RAMDAC

- ENHANCED 2D GRAPHICS ENGINE

■

VIDEO INPUT PORT

VIDEO PIPELINE

- UP-SCALER

- VIDEO COLOUR SPACE CONVERTER

- CHROMA & COLOUR KEY SUPPORT

PBGA516

■

TFT DISPLAY CONTROLLER

PCI 2.1 MASTER / SLAVE / ARBITER

ISA MASTER / SLAVE CONTROLLER

16-BIT LOCAL BUS INTERFACE

PCMCIA INTERFACE CONTROLLER

EIDE CONTROLLER

Figure 0-1. Logic Diagram

Host x86

Core

USB

I/Os

I/F

PCI

m/s

PCI Bus

2 USB HOST HUB INTERFACES

PMU

wdog

I/O FEATURES

- PC/AT+ KEYBOARD CONTROLLER

- PS/2 MOUSE CONTROLLER

- 2 SERIAL PORTS

ISA

m/s

PCI

m/s

IDE

I/F

IPC

ISA Bus

- 1 PARALLEL PORT

- 16 GENERAL PURPOSE I/Os

- I²C INTERFACE

PCMCIA

LB

ctrl

Local Bus

■

INTEGRATED PERIPHERAL CONTROLLER

- DMA CONTROLLER

- INTERRUPT CONTROLLER

- TIMER / COUNTERS

Video

Pipeline

C Key

K Key

LUT

Monitor

■

POWER MANAGEMENT UNIT

WATCHDOG

SVGA

CRTC

Cursor

TFT

JTAG IEEE1149.1

TFT I/F

GE I/F

VIP

Video In

SDRAM

CTRL

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1/111

®

STPC ATLAS

DESCRIPTION

■

Enhanced 2D Graphics Controller

Supports pixel depths of 8, 16, 24 and 32 bit.

Full BitBLT implementation for all 256 raster

operations defined for Windows.

Supports 4 transparent BLT modes - Bitmap

Transparency, Pattern Transparency, Source

Transparency and Destination Transparency.

Hardware clipping

The STPC Atlas integrates a standard 5th

generation x86 core along with a powerful UMA

graphics/video chipset, support logic including

PCI, ISA, Local Bus, USB, EIDE controllers and

combines them with standard I/O interfaces to

provide a single PC compatible subsystem on a

single device, suitable for all kinds of terminal and

industrial appliances.

■

X86 Processor core

Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

Fast line draw engine with anti-aliasing.

Supports 4-bit alpha blended font for anti-

aliased text display.

■

Can access up to 4GB of external memory.

8Kbyte unified instruction and data cache

with write back and write through capability.

Parallel processing integral floating point unit,

with automatic power down.

Complete double buffered registers for

pipelined operation.

64-bit wide pipelined architecture running at

90 MHz. Hardware clipping

■

CRT Controller

Runs up to 133 MHz (X2).

Fully static design for dynamic clock control.

Low power and system management modes.

Optimized design for 2.5V operation.

Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

8-, 16-, 24-bit pixels.

■

Interlaced or non-interlaced output.

■

SDRAM Controller

64-bit data bus.

■

Video Input port

Accepts video inputs in CCIR 601/656 mode.

Optional 2:1 decimator

Stores captured video in off setting area of

the onboard frame buffer.

HSYNC and B/T generation or lock onto

external video timing source.

Up to 90MHz SDRAM clock speed.

Integrated system memory, graphic frame

memory and video frame memory.

Supports 8MB up to 128 MB system memory.

Supports 16-Mbit, 64-Mbit and 128-Mbit

SDRAMs.

■

Supports 8, 16, 32, 64, and 128 MB DIMMs.

Supports buffered, non buffered, and

registered DIMMs

4-line write buffers for CPU to DRAM and PCI

to DRAM cycles.

4-line read prefetch buffers for PCI masters.

Programmable latency

Programmable timing for SDRAM

parameters.

■

Video Pipeline

Two-tap interpolative horizontal filter.

Two-tap interpolative vertical filter.

Color space conversion (RGB to YUV and

YUV to RGB).

Programmable window size.

Chroma and color keying for integrated video

overlay.

■

Supports -8, -10, -12, -13, -15 memory parts

Supports memory hole between 1MB and

8MB for PCI/ISA busses.

■

32-bit access, Autoprecharge & Power-down

are not supported.

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Issue 1.0 - July 24, 2002

®

STPC ATLAS

■

TFT Interface

■

Local Bus interface

Multiplexed with ISA/DMA interface.

Low latency asynchronous bus

16-bit data bus with word steering capability.

Programmable timing (Host clock granularity)

4 Programmable Flash Chip Select.

8 Programmable I/O Chip Select.

I/O device timing (setup & recovery time)

programmable

Programmable panel size up to 1024 by 1024

pixels.

Support for VGA and SVGA active matrix

TFT flat panels with 9, 12, 18-bit interface (1

pixel per clock).

Support for XGA and SXGA active matrix

TFT flat panels with 2 x 9-bit interface (2

pixels per clock).

■

Supports 32-bit Flash burst.

2-level hardware key protection for Flash boot

block protection.

■

Programmable image positionning.

Programmable blank space insertion in text

mode.

■

Supports 2 banks of 32MB flash devices with

boot block shadowed to 0x000F0000.

Reallocatable Memory space Windows

■

Programmable horizontal and vertical image

expansion in graphic mode.

One fully programmable PWM (Pulse Width

Modulator) signals to adjust the flat panel

■

EIDE Interface

Supports PIO

brightness and contrast.

Supports PanelLink

transmitter externally for high resolution

panel interface.

TM

■

high speed serial

Transfer Rates to 22 MBytes/sec

Supports up to 4 IDE devices

Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

Support for PIO mode 3 & 4.

Individual drive timing for all four IDE devices

Supports both legacy & native IDE modes

Supports hard drives larger than 528MB

Support for CD-ROM and tape peripherals

Backward compatibility with IDE (ATA-1).

■

PCI Controller

■

Compatible with PCI 2.1 specification.

Integrated PCI arbitration interface. Up to 3

masters can connect directly. External logic

allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to

PCI.

■

Integrated Peripheral Controller

2X8237/AT compatible 7-channel DMA

controller.

■

Support for burst read/write from PCI master.

PCI clock is 1/2, 1/3 or 1/4 Host bus clock.

■

2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

Supports external RTC (Not in Local Bus

Mode).

■

ISA master/slave

Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

Supports programmable extra wait state for

ISA cycles

Supports I/O recovery time for back to back

I/O cycles.

■

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

Supports flash ROM.

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host

bus.

■

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®

STPC ATLAS

■

PCMCIA interface

Parallel port

■

All IEEE Standard 1284 protocols supported:

Compatibility, Nibble, Byte, EPP, and ECP

modes.

Support one PCMCIA 68-pin standard PC

Card Socket.

Power Management support.

Support PCMCIA/ATA specifications.

Support I/O PC Card with pulse-mode

interrupts.

■

16 bytes FIFO for ECP.

■

Power Management

Four power saving modes: On, Doze,

Standby, Suspend.

Programmable system activity detector

Supports Intel & Cyrix SMM and APM.

Supports STOPCLK.

■

USB Interface

USB 1.1 compatible.

Open HCI 1.0 compliant.

User configurable RootHub.

Support for both LowSpeed and HighSpeed

USB devices.

No bi-directionnal or Tri-state busses.

No level sensitive latches.

System Management Interrupt pin support

Hooks for legacy device support.

■

Supports IO trap & restart.

Independent peripheral time-out timer to

monitor hard disk, serial & parallel port.

128K SM_RAM address space from

0xA0000 to 0xB0000

■

JTAG

■

Keyboard interface

Boundary Scan compatible IEEE1149.1.

Scan Chain control.

Bypass register compatible IEEE1149.1.

ID register compatible IEEE1149.1.

RAM BIST control.

Fully PC/AT+ compatible

■

Mouse interface

Fully PS/2 compatible

■

Serial interface

■

15540 compatible

Programmable word length, stop bits, parity.

16-bit programmable baud rate generator.

Interrupt generator.

Loop-back mode.

8-bit scratch register.

Two 16-bit FIFOs.

Two DMA handshake lines.

.

ExCA is a trademark of PCMCIA / JEIDA.

PanelLink is a trademark of SiliconImage, Inc

4/111

Issue 1.0 - July 24, 2002

GENERAL DESCRIPTION

1. GENERAL DESCRIPTION

At the heart of the STPC Atlas is an advanced

processor block that includes a powerful x86

processor core along with a 64-bit SDRAM

controller, advanced 64-bit accelerated graphics

and video controller, a high speed PCI bus

controller and industry standard PC chip set

functions (Interrupt controller, DMA Controller,

Interval timer and ISA bus).

1.2. GRAPHICS FEATURES

Graphics functions are controlled through the on-

chip SVGA controller and the monitor display is

produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the

host CPU to provide a balanced graphics system

with a low silicon area cost. It performs limited

graphics drawing operations which include

hardware acceleration of text, bitblts, transparent

blts and fills. The results of these operations

change the contents of the on-screen or off-

screen frame buffer areas of SDRAM memory.

The frame buffer can occupy a space up to 4

Mbytes anywhere in the physical main memory.

The STPC Atlas has in addition, a TFT output, a

Video Input, an EIDE controller, a Local Bus

interface, PCMCIA and super I/O features

including USB host hub.

1.1. ARCHITECTURE

The STPC Atlas makes use of a tightly coupled

Unified Memory Architecture (UMA), where the

same memory array is used for CPU main

memory and graphics frame-buffer. This means a

reduction in total system memory for system

performances that are equal to that of a

comparable frame buffer and system memory

based system, and generally much better, due to

the higher memory bandwidth allowed by

attaching the graphics engine directly to the 64-bit

processor host interface running at the speed of

the processor bus rather than the traditional PCI

bus.

The maximum graphics resolution supported is

1280 x 1024 in 16 Million colours at 75 Hz refresh

rate and is VGA and SVGA compatible. Horizontal

timing fields are VGA compatible while the vertical

fields are extended by one bit to accommodate

above display resolution.

To generate the TFT output, the STPC Atlas

extracts the digital video stream before the

RAMDAC and reformats it to the TFT format. The

height and width of the flat panel are

programmable.

The 64-bit wide memory array provides the

system with an 800MB/s peak bandwidth. This

allows for higher resolution screens and greater

color depth. The processor bus runs at 133 MHz,

further increasing “standard” bandwidth by at least

a factor of two.

1.3. INTERFACES

An industry standard EIDE (ATA 2) controller is

built in to the STPC Atlas and connected internally

via the PCI bus.

The STPC Atlas integrates two USB ports.

Universal Serial Bus (USB) is a general purpose

communications

The ‘standard’ PC chipset functions (DMA,

interrupt controller, timers, power management

logic) are integrated together with the x86

processor core; additional low bandwidth

functions such as communication ports are

accessed by the STPC Atlas via an internal ISA

bus.

interface

for

connecting

peripherals to a PC. The USB Open Host

Controller Interface (Open HCI) Specification,

revision 1.1, supports speeds of up to 12 MB/s.

USB is royalty free and is likely to replace low-

speed legacy serial, parallel, keyboard, mouse

and floppy drive interfaces. USB Revision 1.1 is

fully supported under Microsoft Windows 98 and

Windows 2000.

The PCI bus is the main data communication link

to the STPC Atlas chip. The STPC Atlas translates

appropriate host bus I/O and Memory cycles onto

the PCI bus. It also supports the generation of

Configuration cycles on the PCI bus. The STPC

Atlas, as a PCI bus agent (host bridge class), is

compatible with PCI specification 2.1. The chip-

set also implements the PCI mandatory header

registers in Type 0 PCI configuration space for

easy porting of PCI aware system BIOS. The

device contains a PCI arbitration function for three

external PCI devices.

The STPC Atlas PCMCIA controller has been

specifically designed to provide the interface with

PCMCIA cards which contain additional memory

or I/O

The power management control facilities include

socket power control, insertion/removal capability,

power saving with Windows inactivity, NCS

controlled Chip Power Down, together with further

controls for 3.3V suspend with Modem Ring

Resume Detection.

Figure 1-1 describes this architecture.

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GENERAL DESCRIPTION

The STPC Atlas implements a multi-function

parallel port. The standard PC/AT compatible

logical address assignments for LPT1, LPT2 and

LPT3 are supported. It can be configured for any

of the following three modes and supports the

IEEE Standard 1284 parallel interface protocol

standards, as follows:

- Compatibility Mode (Forward channel, standard)

- Nibble Mode (Reverse channel, PC compatible)

- Byte Mode (Reverse channel, PS/2 compatible)

- House-keeping activity detection.

- House-keeping timer to cope with short bursts of

house-keeping activity while dozing or in stand-by

state.

- Peripheral activity detection.

- Peripheral timer detecting peripheral inactivity

- SUSP# modulation to adjust the system

performance in various power down states of the

system including full power-on state.

The General Purpose Input/Output (GPIO)

interface provides a 16-bit I/O facility, using 16

dedicated device pins. It is organised using two

blocks of 8-bit Registers, one for lines 0 to 7, the

other for lines 8 to 15.

Each GPIO port can be configured as an input or

an output simply by programming the associated

port direction control register. All GPIO ports are

configured as inputs at reset, which also latches

the input levels into the Strap Registers. The input

states of the ports are thus recorded automati-

cally at reset, and this can be used as a strap

register anywhere in the system.

- Power control outputs to disable power from

different planes of the board.

Lack of system activity for progressively longer

periods of time is detected by the three power

down timers. These timers can generate SMI

interrupts to CPU so that the SMM software can

put the system in decreasing states of power

consumption. Alternatively, system activity in a

power down state can generate an SMI interrupt

to allow the software to bring the system back up

to full power-on state. The chip-set supports up to

three power down states described above; these

correspond to decreasing levels of power savings.

1.4. FEATURE MULTIPLEXING

Power down puts the STPC Atlas into suspend

mode. The processor completes execution of the

current instruction, any pending decoded

instructions and associated bus cycles. During the

suspend mode, internal clocks are stopped.

Removing power-down, the processor resumes

instruction fetching and begins execution in the

instruction stream at the point it had stopped.

Because of the static nature of the core, no

internal data is lost.

The STPC Atlas BGA package has 516 balls. This

however is not sufficient for all of the integrated

functions available; some features therefore share

the same balls and cannot thus be used at the

same time. The STPC Atlas configuration is done

by ‘strap options’. This is a set of pull-up or pull-

down resistors on the memory data bus, checked

on reset, which auto-configure the STPC Atlas.

There 3 multiplexed functions are the external ISA

bus, the Local Bus and the PCMCIA interface.

1.6. JTAG

1.5. POWER MANAGEMENT

JTAG stands for Joint Test Action Group and is

the popular name for IEEE Std. 1149.1, Standard

Test Access Port and Boundary-Scan Architec-

ture. This built-in circuitry is used to assist in the

test, maintenance and support of functional circuit

blocks. The circuitry includes a standard interface

through which instructions and test data are

communicated. A set of test features is defined,

including a boundary-scan register so that a

component is able to respond to a minimum set of

test instructions.

The STPC Atlas core is compliant with the

Advanced

Power

Management

(APM)

specification to provide a standard method by

which the BIOS can control the power used by

personal computers. The Power Management

Unit (PMU) module

controls the power

consumption, providing a comprehensive set of

features that controls the power usage and

supports compliance with the United States

Environmental Protection Agency's Energy Star

Computer Program. The PMU provides the

following hardware structures to assist the

software in managing the system power

consumption:

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

- Doze timer (short durations).

- Stand-by timer (medium durations).

- Suspend timer (long durations).

6/111

Issue 1.0 - July 24, 2002

GENERAL DESCRIPTION

Figure 1-1. Functional description.

Host

I/F

x86

Core

USB

I/Os

PCI

m/s

PCI Bus

PMU

IDE

I/F

ISA

m/s

PCI

m/s

IPC

ISA Bus

PCMCIA

LB

CTRL

Local Bus

Video

Pipeline

C Key

K Key

LUT

Monitor

SVGA

CRTC

Cursor

TFT

TFT I/F

GE I/F

Video In

VIP

SDRAM

CTRL

JTAG

Issue 1.0 - July 24, 2002

7/111

GENERAL DESCRIPTION

1.7. CLOCK TREE

The speed of the PLLs is either fixed (DEVCLK),

either programmable by strap option (HCLK)

either programmable by software (DCLK, MCLK).

When in synchronized mode, MCLK speed is fixed

to HCLKO speed and HCLKI is generated from

MCLKI.

The STPC Atlas integrates many features and

generates all its clocks from a single 14MHz

oscillator. This results in multiple clock domains as

described in Figure 1-2.

Figure 1-2. STPC Atlas clock architecture

MCLKO

MCLKI

VCLK

DCLK

SDRAM controller

GE, LDE, AFE

VIP

CRTC,Video,TFT

HCLKO

48MHz DEVCLK

PLL

DCLK

PLL

MCLK

PLL

HCLK

PLL

HCLKI

CPU

ISA

x2

1/6

PCMCIA

IPC

UARTs

USB

1/26

North Bridge

Host

Kbd/Mouse

1/4

Local Bus

South Bridge

PWM

1/2

1/3

// Port

1/2

1/4

DEVCLK

(24MHz)

OSC14M ISACLK

(14MHz)

HCLK

PCICLKO

XTALO

XTALI

PCICLKI

14.31818 MHz

8/111

Issue 1.0 - July 24, 2002

GENERAL DESCRIPTION

Figure 1-3. Typical ISA-based Application.

RTC

5V tolerant

EIDE USB

Flash

Boot

ISA

ROMCS#

SVGA

IRQ

DMA.ACK

DMA.REQ

TFT

2 Serial Ports

Keyboard

Parallel Port

Mouse

STPC Atlas

VIP

16 GPIOs

PCI

SDRAM

Issue 1.0 - July 24, 2002

9/111

GENERAL DESCRIPTION

Figure 1-4. Typical PCMCIA-based Application.

5V tolerant

EIDE USB

Flash

Boot

PCMCIA

ROMCS#

SVGA

TFT

2 Serial Ports

Keyboard

Parallel Port

Mouse

STPC Atlas

VIP

16 GPIOs

PCI

SDRAM

10/111

Issue 1.0 - July 24, 2002

GENERAL DESCRIPTION

Figure 1-5. Typical Local-Bus-based Application.

RTC

EIDE USB

Flash

Boot

Local Bus

SVGA

IRQ

TFT

2 Serial Ports

Keyboard

Parallel Port

Mouse

STPC Atlas

VIP

16 GPIOs

PCI

SDRAM

Issue 1.0 - July 24, 2002

11/111

GENERAL DESCRIPTION

12/111

Issue 1.0 - July 24, 2002

PIN DESCRIPTION

2. PIN DESCRIPTION

disabled totally and Local Bus pins are set to the

tri-state (high-impedance) condition.

2.1. INTRODUCTION

The STPC Atlas integrates most of the

functionalities of the PC architecture. Therefore,

many of the traditional interconnections between

the host PC microprocessor and the peripheral

devices are totally internal to the STPC Atlas. This

offers improved performance due to the tight

coupling of the processor core and it’s peripherals.

As a result many of the external pin connections

are made directly to the on-chip peripheral

functions.

Signal Description

Table 2-1.

Group name

Basic Clocks, Reset & Xtal (SYS)

SDRAM Controller (SDRAM)

PCI Controller

Qty

19

95

51

ISA Controller

Local Bus I/F

PCMCIA Controller

IDE Controller

80

67

62

34

100

Table 2-1 describes the physical implementation

listing signal types and their functionalities. Table

2-2 provides a full pin listing and description.

2

VGA Controller (VGA) / I C

10

11

24

6

16

4

18

16

5

Video Input Port

TFT output

Table 2-6 provides a full listing of the STPC Atlas

package pin location physical connection. Please

refer to the pin allocation drawing for reference.

USB Controller

Serial Interface

Keyboard/Mouse Controller

Parallel Port

Due to the number of pins available for the

package, and the number of functional I/Os, some

pins have several functions, selectable by strap

option on Reset. Table 2-4 provides a summary of

these pins and their functions.

GPIO Signals

JTAG Signals

Miscellaneous

Grounds

5

96

36

4

Non multi-functional pins associated with a

particular function are not available for use

elsewhere when that function is disabled. For

example, when in the ISA mode, the Local Bus is

V

3.3 V/2.5 V

DD

Reserved

Total Pin Count

516

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13/111

PIN DESCRIPTION

Definition of Signal Pins

Table 2-2.

1

Signal Name

Dir

Buffer Type

Description

Qty

BASIC CLOCKS AND RESETS

SYSRSTI#

SYSRSTO#

I

SCHMITT_FT

System Reset / Power good

Reset Output to System

1

O BD8STRP_FT

14.31818 MHz Crystal Input

External Oscillator Input

XTALI

I

1

OSCI13B

XTALO

O

I

14.31818 MHz Crystal Output

33 MHz PCI Input Clock

33 MHz PCI Output Clock

ISA Clock x1 and x2

Multiplexer Select Line for IPC

ISA bus synchronisation clock

66 MHz Host Clock (Test pin)

24 MHz Peripheral Clock

135 MHz Dot Clock

1

PCI_CLKI

PCI_CLKO

ISA_CLK,

ISA_CLK2X

OSC14M

HCLK

TLCHT_FT

O BT8TRP_TC

2

O BD8STRP_FT

I/O BD4STRP_FT

O BT8TRP_TC

I/O BD4STRP_FT

1

7

DEV_CLK

DCLK

V

_xxx_PLL

2.5V Power Supply for PLL Clocks

DD

MEMORY CONTROLLER

MCLKI

MCLKO

CS#[1:0]

I

TLCHT_TC

Memory Clock Input

Memory Clock Output

DIMM Chip Select

1

2

O BT8TRP_TC

O BD8STRP_TC

CS#[3]/MA[12]/BA[1] O BD16STARUQP_TC Memory Address

1

Bank Address

DIMM Chip Select

Memory Address

CS#[2]/MA[11]

O BD16STARUQP_TC

1

MA[10:0]

BA[0]

O BD16STARUQP_TC Memory Row & Column Address

O BD16STARUQP_TC Bank Address

11

1

RAS#[1:0]

CAS#[1:0]

MWE#

O BD16STARUQP_TC Row Address Strobe

O BD16STARUQP_TC Column Address Strobe

O BD16STARUQP_TC Write Enable

2

1

MD[0]

I/O BD8STRUP_FT

I/O BD8TRP_TC

I/O BD8STRUP_FT

O BD8STRP_TC

Memory Data

Data Input/Ouput Mask

1

MD[53:1]

MD[63:54]

DQM[7:0]

53

10

8

PCI INTERFACE

AD[31:0]

CBE[3:0]

FRAME#

TRDY#

IRDY#

STOP#

DEVSEL#

PAR

PERR#

SERR#

LOCK#

PCI_REQ#[2:0]

PCI_GNT#[2:0]

PCI_INT#[3:0]

I/O BD8PCIARP_FT

O BD8PCIARP_FT

Address / Data

Bus Commands / Byte Enables

Cycle Frame

32

4

1

3

4

Target Ready

Initiator Ready

Stop Transaction

Device Select

Parity Signal Transactions

Parity Error

System Error

PCI Lock

PCI Request

PCI Grant

I

TLCHT_FT

BD8PCIARP_FT

O BD8PCIARP_FT

BD4STRUP_FT

I

PCI Interrupt Request

1

Note ; See

for buffer type descriptions

Table 2-3

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Issue 1.0 - July 24, 2002

PIN DESCRIPTION

Definition of Signal Pins

Table 2-2.

1

Signal Name

ISA BUS INTERFACE

LA[23:17]

SA[19:0]

SD[15:0]

IOCHRDY

ALE

BHE#

MEMR#, MEMW#

Dir

Buffer Type

Description

Qty

O BD8STRUP_FT

I/O BD8STRP_FT

Unlatched Address Bus

Latched Address Bus

Data Bus

7

20

16

1

2

1

4

3

2

1

I

BD8STRUP_FT

I/O Channel Ready

O BD4STRP_FT

O BD8STRUP_FT

I/O BD8STRUP_FT

Address Latch Enable

System Bus High Enable

Memory Read & Write

System Memory Read and Write

I/O Read and Write

SMEMR#, SMEMW# O BD8STRP_FT

IOR#, IOW#

MASTER#

MCS16#

IOCS16#

REF#

I/O BD8STRUP_FT

I

BD4STRUP_FT

BD8STRP_FT

Add On Card Owns Bus

Memory Chip Select 16

I/O Chip Select 16

Refresh Cycle

Address Enable

I/O Channel Check (ISA)

RTC Read / Write#

RTC Data Strobe

AEN

O BD8STRUP_FT

BD4STRUP_FT

IOCHCK#

RTCRW#

RTCDS#

RTCAS

RMRTCCS#

GPIOCS#

IRQ_MUX[3:0]

DACK_ENC[2:0]

DREQ_MUX[1:0]

TC

I

O BD4STRP_FT

I/O BD4STRP_FT

RTC Address Strobe

ROM / RTC Chip Select

General Purpose Chip Select

Multiplexed Interrupt Request

DMA Acknowledge

Multiplexed DMA Request

ISA Terminal Count

ISA (0) / IDE (1) SELECTION

External Keyboard CHIP SELECT

ZERO WAIT STATE

I

BD4STRP_FT

O BD4STRP_FT

BD4STRP_FT

O BD4STRP_FT

BD4STRP_FT

I/O BD4STRP_FT

BD4STRP_FT

I

ISAOE#

KBCS#

ZWS#

I

PCMCIA INTERFACE

RESET

A[23:0]

D[15:0]

IORD#, IOWR#

O BD8STRP_FT

O BD8STRUP_FT

I/O BD8STRP_FT

O BD8STRUP_FT

Reset

Address Bus

Data Bus

I/O Read and Write

1

24

16

2

DMA Request // Write Protect

I/O Size is 16 bit

WP / IOIS16#

I

BD4STRUP_FT

1

BVD2, BVD1

READY# / IREQ#

WAIT#

OE#

WE#

I

BD4STRUP_FT

BD8STRUP_FT

Battery Voltage Detect

Busy / Ready# // Interrupt Request

Wait

Output Enable // DMA Terminal Count

Write Enable // DMA Terminal Count

DMA Acknowledge // Register

Card Detect

2

1

2

1

O BD8STRUP_FT

O BD4STRP_FT

O BD4STRUP_FT

REG#

CD2#, CD1#

CE2#, CE1#

VCC5_EN

VCC3_EN

VPP_PGM

VPP_VCC

GPI#

I

BD4STRUP_FT

O BD4STRP_FT

O BD8STRP_FT

O BD4STRP_FT

Card Enable

Power Switch control: 5 V power

Power Switch control: 3.3 V power

Power Switch control: Program power

Power Switch control: VCC power

General Purpose Input

I

BD4STRP_FT

1

Note ; See

for buffer type descriptions

Table 2-3

Issue 1.0 - July 24, 2002

15/111

PIN DESCRIPTION

Definition of Signal Pins

Table 2-2.

1

Signal Name

Dir

Buffer Type

Description

Qty

LOCAL BUS INTERFACE

PA[24:20,15,9:8,3:0] O BD4STRP_FT

Address Bus [24:20], [15], [9:8], [3:0]

Address Bus [19], [11]

Address Bus [18:16], [14:12], [7:4]

Address Bus [10]

12

2

10

1

16

1

PA[19,11]

PA[18:16,14:12,7:4]

PA[10]

PD[15:0]

PRD#

O BD8STRP_FT

O BD8STRUP_FT

O BD4STRUP_FT

I/O BD8STRP_FT

O BD4STRUP_FT

Data Bus [15:0]

Memory and I/O Read signal

Memory and I/O Write signal

Data Ready

PWR#

PRDY

I

BD8STRUP_FT

1

IOCS#[7:4]

IOCS#[3]

IOCS#[2:0]

PBE#[1]

PBE#[0]

FCS0#

O BD4STRUP_FT

O BD4STRP_FT

O BD8STRUP_FT

O BD8STRP_FT

O BD4STRUP_FT

O BD4STRP_FT

O BT8TRP_TC

O BD8STRP_FT

I/O BD4STRP_FT

I/O Chip Select

4

1

3

1

4

Upper Byte Enable (PD[15:8])

Lower Byte Enable (PD[7:0])

Flash Bank 0 Chip Select

Flash Bank 1 Chip Select

Upper half Bank 0 Flash Chip Select

Lower half Bank 0 Flash Chip Select

Upper half Bank 1 Flash Chip Select

Lower half Bank 1 Flash Chip Select

Muxed Interrupt Lines

FCS1#

FCS_0H#

FCS_0L#

FCS_1H#

FCS_1L#

1

IRQ_MUX[3:0]

IDE CONTROLLER

DD[15:12]

DD[11:0]

I/O BD4STRP_FT

I/O BD8STRUP_FT

O BD8STRUP_FT

Data Bus

Address Bus

Primary Chip Selects

Secondary Chip Selects

Data I/O Ready

4

12

3

2

DA[2:0]

PCS1, PCS3

SCS1, SCS3

DIORDY

1

PIRQ/SIRQ

I

BD4STRP_FT

Primary / Secondary Interrupt Request

Primary / Secondary DMA Request

Primary / Secondary DMA Acknowledge

Primary / Secondary IO Read

Primary / Secondary IO Write

2

PDRQ/SDRQ

PDACK#/SDACK#

PDIOR#/SDIOR#

PDIOW#/SDIOW#

O BD8STRP_FT

O BD8STRUP_FT

O BD8STRP_FT

2

VGA CONTROLLER

RED, GREEN, BLUE O VDDCO

Red, Green, Blue

3

2

1

VSYNC, HSYNC

VREF_DAC

RSET

I/O BD4STRP_FT

Vertical & Horizontal Synchronisations

DAC Voltage reference

Resistor Set

Compensation

Colour Select

I

ANA

COMP

COL_SEL

O BD4STRP_FT

I2C INTERFACE

SCL / DDC[1]

SDA / DDC[0]

I/O BD4STRUP_FT

I²C Interface - Clock / VGA DDC[1]

I²C Interface - Data / VGA DDC[0]

1

TFT INTERFACE

TFTR[5:2]

TFTR[1:0]

O BD4STRP_TC

O BD4STRP_FT

O BD4STRP_TC

O BD4STRP_FT

for buffer type descriptions

Red

Green

4

2

4

2

TFTG[5:2]

,TFTG[1:0]

1

Note ; See

Table 2-3

16/111

Issue 1.0 - July 24, 2002

PIN DESCRIPTION

Definition of Signal Pins

Table 2-2.

1

Signal Name

TFTB[5:2]

TFTB[1:0]

TFTLINE

TFTFRAME

TFTDE

Dir

Buffer Type

Description

Qty

4

2

1

O BD4STRP_TC

O BD4STRP_FT

O BD8STRP_TC

O BD4STRP_TC

Blue

Horizontal Sync

Vertical Sync

Data Enable

1

TFTENVDD,

TFTENVCC

TFTPWM

TFTDCLK

O BD4STRP_TC

Enable Vdd & Vcc of flat panel

2

O BD8STRP_TC

O BT8TRP_TC

PWM back-light control

Dot clock for Flat Panel

1

VIDEO INPUT PORT

VCLK

VIN[7:0]

ODD_EVEN#

VCS

I/O BD8STRP_FT

27-33 MHz Video Input Port Clock

Video Input Data Bus

Video Input Odd/even Field

Video Input Horizontal Sync

1

8

1

I

BD4STRP_FT

I/O BD4STRP_FT

USB INTERFACE

OC

USBDPLS[0]

USBDMNS[0]

USBDPLS[1]

USBDMNS[1]

POWERON

I

TLCHTU_TC

Over Current Detect

1

2

1

I/O USBDS_2V5

Universal Serial Bus Port 0

1

I/O USBDS_2V5

O BT4CRP

Universal Serial Bus Port 1

USB power supply lines

2

1

SERIAL CONTROLLER

CTS0#, CTS1#

DCD0#, DCD1#

DSR0#, DSR1#

DTR0#, DTR1#

RI0#, RI1#

RTS0#, RTS1#

RXD0, RXD1

TXD0, TXD1

I

TLCHT_FT

Clear to send, MSR[4] status bit

Data Carrier detect, MSR[7] status bit

Data set ready, MSR[5] status bit.

Data terminal ready, MSR[0] status bit

Ring indicator, MSR[6] status bit

Request to send, MSR[1] status bit

Receive data, Input Serial Input

Transmit data, Serial Output

2

O BD4STRP_TC

TLCHT_FT

O BD4STRP_TC

TLCHT_FT

O BD4STRP_TC

I

KEYBOARD & MOUSE INTERFACE

KBCLK

KBDATA

MCLK

I/O BD4STRP_TC

Keyboard Clock Line

Keyboard Data Line

Mouse Clock Line

Mouse Data Line

1

MDATA

PARALLEL PORT

PE

SLCT

BUSY#

ERR#

I

BD14STARP_FT

Paper End

SELECT

BUSY

ERROR

Acknowledge

Parallel Device Direction

PCS / STROBE#

INIT

Automatic Line Feed

SELECT IN

Data Bus

1

8

ACK#

PDIR#

O BD14STARP_FT

I/O BD14STARP_FT

STROBE#

INIT#

AUTOFD#

SLCTIN#

PPD[7:0]

1

Note ; See

for buffer type descriptions

Table 2-3

Issue 1.0 - July 24, 2002

17/111

PIN DESCRIPTION

Definition of Signal Pins

Table 2-2.

1

Signal Name

Dir

Buffer Type

Description

Qty

GPIO SIGNALS

GPIO[15:0]

I/O BD4STRP_FT

General Purpose IOs

16

JTAG

TCLK

TRST

TDI

TMS

TDO

I

TLCHT_FT

TLCHTD_FT

TLCHT_FT

Test Clock

Test Reset

Test Data Input

Test Mode Set

Test Data output

1

O BT8TRP_TC

MISCELLANEOUS

SCAN_ENABLE

I

TLCHTD_FT

Test Pin - Reserved

Speaker Device Output

1

SPKRD

O BD4STRP_FT

for buffer type descriptions

1

Note ; See

Table 2-3

Buffer Type Descriptions

Description

Table 2-3.

Buffer

ANA

Analog pad buffer

OSCI13B

Oscillator, 13 MHz, HCMOS

BT4CRP

LVTTL Output, 4 mA drive capability, Tri-State Control

BT8TRP_TC

LVTTL Output, 8 mA drive capability, Tri-State Control, Schmitt trigger

BD4STRP_FT

BD4STRUP_FT

BD4STRP_TC

BD8STRP_FT

BD8STRUP_FT

BD8STRP_TC

BD8TRP_TC

LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, 5V tolerant

LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant

LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger

LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, 5V tolerant

LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant

LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger

BD8PCIARP_FT

BD14STARP_FT

LVTTL Bi-Directional, 8 mA drive capability, PCI compatible, 5V tolerant

LVTTL Bi-Directional, 14 mA drive capability, Schmitt trigger, IEEE1284 compliant, 5V tolerant

BD16STARUQP_TC LVTTL Bi-Directional, 16 mA drive capability, Schmitt trigger

SCHMITT_FT

TLCHT_FT

LVTTL Input, Schmitt trigger, 5V tolerant

LVTTL Input, 5V tolerant

LVTTL Input

TLCHT_TC

TLCHTD_TC

TLCHTU_TC

LVTTL Input, Pull-Down

LVTTL Input, Pull-Up

USBDS_2V5

VDDCO

USB 1.1 compliant pad buffer

Analog output pad

18/111

Issue 1.0 - July 24, 2002

PIN DESCRIPTION

2.2. SIGNAL DESCRIPTIONS

DEV_CLK

24 MHz Peripheral Clock (floppy

drive). This 24 MHz signal is provided as a

convenience for the system integration of a Floppy

Disk driver function in an external chip. This clock

signal is not available in Local Bus mode.

2.2.1. BASIC CLOCKS AND RESETS

SYSRSTI#

System Reset/Power good. This input

is low when the reset switch is depressed.

Otherwise, it reflects the power supply’s power

good signal. PWGD is asynchronous to all clocks,

and acts as a negative active reset. The reset

circuit initiates a hard reset on the rising edge of

PWGD.

DCLK

135 MHz Dot Clock. This is the dot clock,

which drives graphics display cycles. Its frequency

can be as high as 135 MHz, and it is required to

have a worst case duty cycle of 60-40. For further

details, refer to Section 3.1.4. bit 4.

2.2.2. MEMORY INTERFACE

Note that while Reset is being asserted, the

signals on the device pins are in an unknown

state.

MCLKI

Memory Clock Input. This clock is driving

the SDRAM controller, the graphics engine and

display controller. This input should be a buffered

version of the MCLKO signal with the track lengths

between the buffer and the pin matched with the

track lengths between the buffer and the Memory

Banks.

SYSRSTO#

Reset Output to System. This is the

system reset signal and is used to reset the rest of

the components (not on Host bus) in the system.

The ISA bus reset is an externally inverted

buffered version of this output and the PCI bus

reset is an externally buffered version of this

output.

MCLKO

Memory Clock Output. This clock drives

the Memory Banks on board and is generated

from an internal PLL.

XTALI

XTALO

14.3 MHz Crystal Input

14.3 MHz Crystal Output. These pins are

The STPC Atlas MClock signal can run up to

100MHz reliably, but PCB layout is so critical that

the maximum guaranteed speed is 90MHz

provided for the connection of an external 14.318

MHz crystal to provide the reference clock for the

internal frequency synthesizer, from which the

HCLK and CLK24M signals are generated.

CS#[1:0] Chip Select These signals are used to

disable or enable device operation by masking or

enabling all SDRAM inputs except MCLK, CKE,

and DQM.

PCI_CLKI

33 MHz PCI Input Clock. This signal

must be connected to a clock generator and is

usually connected to PCI_CLKO.

CS#[2]/MA[11] Chip Select/Bank Address This

pin is CS#[2] in the case when 16-Mbit devices are

used. For all other densities, it becomes MA[11].

PCI_CLKO

33 MHz PCI Output Clock. This is the

master PCI bus clock output.

ISA_CLK

ISA Clock Output (also Multiplexer

CS#[3]/MA[12]/BA[1] Chip Select/ Memory

Address/ Bank Address This pin is CS#[3] in the

case when 16 Mbit devices are used. For all other

densities, it becomes MA[12] when 2 internal

banks devices are used and BA[1] when 4 internal

bank devices are used.

Select Line For IPC). This pin produces the Clock

signal for the ISA bus. It is also used with

ISA_CLK2X as the multiplexer control lines for the

Interrupt Controller Interrupt input lines. This is a

divided down version of the PCICLK or OSC14M.

ISA_CLKX2

ISA Clock Output (also Multiplexer

MA[10:0]

Memory Address. Multiplexed row and

Select Line For IPC). This pin produces a signal at

twice the frequency of the ISA bus Clock signal. It

is also used with ISA_CLK as the multiplexer

control lines for the Interrupt Controller Interrupt

input lines.

column address lines.

BA[0]

Bank Address. Internal bank address line.

This is the 64-bit memory

MD[63:0] Memory Data.

data bus. This bus is also used as input at the

rising edge of SYSRSTI# to latch in power-up

configuration information into the ADPC strap

registers.

CLK14M

ISA bus synchronisation clock. This is

the buffered 14.318 MHz clock to the ISA bus.

HCLK

frequency can vary from 25 to 66 MHz. All host

transactions and PCI transactions are

Host Clock. This is the host clock. Its

RAS#[1:0] Row Address Strobe. There are two

active-low row address strobe output signals. The

RAS# signals drive the memory devices directly

without any external buffering.

synchronized to this clock. Host transactions

executed by the DRAM controller are also driven

by this clock.

Issue 1.0 - July 24, 2002

19/111

PIN DESCRIPTION

CAS#[1:0] Column Address Strobe. There are

two active-low column address strobe output

signals. The CAS# signals drive the memory

devices directly without any external buffering.

DEVSEL# prior to the subtractive decode phase of

the current PCI transaction.

PAR

Parity Signal Transactions.

This is the parity

signal of the PCI bus. This signal is used to

guarantee even parity across AD[31:0],

CBE[3:0]#, and PAR. This signal is driven by the

master during the address phase and data phase

of write transactions. It is driven by the target

during data phase of read transactions. (Its

assertion is identical to that of the AD bus delayed

by one PCI clock cycle)

MWE# Write Enable. Write enable specifies

whether the memory access is a read (MWE# = H)

or a write (MWE# = L). This single write enable

controls all DRAMs. The MWE# signals drive the

memory devices directly without any external

buffering.

2.2.3. PCI INTERFACE

PERR# Parity Error

AD[31:0] PCI Address/Data. This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and data phase of write transactions. It is

driven by the target during data phase of read

transactions.

SERR# System Error. This is the system error

signal of the PCI bus. It may, if enabled, be

asserted for one PCI clock cycle if target aborts a

STPC Atlas initiated PCI transaction. Its assertion

by either the STPC Atlas or by another PCI bus

agent will trigger the assertion of NMI to the host

CPU. This is an open drain output.

PBE[3:0]# Bus Commands/Byte Enables. These

are the multiplexed command and Byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

phase they carry the Byte enable information.

These pins are inputs when a PCI master other

than the STPC Atlas owns the bus and outputs

when the STPC Atlas owns the bus.

LOCK# PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

PCI_REQ#[2:0] PCI Request. These pins are the

three external PCI master request pins. They

indicates to the PCI arbiter that the external

agents desire use of the bus.

FRAME# Cycle Frame. This is the frame signal of

the PCI bus. It is an input when a PCI master owns

the bus and is an output when STPC Atlas owns

the PCI bus.

PCI_GNT#[2:0] PCI Grant. These pins indicate

that the PCI bus has been granted to the master

requesting it on its PCI_REQ#.

TRDY# Target Ready. This is the target ready

signal of the PCI bus. It is driven as an output

when the STPC Atlas is the target of the current

bus transaction. It is used as an input when STPC

Atlas initiates a cycle on the PCI bus.

PCI_INT#[3:0] PCI Interrupt Request. These are

the PCI bus interrupt signals. They are to be

encoded before connection to the STPC Atlas

using ISACLK and ISACLKX2 as the input

selection strobes.

IRDY# Initiator Ready. This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Atlas initiates a bus cycle on the PCI

bus. It is used as an input during the PCI cycles

targeted to the STPC Atlas to determine when the

current PCI master is ready to complete the

current transaction.

2.2.4. ISA BUS INTERFACE

LA[23:17]

Unlatched Address.

These unlatched

ISA Bus pins address bits 23-17 on 16-bit devices.

When the ISA bus is accessed by any cycle

initiated from the PCI bus, these pins are in output

mode. When an ISA bus master owns the bus,

these pins are tristated.

STOP# Stop Transaction. STOP# is used to

implement the disconnect, retry and abort protocol

of the PCI bus. It is used as an input for the bus

cycles initiated by the STPC Atlas and is used as

an output when a PCI master cycle is targeted to

the STPC Atlas.

SA[19:0]

Unlatched Address.

These are the 20

low bits of the system address bus of ISA. These

pins are used as an input when an ISA bus master

owns the bus and are outputs at all other times.

DEVSEL# Device Select. This signal is used as

an input when the STPC Atlas initiates a bus cycle

on the PCI bus to determine if a PCI slave device

has decoded itself to be the target of the current

transaction. It is asserted as an output either when

the STPC Atlas is the target of the current PCI

transaction or when no other device asserts

SD[15:0] I/O Data Bus (ISA). These are the

external ISA databus pins.

IOCHRDY

IO Channel Ready.

IOCHRDY is the IO

channel ready signal of the ISA bus and is driven

as an output in response to an ISA master cycle

targeted to the host bus or an internal register of

20/111

Issue 1.0 - July 24, 2002

PIN DESCRIPTION

the STPC Atlas. The STPC Atlas monitors this

signal as an input when performing an ISA cycle

on behalf of the host CPU, DMA master or refresh.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Atlas since

the access to the system memory can be

considerably delayed due to CRT refresh or a

write back cycle.

IOCS16# IO Chip Select16. This signal is the

decode of SA15-0 address pins of the ISA

address bus without any qualification of the

command signals. The STPC Atlas does not drive

IOCS16# (similar to PC-AT design). An ISA

master access to an internal register of the STPC

Atlas is executed as an extended 8-bit IO cycle.

REF#

Refresh Cycle. This is the refresh command

ALE

Address Latch Enable. This is the address

signal of the ISA bus. It is driven as an output

when the STPC Atlas performs a refresh cycle on

the ISA bus. It is used as an input when an ISA

master owns the bus and is used to trigger a

refresh cycle.

latch enable output of the ISA bus and is asserted

by the STPC Atlas to indicate that LA23-17, SA19-

0, AEN and SBHE# signals are valid. The ALE is

driven high during refresh, DMA master or an ISA

master cycles by the STPC Atlas.

The STPC Atlas performs a pseudo hidden

refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

in external buffers. The host bus is then

relinquished while the refresh cycle continues on

the ISA bus.

ALE is driven low after reset.

BHE#

System Bus High Enable. This signal, when

asserted, indicates that a data Byte is being

transferred on SD15-8 lines. It is used as an input

when an ISA master owns the bus and is an

output at all other times.

AEN Address Enable. Address Enable is enabled

when the DMA controller is the bus owner to

indicate that a DMA transfer will occur. The

enabling of the signal indicates to IO devices to

ignore the IOR#/IOW# signal during DMA

transfers.

MEMR#

Memory Read. This is the memory read

command signal of the ISA bus. It is used as an

input when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

IOCHCK#

IO Channel Check. IO Channel Check

MEMW#

Memory Write. This is the memory write

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal

becomes active upon seeing IOCHCK# active if

the corresponding bit in Port B is enabled.

command signal of the ISA bus. It is used as an

input when an ISA master owns the bus and is an

output at all other times.

SMEMR#

System Memory Read. The STPC Atlas

GPIOCS#

I/O General Purpose Chip Select 1.

generates SMEMR# signal of the ISA bus only

when the address is below one MByte or the cycle

is a refresh cycle.

This output signal is used by the external latch on

ISA bus to latch the data on the SD[7:0] bus. The

latch can be use by PMU unit to control the

external peripheral devices to power down or any

other desired function.

SMEMW#

System Memory Write. The STPC

Atlas generates SMEMW# signal of the ISA bus

only when the address is below one MByte.

RTCRW# Real Time Clock RW#. This pin is used

as RTCRW#. This signal is asserted for any I/O

write to port 71h.

IOR# I/O Read. This is the IO read command

signal of the ISA bus. It is an input when an ISA

master owns the bus and is an output at all other

times.

RTCDS#

Real Time Clock DS. This pin is used as

RTCDS#. This signal is asserted for any I/O read

to port 71h. Its polarity complies with the DS pin of

the MT48T86 RTC device when configured with

Intel timings.

IOW#

I/O Write. This is the IO write command

signal of the ISA bus. It is an input when an ISA

master owns the bus and is an output at all other

times.

RTCAS Real time clock address strobe. This

signal is asserted for any I/O write to port 70h.

MASTER#

Add On Card Owns Bus. This signal is

active when an ISA device has been granted bus

ownership.

RMRTCCS# ROM/Real Time clock chip select.

This pin is a multi-function pin. This signal is

asserted if a ROM access is decoded during a

memory cycle. It should be combined with

MEMR# or MEMW# signals to properly access the

ROM. During an IO cycle, this signal is asserted if

access to the Real Time Clock (RTC) is decoded.

It should be combined with IOR# or IOW# signals

to properly access the real time clock.

MCS16#

Memory Chip Select16. This is the

decode of LA23-17 address pins of the ISA

address bus without any qualification of the

command signal lines. MCS16# is always an

input. The STPC Atlas ignores this signal during

IO and refresh cycles.

Issue 1.0 - July 24, 2002

21/111

PIN DESCRIPTION

IRQ_MUX[3:0] Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They are

to be encoded before connection to the STPC

Atlas using ISACLK and ISACLKX2 as the input

selection strobes.

Note that IRQ8B, which by convention is

connected to the RTC, is inverted before being

sent to the interrupt controller, so that it may be

connected directly to the IRQ# pin of the RTC.

Cards (asserted when the switch is set to write

protect).

BVD1, BVD2

Battery Voltage Detect.

These

inputs will be generated by memory PC Cards that

include batteries and are an indication of the

condition of the batteries. BVD1 and BVD2 are

kept asserted high when the battery is in good

condition.

ISAOE# Bidirectional OE Control. This signal

controls the OE signal of the external transceiver

that connects the IDE DD bus and ISA SA bus.

READY#/BUSY#/IREQ#

Ready/busy/Interrupt

request.

This input is driven low by memory PC

Cards to signal that their circuits are busy

processing a previous write command.

KBCS# Keyboard Chip Select. This signal is

asserted if a keyboard access is decoded during a

I/O cycle.

WAIT#

Bus Cycle Wait.

PC Card to delay completion of the memory or I/O

cycle in progress.

This input is driven by the

ZWS# Zero Wait State. This signal, when

asserted by addressed device, indicates that

current cycle can be shortened.

OE# Output Enable. OE# is an active low output

which is driven to the PC Card to gate Memory

Read data from memory PC Cards.

DACK_ENC[2:0] DMA Acknowledge. These are

the ISA bus DMA acknowledge signals. They are

encoded by the STPC Atlas before output and

should be decoded externally using ISACLK and

ISACLKX2 as the control strobes.

WE#/PRGM# Write Enable. This output is used by

the host for gating Memory Write data. WE# is

also used for memory PC Cards that have

programmable memory.

REG# Attribute Memory Select. This output is

inactive (high) for all normal accesses to the Main

Memory of the PC Card. I/O PC Cards will only

respond to IORD# or IOWR# when REG# is active

(low). Also see Section 2.2.7.

DREQ_MUX[1:0] ISA Bus Multiplexed DMA

Request.

These are the ISA bus DMA request

signals. They are to be encoded before

connection to the STPC Atlas using ISACLK and

ISACLKX2 as the input selection strobes.

CD1#, CD2# Card Detect. These inputs provide

for the detection of correct card insertion. CD#1

and CD#2 are positioned at opposite ends of the

connector to assist in the detection process.

These inputs are internally grounded on the PC

Card therefore they will be forced low whenever a

card is inserted in a socket.

TC ISA Terminal Count. This is the terminal count

output of the DMA controller and is connected to

the TC line of the ISA bus. It is asserted during the

last DMA transfer, when the Byte count expires.

2.2.5. PCMCIA INTERFACE

RESET Card Reset. This output forces a hard

reset to a PC Card.

CE1#, CE2# Card Enable. These are active low

output signals provided from the PCIC. CE#1

enables even Bytes, CE#2 odd Bytes.

A[25:0] Address Bus. These are the 25 low bits of

the system address bus of the PCMCIA bus.

These pins are used as an input when an PCMCIA

bus owns the bus and are outputs at all other

times.

ENABLE# Enable. This output is used to activate/

select a PC Card socket. ENABLE# controls the

external address buffer logic.C card has been

detected (CD#1 and CD#2 = '0').

D[15:0] I/O Data Bus (PCMCIA). These are the

external PCMCIA databus pins.

ENIF# ENIF. This output is used to activate/select

a PC Card socket.

IORD# I/O Read. This output is used with REG# to

gate I/O read data from the PC Card, (only when

REG# is asserted).

EXT_DIR EXternal Transceiver Direction Control.

This output is high during a read and low during a

write. The default power up condition is write

(low). Used for both Low and High Bytes of the

Data Bus.

IOWR# I/O Write. This output is used with REG#

to gate I/O write data from the PC Card, (only

when REG# is asserted).

VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0,

VPP2_EN1 Power Control. Five output signals

WP Write Protect. This input indicates the status

of the Write Protect switch (if fitted) on memory PC

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Issue 1.0 - July 24, 2002

PIN DESCRIPTION

used to control voltages (VPP1, VPP2 and VCC)

to a PC Card socket. Also see Section 13.7.5.

2.2.8. IDE INTERFACE

Address. These signals are connected to

DA[2:0] of IDE devices directly or through a buffer.

If the toggling of signals are to be masked during

ISA bus cycles, they can be externally ORed with

ISAOE# before being connected to the IDE

devices.

DA[2:0]

GPI#

General Purpose Input. This signal is

hardwired to 1.

2.2.6. LOCAL BUS

PA[24:0] Address Bus Output.

DD[15:0] Databus. When the IDE bus is active,

they serve as IDE signals DD[11:0]. IDE devices

are connected to SA[19:8] directly and ISA bus is

connected to these pins through two LS245

transceivers.

This is the 16-bit data bus.

PD[15:0] Data Bus.

D[7:0] is the LSB and PD[15:8] is the MSB.

PRD#[1:0] Read Control output. These are

memory and I/O Read signals. PRD0# is used to

read the LSB and PRD1# to read the MSB.

PCS1, PCS3, SCS1, SCS3 Primary & Secondary

Chip Selects. These signals are used as the active

high primary and secondary master & slave IDE

chip select signals. These signals must be

externally NANDed with the ISAOE# signal before

driving the IDE devices to guarantee it is active

only when ISA bus is idle. In Local Bus mode, they

just need to be inverted.

PWR#[1:0] Write Control output. These are

memory and I/O Write signals. PWR0# is used to

write the LSB and PWR1# to write the MSB.

PRDY Data Ready input. This signal is used to

create wait states on the bus. When high, it

completes the current cycle.

DIORDY

Busy/Ready. This pin serves as IDE

signal DIORDY.

FCS#[1:0] Two Flash Memory Chip Select

outputs. These are the Programmable Chip Select

signals for Flash memory.

PIRQ

SIRQ

Primary Interrupt Request.

Secondary Interrupt Request.

Interrupt request from IDE channels.

IOCS#[7:0] I/O Chip Select output. These are the

Programmable Chip Select signals for up to 4

external I/O devices.

PDRQ

SDRQ

Primary DMA Request.

Secondary DMA Request.

DMA request from IDE channels.

PBE#[1:0] Byte Enable. These are the Byte

enables that identifies on which databus the date

is valid. PBE#[0] corresponds to PD[7:0] and

PBE#[1] corresponds to PD[15:8]. These are

normally used when 8 bit transfers are transfered

across the 16 bit bus.

PDACK#

SDACK#

Primary DMA Acknowledge.

Secondary DMA Acknowledge.

DMA acknowledge to IDE channels.

PDIOR#, PDIOW# Primary I/O Read & Write.

SDIOR#, SDIOW#

Secondary I/O Read & Write.

IRQ_MUX#[3:0]

2.2.7. IPC

Multiplexed Interrupt Lines.

Primary & Secondary channel read & write.

2.2.9. MONITOR INTERFACE

DACK_ENC[2:0]

DMA Acknowledge. These are

RED, GREEN, BLUE

RGB Video Outputs. These

the ISA bus DMA acknowledge signals. They are

encoded by the STPC Industrial before output and

should be decoded externally using ISACLK and

ISACLKX2 as the control strobes.

are the 3 analog colour outputs from the

RAMDACs. These signals are sensitive to

interference, therefore they need to be properly

shielded.

DREQ_MUX[1:0]

ISA Bus Multiplexed DMA

VSYNC

Vertical Synchronisation Pulse. This is

the vertical synchronization signal from the VGA

controller.

Request. These are the ISA bus DMA request

signals. They are to be encoded before

connection to the STPC Industrial using ISACLK

and ISACLKX2 as the input selection strobes.

HSYNC

Horizontal Synchronisation Pulse. This is

the horizontal synchronization signal from the

VGA controller.

TC

ISA Terminal Count. This is the terminal count

output of the DMA controller and is connected to

the TC line of the ISA bus. It is asserted during the

last DMA transfer, when the Byte count expires.

VREF_DAC DAC Voltage reference. This pin is

an input driving the digital to analog converters.

This allows an external voltage reference source

to be used.

Issue 1.0 - July 24, 2002

23/111

PIN DESCRIPTION

RSET Resistor Current Set. This is the reference

current input to the RAMDAC. Used to set the full-

scale output of the RAMDAC.

TFTR5-0, Red Output.

Green Output.

TFTG5-0,

TFTB5-0, Blue Output.

COMP Compensation. This is the RAMDAC

compensation pin. Normally, an external capacitor

(typically 10nF) is connected between this pin and

TFTENVDD,

Enable VDD of Flat Panel.

V

to damp oscillations.

DD

TFTENVCC, Enable VCC of Flat Panel.

DDC[1:0] Direct Data Channel Serial Link. These

bidirectional pins are connected to CRTC register

3Fh to implement DDC capabilities. They conform

PWM

PWM Back-Light Control.

This PWM is

clocked by the PCI clock.

2

to I C electrical specifications, they have open-

TFTDCLK,

Dot clock for the Flat Panel.

collector output drivers which are internally

connected to V through pull-up resistors.

DD

2.2.12. USB INTERFACE

They can instead be used for accessing I²C

devices on board. DDC1 and DDC0 correspond to

SCL and SDA respectively.

OC OVER CURRENT DETECT This signal is

used to monitor the status of the USB power

supply lines of both devices. USB port are

disabled when OC signal is asserted.

2.2.10. VIDEO INTERFACE

VCLK Pixel Clock Input.This signal is used to

synchronise data being transferred from an

external video device to either the frame buffer, or

alternatively out the TV output in bypass mode.

This pin can be sourced from STPC if no external

VCLK is detected, or can be input from an external

video clock source.

USBDPL0, USBDMNS0 UNIVERSAL SERIAL

BUS DATA 0

This signal pair comprises the

differential data signal for USB port 0.

USBDPL1, USBDMNS1

BUS PORT 1

UNIVERSAL SERIAL

This signal pair comprises the

differential data signal for USB port 1.

POWERON USB power supply lines

2.2.13. SERIAL INTERFACE

VIN[7:0] YUV Video Data Input ITU-R 601 or 656.

Time

multiplexed

4:2:2

luminance

and

chrominance data as defined in ITU-R Rec601-2

and Rec656 (except for TTL input levels). This bus

typically carries a stream of Cb,Y,Cr,Y digital

video at VCLK frequency, clocked on the rising

edge (by default) of VCLK.

RXD0, RXD1 Serial Input. Data is clocked in using

RCLK/16.

TXD0, TXD1 Serial Output. Data is clocked out

using TCLK/16 (TCLK=BAUD#).

VCS Line synchronisation Input. This is the

horizontal synchronisation of the incomming

CCIR601 video.

DCD0#, DCD1# Input Data carrier detect.

RI0#, RI1# Input Ring indicator.

The signal is synchronous to rising edge of VCLK.

ODD_EVEN Frame Synchronisation Output. This

is the vertical synchronisation of the incomming

CCIR601 video.

The signal is synchronous to rising edge of VCLK.

The default polarity for this pin is:

- odd (not-top) field: LOW level

- even (bottom) field: HIGH level

DSR0#, DSR1# Input Data set ready.

CTS0#, CTS1# Input Clear to send.

RTS0#, RTS1# Output Request to send.

DTR0#, DTR1# Output Data terminal read.

2.2.14. KEYBOARD/MOUSE INTERFACE

2.2.11. TFT INTERFACE SIGNALS

The TFT (Thin Film Transistor) interface converts

signals from the CRT controller into control signals

for an external TFT Flat Panel. The signals are

listed below.

KBCLK, Keyboard Clock line. Keyboard data is

latched by the controller on each negative clock

edge produced on this pin. The keyboard can be

disabled by pulling this pin low by software control.

TFTFRAME, Vertical Sync. pulse Output.

TFTLINE, Horizontal Sync. Pulse Output.

TFTDE, Data Enable.

KBDATA, Keyboard Data Line. 11-bits of data are

shifted serially through this line when data is being

transferred. Data is synchronised to KBCLK.

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Issue 1.0 - July 24, 2002

PIN DESCRIPTION

Mouse data is latched

SLCTIN# Select In. Printer select output.

Parallel Port Data Lines Data transfer

MCLK, Mouse Clock line.

by the controller on each negative clock edge

produced on this pin. The mouse can be disabled

by pulling this pin low by software control.

PPD[7-0]

lines to printer. Bidirectional depending on modes.

MDATA,

Mouse Data Line. 11-bits of data are

2.2.16. MISCELLANEOUS

shifted serially through this line when data is being

transferred. Data is synchronised to MCLK.

SPKRD

Speaker Drive. This is the output to the

speaker and is the AND of the counter 2 output

with bit 1 of Port 61h and drives an external

speaker driver. This output should be connected

to a 7407 type high voltage driver.

2.2.15. PARALLEL PORT

Input status signal from printer.

PE Paper End.

SLCT

Printer Select. Printer selected input.

SCAN_ENABLE Reserved. This pin is reserved

for Test and Miscellaneous functions. It has to be

set to ‘0’ or connected to ground in normal

operation.

BUSY#

Printer Busy.

Input status signal from printer.

ERR#

ACK#

Error. Input status signal from printer.

Acknowledge.

COL_SEL

Colour Select. Can be used for Picture

in Picture function. Note however that this signal,

brought out from the video pipeline, is not in sync

with the VGA output signals, i.e. the VGA signals

run four clock cycles after the Col_Sel signal.

Input status signal from printer.

PDDIR#

Parallel Device Direction.

Bidirectional control line output.

2.2.17. JTAG INTERFACE

STROBE#

PCS/Strobe#.

TCLK

Test clock

Data transfer strobe line to printer.

TDI

Test data input

INIT#

Initialize Printer. This output sends an

initialize command to the connected printer.

TMS

TDO

TRST

Test mode input

AUTOFD#

Automatic Line feed. This output sends

Test data output

a

command to the connected printer to

automatically generate line feed on received

carriage returns.

Test reset input

Issue 1.0 - July 24, 2002

25/111

PIN DESCRIPTION

2.3. SIGNAL DETAIL

The resulting interface is then dynamically muxed

with the IDE Interface.

The muxing between ISA, LOCAL BUS and

PCMCIA is performed by external strap options.

Multiplexed Signals (on the same pin)

Table 2-4.

IDE Pin Name

DIORDY

DA[2]

ISA Pin Name

IOCHRDY

LA[19]

PCMCIA Pin Names

Local Bus Pin Name

-

= 0

DA[1:0]

LA[18:17]

LA[23:22]

LA[21:20]

RMRTCCS#

KBCS#

A[25:24]

A[23:22]

A[21:20]

ROMCS#

Hi-Z

SCS3,SCS1

PCS3,PCS1

DD[15]

DD[14]

DD[13:12]

DD[11:0]

RTCRW#, RTCDS#

SA[19:8]

SD[15:0]

RTCAS

DEV_CLK

SA[3]

Hi-Z

A[19:8]

D[15:0]

= 0

DEV_CLK

A[3]

PD[15:0]

FCS0#

FCS1#

PRDY

SA[2:0]

A[2:0]

IOCS#[2:0]

PBE#[1]

PBE#[0]

PRD#

PWR#

PA[2:0]

PA[3]

SMEMW#

IOCS16#

MASTER#

MCS16#

DACK_ENC [2:0]

TC

VPP_PGM

WP/IOIS16#

BVD1

= 0

= 0x04

= 0

SA[7:4]

ZWS#

A[7:4]

GPI#

PA[7:4]

PA[8]

GPIOCS#

IOCHCK#

REF#

IOW#

IOR#

VCC5_EN

BVD2

RESET

IOWR#

IORD#

= 0

PA[9]

PA[10]

PA[11]

PA[12]

PA[13]

PA[14]

PA[15]

MEMR#

ALE

= 0

AEN

BHE#

WAIT#

OE#

PA[16]

PA[17]

MEMW#

SMEMR#

DREQ_MUX#[1:0]

Hi-Z

= 0

PA[18]

PA[19]

PA[21:20]

PA[22]

VCC3_EN

CE2#, CE1#

Hi-Z

VPP_VCC

WE#

PA[23]

PA[24]

Hi-Z

ISAOE# = 0

REG#

IOCS#[7]

IOCS#[6]

IOCS#[5], IOCS#[4]

IOCS#[3]

READY#

CD1#, CD2#

ISAOE# = 0

ISAOE# = 1

26/111

Issue 1.0 - July 24, 2002

PIN DESCRIPTION

Signal value on Reset

Table 2-5.

SYSRSTI# inactive

SYSRSTO# active

Signal Name

SYSRSTI# active

release of SYSRSTO#

BASIC CLOCKS AND RESETS

XTALO

ISA_CLK

14MHz

Low

7MHz

ISA_CLK2X

OSC14M

DEV_CLK

14MHz

24MHz

HCLK

PCI_CLKO

DCLK

Oscillating at the speed defined by the strap options.

HCLK divided by 2 or 3, depending on the strap options.

17MHz

MEMORY CONTROLLER

MCLKO

66MHz if asynchonous mode, HCLK speed if synchronized mode.

CS#[3:1]

CS#[0]

High

MA[10:0], BA[0]

RAS#[1:0], CAS#[1:0]

MWE#, DQM[7:0]

MD[63:0]

0x00

High

Input

SDRAM init sequence:

Write Cycles

PCI INTERFACE

AD[31:0]

0x0000

CBE[3:0], PAR

FRAME#, TRDY#, IRDY#

STOP#, DEVSEL#

PERR#, SERR#

PCI_GNT#[2:0]

ISA BUS INTERFACE

ISAOE#

Low

Input

High

First prefetch cycles

when not in Local Bus mode.

High

Low

RMRTCCS#

LA[23:17]

SA[19:0]

SD[15:0]

BHE#, MEMR#

Hi-Z

Unknown

0xFFFXX

Unknown

0x00

First prefetch cycles

when in ISA or PCMCIA mode.

Address start is 0xFFFFF0

0xFFF03

0xFF

High

MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown

High

REF#

ALE, AEN

Unknown

Low

High

DACK_ENC[2:0]

TC

Input

0x04

Low

GPIOCS#

Hi-Z

High

RTCDS#, RTCRW#, KBCS#

RTCAS

Hi-Z

Unknown

Low

PCMCIA INTERFACE

RESET

A[23:0]

D[15:0]

IORD#, IOWR#, OE#

WE#, REG#

Unknown

High

0x00

0xFF

High

First prefetch cycles

using RMRTCCS#

CE2#, CE1#, VCC5_EN, VCC3_EN

VPP_PGM, VPP_VCC

LOCAL BUS INTERFACE

PA[24:0]

PD[15:0]

PRD#

High

Low

Unknown

High

0xFF

High

First prefetch cycles

PBE#[1:0], FCS0#, FCS_0H#

Issue 1.0 - July 24, 2002

27/111

PIN DESCRIPTION

Signal value on Reset

Table 2-5.

SYSRSTI# inactive

SYSRSTO# active

Signal Name

SYSRSTI# active

release of SYSRSTO#

FCS_0L#, FCS1#, FCS_1H#, FCS_1L#

PWR#, IOCS#[7:0]

IDE CONTROLLER

DD[15:0]

High

0xFF

DA[2:0]

Unknown

High

Low

PCS1, PCS3, SCS1, SCS3

PDACK#, SDACK#

PDIOR#, PDIOW#, SDIOR#, SDIOW#

VGA CONTROLLER

RED, GREEN, BLUE

VSYNC, HSYNC

High

Black

Low

COL_SEL

Unknown

I2C INTERFACE

SCL / DDC[1]

SDA / DDC[0]

Input

TFT INTERFACE

TFT[R,G,B][5:0]

TFTLINE, TFTFRAME

0x00,0x00,0x00

Low

TFTDE, TFTENVDD, TFTENVCC, TFTPWM Low

TFTDCLK

Oscillating at DCLK speed

USB INTERFACE

1

USBDPLS[1:0]

Low

High

Unknown

1

USBDMNS[1:0]

1

POWERON

Low

SERIAL CONTROLLER

TXD0, RTS0#, DTR0#

TXD1, RTS1#, DTR1#

KEYBOARD & MOUSE INTERFACE

KBCLK, MCLK

High

Low

KBDATA, MDATA

PARALLEL PORT

PDIR#, INIT#

Input

Low

STROBE#, AUTOFD#

SLCTIN#

PPD[7:0]

High

Unknown

Low

0x00

GPIO SIGNALS

GPIO[15:0]

JTAG

High

Low

TDO

MISCELLANEOUS

SPKRD

28/111

Issue 1.0 - July 24, 2002

PIN DESCRIPTION

Pinout

Table 2-6.

Pinout

Table 2-6.

Pin#

AB3

Pin Name

Pin#

T4

Y5

AA2

T3

T5

Pin Name

MD[18]

MD[19]

MD[20]

MD[21]

MD[22]

MD[23]

MD[24]

MD[25]

MD[26]

MD[27]

MD[28]

MD[29]

MD[30]

MD[31]

MD[32]

MD[33]

MD[34]

MD[35]

MD[36]

MD[37]

MD[38]

MD[39]

MD[40]

MD[41]

MD[42]

MD[43]

MD[44]

MD[45]

MD[46]

MD[47]

MD[48]

MD[49]

MD[50]

MD[51]

MD[52]

MD[53]

MD[54]

MD[55]

MD[56]

MD[57]

MD[58]

MD[59]

MD[60]

MD[61]

MD[62]

MD[63]

CS#[0]

CS#[1]

DQM[1]

DQM[2]

DQM[3]

DQM[4]

DQM[5]

DQM[6]

DQM[7]

Pin#

D15

C15

AF21

AF22

AF23

AF24

E15

Pin Name

SYSRSETI#

SYSRSETO#

XTALI

AC1

AC3

AD2

AF3

AE4

AF4

AD5

AF5

AC6

AF6

AC7

AE7

AB8

J3

J1

K4

K2

L5

L3

L1

M4

M2

N5

N3

N1

P2

P4

R1

R3

AA5

AB2

AB4

AC2

AD1

AE3

AD4

AC5

AB6

AE5

AB7

AD6

AE6

AD7

AF7

AC8

U1

XTALO

AA1

AA3

PCI_CLKI

PCI_CLKO

ISA_CLK

ISA_CLK2X

OSC14M

HCLK

B3

A3

C4

B4

A4

D5

C5

B5

A5

D6

C6

B6

A6

E7

D7

C7

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

AD[5]

AD[6]

AD[7]

A16

AB18

AB24

AB25

AC18

1

DEV_CLK /FCS1#

DCLK

AF20

AF19

U5

V1

V2

V3

MCLKI

MCLKO

MA[0]

MA[1]

MA[2]

MA[3]

MA[4]

MA[5]

MA[6]

MA[7]

MA[8]

MA[9]

MA[10]

BA[0]

RAS#[0]

RAS#[1]

CAS#[0]

CAS#[1]

MWE#

MD[0]

AD[8]

AD[9]

AD[10]

AD[11]

AD[12]

AD[13]

AD[14]

AD[15]

AD[16]

AD[17]

AD[18]

AD[19]

AD[20]

AD[21]

AD[22]

AD[23]

AD[24]

AD[25]

AD[26]

AD[27]

AD[28]

AD[29]

AD[30]

AD[31]

CBE[0]

CBE[1]

CBE[2]

CBE[3]

V4

V5

W1

W2

W3

W5

Y1

A9

E10

C10

B10

A10

E11

D11

C11

A11

E12

D12

C12

B12

A12

E13

D13

E6

B7

B9

B11

C9

E9

D9

B8

A8

A7

Y2

U3

U4

R5

T1

R4

J4

J2

K5

K3

K1

MD[1]

MD[2]

MD[3]

MD[4]

MD[5]

MD[6]

MD[7]

MD[8]

L4

L2

M5

M3

M1

N4

N2

P1

MD[9]

MD[10]

MD[11]

MD[12]

MD[13]

MD[14]

MD[15]

MD[16]

MD[17]

FRAME#

TRDY#

IRDY#

STOP#

DEVSEL#

PAR

P3

P5

U2

Y3

Y4

CS#[2]/MA[11]

CS#[3]/MA[12]/BA[1]

DQM[0]

R2

AA4

AB1

T2

D8

PERR#

1

Note ; This signal is multiplexed

see

1

Note ; This signal is multiplexed

see

Table 2-4

Issue 1.0 - July 24, 2002

29/111

PIN DESCRIPTION

Pinout

Table 2-6.

Pin#

E8

C8

C14

B14

A14

A13

B13

C13

Pin Name

SERR#

Pin#

F25

Pin Name

Pin#

C19

Pin Name

1

SD[15]

PA[23]

PA[24]

1

LOCK#

F23

D20

K25

F24

A22

G23

E21

H22

E26

E25

E24

C22

G22

E17

A23

U25

U26

U24

U23

D22

D24

E23

C26

F22

A24

C23

B23

D26

D25

B24

B15

A15

E14

D14

B16

B22

K26

IOCHRDY

B19

A17

B17

C16

E16

D17

C18

B18

C17

1

PCI_REQ#[0]

PCI_REQ#[1]

PCI_REQ#[2]

PCI_GNT#[0]

PCI_GNT#[1]

PCI_GNT#[2]

ALE

FCS_0H

FCS_0L

FCS_1H

FCS_1L

IOCS#[4]

IOCS#[5]

IOCS#[6]

IOCS#[7]

1

BHE#

1

MEMR#

1

MEMW#

1

SMEMR#

SMEMW#

1

IOR#

1

C20

B21

B20

E19

E18

C21

D19

P22

P23

P24

P25

P26

N26

N25

N24

N23

N22

M26

M25

M24

M23

M22

L26

L25

L24

L23

L22

K24

J26

LA[17]

LA[18]

LA[19]

LA[20]

LA[21]

LA[22]

LA[23]

IOW#

1

MASTER#

1

MCS16#

AD8

AF8

AC9

AB10

AF9

AB9

AD9

AE8

AE9

AC10

RED

1

IOCS16#

GREEN

BLUE

VSYNC

HSYNC

VREF_DAC

RSET

1

REF#

AEN

1

IOCHCK#

RTCRW#

1

SA[0]

SA[1]

SA[2]

SA[3]

SA[4]

SA[5]

SA[6]

SA[7]

1

RTCDS#

1

RTCAS /FCS0#

COMP

1

RMRTCCS#

VDD_DAC

VSS_DAC

1

GPIOCS#

1

IRQ_MUX[0]

IRQ_MUX[1]

IRQ_MUX[2]

IRQ_MUX[3]

DACK_ENC[0]

DACK_ENC[1]

DACK_ENC[2]

DREQ_MUX[0]

DREQ_MUX[1]

1

AB15

AF16

AE16

AC16

AB16

AF17

AE17

AD17

AB17

AD18

AF18

VCLK

1

VIN[0]

VIN[1]

VIN[2]

VIN[3]

VIN[4]

VIN[5]

VIN[6]

VIN[7]

ODD_EVEN#

VCS

1

SA[8]

SA[9]

1

SA[10]

SA[11]

SA[12]

SA[13]

SA[14]

SA[15]

SA[16]

SA[17]

1

TC

1

PCI_INT#[0]

PCI_INT#[1]

PCI_INT#[2]

PCI_INT#[3]

1

SA[18]

SA[19]

AE10

AF10

AB11

AD11

AE11

AF11

AB12

AC12

AD12

AE12

AF12

AB13

AC13

AD13

AE13

AF13

AF14

TFTR0

TFTR1

TFTR2

TFTR3

TFTR4

TFTR5

TFTG0

TFTG1

TFTG2

TFTG3

TFTG4

TFTG5

TFTB0

TFTB1

TFTB2

TFTB3

TFTB4

1

ISAOE#

1

SD[0]

SD[1]

SD[2]

SD[3]

SD[4]

SD[5]

SD[6]

SD[7]

KBCS#

1

ZWS#

1

J25

J24

1

R23

R24

T22

T23

R25

R26

T25

T24

R22

T26

PIRQ

SIRQ

PDRQ

SDRQ

1

K23

K22

H26

H25

H24

G26

G25

G24

J22

1

PDACK#

SDACK#

PDIOR#

PDIOW#

SDIOR#

SDIOW#

1

SD[8]

SD[9]

1

SD[10]

SD[11]

SD[12]

SD[13]

1

J23

1

F26

SD[14]

D18

PA[22]

1

Note ; This signal is multiplexed

see

Note ; This signal is multiplexed

see

Table 2-4

30/111

Issue 1.0 - July 24, 2002

PIN DESCRIPTION

Pinout

Table 2-6.

Pin#

AE14

Pin Name

Pin#

AA26

Y24

Y25

Y26

W22

Pin Name

Pin#

R6

U21

AA10

AA12

AA14

Pin Name

VDD_CORE

TFTB5

PPD[3]

PPD[4]

PPD[5]

PPD[6]

PPD[7]

AB14

AC14

AF15

AE15

AD15

AC15

AD14

TFTLINE

TFTFRAME

TFTDE

TFTENVDD

TFTENVCC

TFTPWM

TFTDCLK

AC19

AD19

SCL / DDC[1]

SDA / DDC[0]

A2

A25

B1

B26

F7

F11

F20

G6

G21

H6

J21

K21

U6

V6

VDD

D21

A20

A18

A21

A19

E20

OC

C2

C1

D3

D2

D1

E4

E3

E2

E1

F5

F4

F3

F2

G5

G4

G2

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[5]

GPIO[6]

GPIO[7]

GPIO[8]

GPIO[9]

GPIO[10]

GPIO[11]

GPIO[12]

GPIO[13]

GPIO[14]

GPIO[15]

USBDMNS[0]

USBDMNS[1]

USBDPLS[0]

USBDPLS[1]

POWERON

AC22

AC24

AD21

AE24

AC21

AD25

AD22

AC26

AD23

AA22

AE22

AC25

AB21

AD26

AE23

AB23

CTS0#

CTS1#

DCD0#

DCD1#

DSR0#

DSR1#

DTR0#

DTR1#

RI0#

Y6

Y21

AA7

AA16

AA18

AA20

AE01

AE26

AF02

AF25

RI1#

RTS0#

RTS1#

RXD0

RXD1

TXD0

H2

J5

H5

H3

H1

TCLK

TRST

TDI

TMS

TDO

TXD1

A1

GND

G1

AD10

C25

SCAN_ENABLE

COL_SEL

SPKRD

A26

B2

B25

C3

C24

D4

D10

D16

D23

E5

AD20

AB19

AC20

AB20

KBCLK

KBDATA

MDATA

MCLK

AD16

Y23

VDD_DCLK_PLL

VDD_DEVCLK_PLL

VDD_HCLKI_PLL

VDD_HCLKO_PLL

VDD_MCLKI_PLL

VDD_MCLKO_PLL

VDD_PCICLK_PLL

AA23

W24

W23

W25

W26

V22

V24

V25

V26

U22

PE

SLCT

BUSY

ERR#

AE20

AB26

AE19

AE18

AE21

ACK#

E22

F6

F8

PDDIR

STROBE#

INIT#

AUTOFD#

SLCTIN#

PPD[0]

PPD[1]

PPD[2]

F13

F15

F17

K6

M21

N6

VDD_CORE

F9

F10

F12

F14

F16

F18

Y22

AA24

AA25

P21

1

Note ; This signal is multiplexed

see

Note ; This signal is multiplexed

see

Note ; This signal is multiplexed

see

Table 2-4

Issue 1.0 - July 24, 2002

31/111

PIN DESCRIPTION

Pinout

Table 2-6.

Pin#

F19

F21

H4

H21

H23

J6

Pin Name

Pin#

T11:16

T21

V21

V23

W4

W6

W21

AA6

AA8

Pin Name

Pin#

AC4

AC11

AC17

AC23

AD3

AD24

AE2

AE25

AF1

Pin Name

GND

L6

L11:16

L21

M6

M11:16 GND

N11:16 GND

N21

P6

P11:16

R11:16 GND

AA9

AF26

AA11

AA13

AA15

AA17

AA19

AA21

AB5

G3

F1

Reserved

GND

1

Note ; This signal is multiplexed

see

Table 2-4

R21

T6

GND

AB22

1

Note ; This signal is multiplexed

see

Note ; This signal is multiplexed

see

Table 2-4

32/111

Issue 1.0 - July 24, 2002

STRAP OPTION

3. STRAP OPTION

This chapter defines the STPC Atlas Strap

Options and their locations. Some strap options

are left programmable for future versions of

silicon. The strap options are sampled at a specific

point of the boot process. This is shown in detail in

Figure 4-3

Actual

Settings

Signal

Designation

Location

Set to ’0’ Set to ’1’

2

MD1

MD2

Reserved

Not accessible

Pull Up

-

Index 5F,bit 6 User defined

Index 5F,bit 7 User defined

HCLK Speed

See

Section 3.1.3.

Section 3.1.1.

MD3

PCI_CLKO Divisor

Index 4A,bit 1

Pull-up

See

MD[4]

MD[5]

MD[6]

MD[7]

MD[8]

MD[9]

MD10

MD11

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

MD32

MD33

MD34

MD35

MD36

MD37

MD38

MD40

MD41

MD42

MCLK Synchro (see

)

Index 4A,bit 2 User defined

Index 4A,bit 6 User defined

Async

Sync

Section 3.1.1.

PCI_CLKO Programming

ISA / PCMCIA / Local Bus

See

Section 3.1.1.

Index 4A,bit 7

Pull-down

Index 4A,bit 3 User defined

Section 3.1.1.

2

Reserved

Index 4B,bit 2

Index 4B,bit 3

Index 4B,bit 6

Not accessible

Pull down

Pull-up

-

2

Reserved

-

See

-

CPU clock Multiplication

Section 3.1.2.

2

Reserved

Pull up

-

2

Reserved

Pull up

-

PCI_CLKO Divisor

HCLK Pad Direction

MCLK Pad Direction

DCLK Pad Direction

Index 4A,bit 0 User defined

See

Section 3.1.1.

Index 4C,bit 2

Index 4C,bit 3

Pull-up

Input

Hi-Z

Input

-

Output

Index 4C,bit 4 User defined

Output

2

Reserved

Index 5F,bit 0

Index 5F,bit 2

Pull up

-

2

Reserved

-

Index 5F,bit 3 User defined

Index 5F,bit 4 User defined

Index 5F,bit 5 User defined

HCLK PLL Speed

See

Section 3.1.3.

2

Reserved

Not accessible

Pull up

-

2

Reserved

2

Reserved

Pull up

2

Reserved

Pull up

2

Reserved

Pull up

2

Reserved

Pull down

Pull up

2

Reserved

2

Reserved

Pull down

2

Reserved

Local Bus Boot Device Size

Index 4B,bit 0 User defined

8-bit

16-bit

2

Reserved

Not accessible

Pull down

-

2

Reserved

-

CPU clock Multiplication

Index 4B,bit 7 User defined

See

Section 3.1.2.

2

Reserved

Not accessible

Pull down

Pull up

-

2

Reserved

2

MD 43

1

Reserved

Pull down

Note : Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,

PCMCIA, Local Bus).

2

Note : Must be implemented.

Issue 1.0 - July 24, 2002

33/111

STRAP OPTION

Actual

Settings

Signal

Designation

Location

Set to ’0’ Set to ’1’

MD 45

Not accessible User defined

CPUCLK/HCKL Deskew Programming

See

Section 3.1.5.

MD 46

MD 47

MD 48

MD 50

MD 51

MD 52

MD 53

2

Reserved

Not accessible

Pull down

Pull up

-

2

Reserved

Internal UART2 (see

Internal UART1 (see

)

Index 4C,bit 0 User defined

Index 4C,bit 1 User defined

Index 4C,bit 6 User defined

Index 4C,bit 7 User defined

Disable

Enable

Section 3.1.4.

Disable

Enable

Internal Kbd / Mouse (see

)

Disable

Enable

Section 3.1.4.

Internal Parallel Port (see

)

Disable

Enable

1

2

TC

Reserved

Hardware

Pull up

-

1

2

DACK_ENC[2]

DACK_ENC[1]

DACK_ENC[0]

1

Note : Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,

PCMCIA, Local Bus).

2

Note : Must be implemented.

34/

111

Issue 1.0 - July 24, 2002

STRAP OPTION

3.1. STRAP OPTION REGISTER DESCRIPTION

3.1.1. STRAP REGISTER 0

This register is read only.

STRAP0

7

Access = 0022h/0023h

Regoffset =04Ah

6

5

4

3

2

1

0

MD[7]

MD[6]

MD[9]

MD[8]

RSV

MD[5]

MD[4]

MD[17]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Mnemonic

Description

PCICLK PLL set-up: The value sampled on MD[7:6] controls the PCICLK

PLL programming according to the PCICLK frequency.

MD7 MD6

Bits 7-6

MD[7:6]

0

1

0

1

X

PCICLK frequency between 16 & 32 MHz

PCICLK frequency between 32 & 64 MHz

Reserved

Mode selection:

MD9 MD8

0

1

0 ISA mode: ISA enabled, PCMCIA & Local Bus disabled

Bits 5-4

MD[9:8]

1 PCMCIA mode: PCMCIA enabled, ISA & Local Bus disabled

0 Local Bus mode: Local Bus enabled, ISA & PCMCIA disabled

1 Reserved

Bit 3

Bit 2

Rsv

Reserved

Host Memory synchronization. This bit reflects the value sampled on

[MD5] and controls the MCLK/HCLK synchronization.

0: MCLK and HCLK not synchronized

MD[5]

1: MCLK and HCLK synchronized.

PCICLK division: These bits reflect the values sampled on [MD4] and

MD[17] to select the PCICLK frequency.

MD4 MD17

Bits 1-0

MD[4], MD[17]

0

1

X

0

1

PCI Clock output = HCLK / 4

PCI Clock output = HCLK / 3

PCI Clock output = HCLK / 2

Issue 1.0 - July 24, 2002

35/111

STRAP OPTION

3.1.2. STRAP REGISTER 1

This register is read only.

STRAP1

Access = 0022h/0023h

Regoffset =04Bh

7

6

5

4

3

2

1

0

MD[40]

MD[14]

RSV

MD[36]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Mnemonic

Description

CPU Clock Multiplication (486 mode):

MD14 MD40

1

0

1

X 1

X 2

Bits 7-6

MD[40] & MD[14]

All other settings are reserved

HCLK maximum speed is 66MHz and in CPU mode X2.

Operation in X1 mode is only guaranteed up to 66MHz.

Bits 5-1

Bit 0

Rsv

Reserved

These bits reflect the values sampled on MD[36] and determines the

Local Bus Boot device width:

0: 8-bit Boot Device

1: 16-bit Boot Device

MD[36]

36/

111

Issue 1.0 - July 24, 2002

STRAP OPTION

3.1.3. HCLK PLL STRAP REGISTER

This register is read only.

HCLK_STRAP0

Access = 0022h/0023h

Regoffset =05Fh

7

6

5

4

3

2

1

0

RSV

MD[26]

MD[25]

MD[24]

RSV

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Mnemonic

Description

Bits 7-6

Rsv

These bits are fixed to ‘0’

These pins reflect the values sampled on MD[26:24] pins respectively

Bits 5-3

Bits 2-0

MD[26:24]

Rsv

and control the Host clock frequency synthesizer as shown in

Table 3-1

Reserved

Table 3-1. HCLK Frequency Configuration

MD[3]

MD[2]

MD[26]

MD[25]

MD[24]

HCLK Speed

0

1

0

1

25 MHz

50 MHz

60 MHz

66 MHz

0

1

All other settings are reserved

Issue 1.0 - July 24, 2002

37/111

STRAP OPTION

3.1.4. STRAP REGISTER 2

This register is read only with the exception of bit 4

STRAP2

7

Access = 0022h/0023h

Regoffset =04Ch

6

5

4

3

2

1

0

MD[53]

MD[52]

RSV

MD[20]

MD[19]

MD[18]

MD[51]

MD[50]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Mnemonic

Description

This bit reflects the value sampled on MD[53] pin and determines

whether the internal Parallel Port Controller is used

0: Internal Parallel Port Controller is disabled

1: Internal Parallel Port Controller is enabled

Bit 7

MD[53]

This bit reflects the value sampled on MD[52] pin and determines

whether the internal Keyboard controller is used

0: Internal Keyboard Controller is disabled

Bit 6

Bit 5

Bit 4

MD[52]

Rsv

1: Internal Keyboard Controller is enabled

Reserved

This bit reflects the value sampled on MD[20] pin and controls the Dot

clock pin (DCLK) direction as follows:

MD[20]

0: Input.

1: Output of the internal frequency synthesizer DCLK PLL.

This bit reflects the value sampled on MD[19] pin and controls the

Memory clock output pin (MCLKO) as follows:

0: Tristated.

Bit 3

Bit 2

Bit 1

Bit 0

MD[19]

MD[18]

MD[51]

MD[50]

1: Output of the internal frequency synthesizer MCLKO PLL.

This bit reflects the value sampled on MD[18] pin and controls the Host

clock pin (HCLK) direction as follows:

0: Input.

1: Output of the internal frequency synthesizer HCLK PLL.

This bit reflects the value sampled on MD[51] pin and determines

whether the internal UART1 is enabled:

0: Internal UART1 is disabled

1: Internal UART1 is enabled

This bit reflects the value sampled on MD[50] pin and determines

whether the internal UART2 is enabled:

0: Internal UART2 is disabled

1: Internal UART2 is enabled

38/

111

Issue 1.0 - July 24, 2002

STRAP OPTION

3.1.5.

CPUCLK/HCKL

DESKEW

PROGRAMMING

;

MD[45]

MD[46]

Description

HCLK between 33MHz and

64MHz

1

0

HCLK between 64MHz and

133MHz

0

1

All other settings are reserved

Table 3-1.

Note that these straps are not accessible by

software.

Issue 1.0 - July 24, 2002

39/111

STRAP OPTION

3.2. TYPICAL STRAP OPTION

IMPLEMENTATION

Host Clock Frequency of 66MHz in X2 mode with

internal keyboard/mouse, UARTS and parallel

port enabled.

Table Table 3-1.shows the detailed Strap options

required to boot the STPC in ISA mode with a

Actual

Signal

Designation

Description

Settings

2

MD1

MD2

Reserved

Pull Up

Pull down

Pull up

-

HCLK Speed

HCLK = 66MHz

MD3

PCI_CLKO Divisor

PCICLK = HCLK/2

Asynchronous

MD[4]

MD[5]

MD[6]

MD[7]

MD[8]

MD[9]

MD10

MD11

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

MD32

MD33

MD34

MD35

MD36

MD37

MD38

MD40

MD41

MD42

MCLK Synchro (see

)

Pull down

Pull up

Section 3.1.1.

PCICLK PLL Window =

32MHz - 64MHz

PCI_CLKO Programming

ISA / PCMCIA / Local Bus

Pull down

Pull up

ISA Mode

2

Reserved

-

2

Reserved

-

CPU clock Multiplication

X2 Mode

2

Reserved

Pull up

-

2

Reserved

Pull up

-

PCI_CLKO Divisor

HCLK Pad Direction

MCLK Pad Direction

DCLK Pad Direction

Pull up

PCICLK = HCLK/2

Pull up

Output

Pull up

Output

Pull up

Output

2

Reserved

Pull up

-

2

Reserved

Pull up

HCLK PLL Speed

Pull up

HCLK = 66MHz

Pull down

Pull up

2

Reserved

-

2

Reserved

Pull up

2

Reserved

Pull up

2

Reserved

Pull up

2

Reserved

Pull up

2

Reserved

Pull down

Pull up

2

Reserved

2

Reserved

Pull down

User defined

Pull down

Pull up

2

Reserved

Local Bus Boot Device Size

Not Applicable

2

Reserved

-

2

Reserved

-

CPU clock Multiplication

X2 mode

2

Reserved

Pull down

Pull up

-

2

Reserved

2

MD 43

1

Reserved

Pull down

Note : Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,

PCMCIA, Local Bus).

2

Note : Must be implemented.

Typical Strap Option Implementation

Table 3-1.

40/

111

Issue 1.0 - July 24, 2002

STRAP OPTION

Actual

Settings

Signal

Designation

Description

MD 45

MD 46

MD 47

MD 48

MD 50

MD 51

MD 52

MD 53

Pull down

Pull up

Pull down

Pull up

HCLK between 64MHz and

133MHz

CPUCLK/HCKL Deskew Programming

2

Reserved

-

2

Reserved

-

Internal UART2 (see

Internal UART1 (see

)

Enable

Section 3.1.4.

Enable

Internal Kbd / Mouse (see

)

Enable

Section 3.1.4.

Internal Parallel Port (see

)

Enable

1

2

TC

Reserved

-

1

2

DACK_ENC[2]

DACK_ENC[1]

DACK_ENC[0]

1

Note : Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,

PCMCIA, Local Bus).

2

Note : Must be implemented.

Typical Strap Option Implementation

Table 3-1.

Issue 1.0 - July 24, 2002

41/111

STRAP OPTION

42/

111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

4. ELECTRICAL SPECIFICATIONS

4.1. INTRODUCTION

4.2.3. RESERVED DESIGNATED PINS

Pins designated as reserved should be left dis-

connected. Connecting a reserved pin to a pull-up

resistor, pull-down resistor, or an active signal

could cause unexpected results and possible

circuit malfunctions.

The electrical specifications in this chapter are

valid for the STPC Atlas.

4.2. ELECTRICAL CONNECTIONS

4.2.1.

POWER/GROUND

CONNECTIONS/

4.3. ABSOLUTE MAXIMUM RATINGS

DECOUPLING

The following table lists the absolute maximum

ratings for the STPC Atlas device. Stresses

beyond those listed under Table 4-1 limits may

cause permanent damage to the device. These

are stress ratings only and do not imply that

operation under any conditions other than those

specified in section "Operating Conditions".

Due to the high frequency of operation of the

STPC Atlas, it is necessary to install and test this

device using standard high frequency techniques.

The high clock frequencies used in the STPC

Atlas and its output buffer circuits can cause

transient power surges when several output

buffers switch output levels simultaneously. These

effects can be minimized by filtering the DC power

leads with low-inductance decoupling capacitors,

using low impedance wiring, and by utilizing all of

the VSS and VDD pins.

Exposure to conditions beyond those outlined in

Table 4-1 may (1) reduce device reliability and (2)

result in premature failure even when there is no

immediately apparent sign of failure. Prolonged

exposure to conditions at or near the absolute

maximum ratings (Table 4-1) may also result in

reduced useful life and reliability.

4.2.2. UNUSED INPUT PINS

No unused input pin should be left unconnected

unless they have an integrated pull-up or pull-

down. Connect active-low inputs to VDD through a

20 kΩ (±10%) pull-up resistor and active-high

inputs to VSS. For bi-directionnal active-high

inputs, connect to VSS through a 20 kΩ (±10%)

pull-up resistor to prevent spurious operation.

4.3.1. 5V TOLERANCE

The STPC is capable of running with I/O systems

that operate at 5 V such as PCI and ISA devices.

Certain pins of the STPC tolerate inputs up to

5.5 V. Above this limit the component is likely to

sustain permanent damage.

All 5 volt tolerant pins are outlined in Table 2-3

Buffer Type Descriptions.

Table 4-1. Absolute Maximum Ratings

Symbol

Parameter

Minimum

Maximum

4.0

Units

V

DC Supply Voltage

-0.3

-

DDx

V

DC Supply Voltage for Core

Digital Input and Output Voltage

5Volt Tolerance

2.7

V

CORE

V , V

VDD + 0.3

5.5

V

I

O

V

5T

V

T

ESD Capacity (Human body mode)

Storage Temperature

2000

+150

+85

V

ESD

STG

-40

0

°C

W

T

Operating Temperature (Note 1)

OPER

-40

-

+115

4.8

P

Maximum Power Dissipation (package)

TOT

Note 1: The figures specified apply to the Tcase of a

STPC device that is soldered to a board, as detailed in

the Design Guidelines Section, for Commercial and In-

dustrial temperature ranges.

Issue 1.0 - July 24, 2002

43/111

ELECTRICAL SPECIFICATIONS

4.4. DC CHARACTERISTICS

Table 4-2. DC Characteristics

Symbol

Parameter

3.3V Operating Voltage

2.5V Operating Voltage

3.3V Supply Power

Test conditions

Min

3.0

Typ

3.3

2.5

Max

3.6

Unit

V

DD

V

2.45

2.7

V

CORE

P

3.0V < V < 3.6V

0.24

4.1

W

V

DD

1

P

2.5V Supply Power

2.45V < V

< 2.7V

CORE

Except XTALI

XTALI

-0.3

2.1

0.8

V

Input Low Voltage

Input High Voltage

IL

0.8

V

Except XTALI

XTALI

V

+0.3

V

DD

V

IH

2.35

-5

+0.3

V

DD

I

Input Leakage Current

Integrated Pull up/down

Input, I/O

5

µA

KΩ

LK

50

Note 1; Power consumption is heavily dependant on the clock frequencies and on the enabled features. See details in

Table 4-5 to Table 4-8.

Table 4-3. PAD buffers DC Characteristics

I/O

count

V

min V max V min V max I min I max C

max Derating

C

IN

(pF)

IH

IL

OH

OL

OH

load

Buffer Type

1

(V)

(mA)

(pF)

(ps/pF)

ANA

10

2

2.35

0.9

0.8

-

2.4

-

0.4

0.1*V

0.4

-

2

-

- 2

- 4

- 8

- 4

- 8

- 0.5

-14

-16

-

OSCI13B

2.1

-

50

-

BT4CRP

1

0.85*V

2.4

4

100

200

100

200

100

400

-

30

21

42

41

42

23

21

15

71

12

-

5.61

6.89

5.97

5.83

5.96

7.02

7.03

6.97

6.20

9.34

5.97

DD

BT8TRP_TC

7

-

8

BD4STRP_FT

BD4STRUP_FT

BD4STRP_TC

BD8STRP_FT

BD8STRUP_FT

BD8STRP_TC

BD8TRP_TC

64

14

26

30

47

12

53

2

0.8

0.3*V

0.8

2.4

4

2.4

4

2.4

4

2.4

8

2.4

8

2.4

8

2.4

8

BD8PCIARP_FT

BD14STARP_FT

BD16STARUQP_TC

SCHMITT_FT

TLCHT_FT

50 0.5*V

0.9*V

1.5

14

16

-

DD

18

19

1

2

2.4

-

16

1

-

TLCHT_TC

-

TLCHTD_TC

1

-

TLCHTU_TC

1

-

USBDS_2V5 (slow)

USBDS_2V5 (fast)

45.2

98.8

4

2

0.8

2.4

0.4

-

100

8.41

Note 1: time to output variation depending on the capacitive load.

Table 4-4. RAMDAC DC Specification

Parameter

Symbol

Vref_dac

INL

DNL

BLC

Min

1.00 V

Max

Voltage Reference

1.24 V

3 LSB

1 LSB

2.0 mA

Integrated Non Linear Error

Differentiated Non Linear Error

Black Level Current

-

1.0 mA

44/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

Table 4-4. RAMDAC DC Specification

Symbol

Parameter

Min

Max

WLC

White Level Current

15.00 mA

18.50 mA

Table 4-5. VGA RAMDAC Power Consumption

DCLK

DAC mode

P

(mW)

Max

VDD_DAC = 2.45V

VDD_DAC = 2.7V

(MHz)

-

6.25 - 135

(State)

Shutdown

Active

0

150

0

180

Table 4-6. 2.5V Power Consumptions (V

+ VDD_x_PLL + VDD_DAC)

CORE

HCLK

(MHz)

CPUCLK

(MHz)

MCLK

(MHz)

DCLK

(MHz)

PMU

P

(W)

Max

Mode

V

=2.45V

V

=2.7V

2.5V

(State)

2.5V

Stop Clock

Full Speed

Stop Clock

Full Speed

Stop Clock

Full Speed

Stop Clock

Full Speed

1.5

2.5

2.1

1.9

2.8

2.5

3.3

1.9

Stopped

135

3.0

2.6

3.6

2.4

3.5

3.1

4.1

66

133 (x2)

66

90

SYNC

Stopped

135

ASYNC

Note 1: PCI clock at 33MHz

Table 4-7. 3.3V Power Consumptions (V

)

DD

HCLK

(MHz)

CPUCLK

MCLK

(MHz)

DCLK

PMU

P

Max

(mW)

(MHz)

6.26

135

6.26

135

(State)

130

215

150

240

66

133 (x2)

66

90

Full Speed

133 (x2)

Table 4-8. PLL Power Consumptions

P

(mW)

Max

PLL name

VDD_PLL = 2.45V

VDD_PLL = 2.7V

VDD_DCLK_PLL

VDD_DEVCLK_PLL

VDD_HCLKI_PLL

VDD_HCLKO_PLL

VDD_MCLKI_PLL

VDD_MCLKO_PLL

VDD_PCICLK_PLL

5

10

Issue 1.0 - July 24, 2002

45/111

ELECTRICAL SPECIFICATIONS

4.5. AC CHARACTERISTICS

are shown in Table 4-9 below. Input or output

signals must cross these levels during testing.

This section lists the AC characteristics of the

STPC interfaces including output delays, input

setup requirements, input hold requirements and

output float delays. These measurements are

based on the measurement points identified in

Figure 4-1 and Figure 4-2. The rising clock edge

reference level VREF and other reference levels

Figure 4-1 shows output delay (A and B) and input

setup and hold times (C and D). Input setup and

hold times (C and D) are specified minimums,

defining the smallest acceptable sampling window

a synchronous input signal must be stable for

correct operation.

Table 4-9. Drive Level and Measurement Points for Switching Characteristics

Symbol

Value

1.5

Units

V

REF

V

2.5

IHD

V

0.0

ILD

Note: Refer to Figure 4-1.

Figure 4-1. Drive Level and Measurement Points for Switching Characteristics

Tx

V

IHD

CLK:

Ref

ILD

V

A

MAX

B

MIN

Valid

Output n

Valid

Output n+1

V

OUTPUTS:

Ref

C

D

V

IHD

Valid

Input

INPUTS:

LEGEND:

Ref

ILD

V

A - Maximum Output Delay Specification

B - Minimum Output Delay Specification

C - Minimum Input Setup Specification

D - Minimum Input Hold Specification

46/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

Figure 4-2. CLK Timing Measurement Points

T1

T2

V

IH (MIN)

V

Ref

IL (MAX)

CLK

T5

T3

T4

T1 - One Clock Cycle

T2 - Minimum Time at V

LEGEND:

IH

IL

T3 - Minimum Time at V

T4 - Clock Fall Time

T5 - Clock Rise Time

NOTE; All sIgnals are sampled on the rising edge of the CLK.

Issue 1.0 - July 24, 2002

47/111

ELECTRICAL SPECIFICATIONS

4.5.1. POWER ON SEQUENCE

Strap Options are continuously sampled during

SYSRSTI# low and must remain stable. Once

SYSRSTI# is high, they MUST NOT CHANGE

until SYSRSTO# goes high.

Figure 4-3 describes the power-on sequence of

the STPC, also called cold reset.

There is no dependency between the different

power supplies and there is no constraint on their

rising time.

Bus activity starts only few clock cycles after the

release of SYSRSTO#. The toggling signals

depend on the STPC configuration.

In ISA mode, activity is visible on PCI prior to the

ISA bus as the controller is part of the south

bridge.

In Local Bus mode, the PCI bus is not accessed

and the Flash Chip Select is the control signal to

monitor.

SYSRSTI# as no constraint on its rising edge but

must stay active until power supplies are all within

µ

margin of 10 s is even

specifications,

a

recommended to let the STPC PLLs and strap

options stabilize.

Figure 4-3. Power-on timing diagram

Power Supplies

14 MHz

> 10 us

1.6 V

SYSRSTI#

ISACLK

VALID CONFIGURATION

Strap Options

HCLK

PCI_CLK

2.3 ms

SYSRSTO#

48/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

4.5.2 RESET SEQUENCE

It is mandatory to have a clean reset pulse without

glitches as the STPC could then sample invalid

strap option setting and enter into an umpredicta-

ble mode.

Figure 4-4 describes the reset sequence of the

STPC, also called warm reset.

The constraints on the strap options and the bus

activities are the same as for the cold reset.

The SYSRSTI# pulse duration must be long

enough to have all the strap options stabilized and

must be adjusted depending on resistor values.

While SYSRSTI# is active, the PCI clock PLL runs

in open loop mode at a speed of few 100’s KHz.

Figure 4-4. Reset timing diagram

14 M Hz

1.6 V

SYSRSTI#

ISACLK

M D[63:0]

Strap Options

HCLK

VALID CONFIGURATION

PCI_CLK

SYSRSTO#

2.3 ms

Issue 1.0 - July 24, 2002

49/111

ELECTRICAL SPECIFICATIONS

4.5.3. SDRAM INTERFACE

MCLKx clocks are the input clock of the SDRAM

devices.

Figure 4-5, Table 4-10, Table 4-11 lists the AC

characteristics of the SDRAM interface. The

Figure 4-5. SDRAM Timing Diagram

MCLKx

MCLKI

T

delay

T

low

high

T

cycle

STPC.output

STPC.input

T

output (min)

output (max)

T

setup

hold

Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range

Max

Unit

ns

Name

Tcycle

Thigh

Tlow

Parameter

Min

10

4

Typ

MCLKI Cycle Time

MCLKI High Time

MCLKI Low Time

4

MCLKI Rising Time

1

MCLKI Falling Time

2.1

Tdelay

MCLKx to MCLKI delay

MCLKI to RAS# Valid

MCLKI to CAS# Valid

MCLKI to CS# Valid

1.6

5.2

1.6

1.35

1.6

Toutput

MCLKI to DQM[ ] Outputs Valid

MCLKI to MD[ ] Outputs Valid

MCLKI to MA[ ] Outputs Valid

MCLKI to MWE# Valid

MD[63:0] setup to MCKLI

MD[63:0] hold from MCKLI

1.6

7.5

Tsetup

Thold

-0.36

Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK not activated

The PC100 memory is recommended to reach

90MHz operation.

50/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

Table 4-11. SDRAM Bus AC Timings - Industrial Temperature Range

Max

Unit

ns

Name

Tcycle

Thigh

Tlow

Parameter

Min

11

4

Typ

MCLKI Cycle Time

MCLKI High Time

MCLKI Low Time

4

MCLKI Rising Time

1

MCLKI Falling Time

1.8

Tdelay

MCLKx to MCLKI delay

MCLKI to RAS# Valid

MCLKI to CAS# Valid

MCLKI to CS# Valid

1.7

2

6.5

6

Toutput

MCLKI to DQM[ ] Outputs Valid

MCLKI to MD[ ] Outputs Valid

MCLKI to MA[ ] Outputs Valid

MCLKI to MWE# Valid

MD[63:0] setup to MCKLI

MD[63:0] hold from MCKLI

2

7.8

6.5

6

1.7

7.5

-0.36

Tsetup

Thold

Note: These timings are for a load of 50pF, part running at 90MHz and ReadCLK not activated

The PC100 memory is recommended to reach

90MHz operation.

Issue 1.0 - July 24, 2002

51/111

ELECTRICAL SPECIFICATIONS

4.5.4. PCI INTERFACE

Figure 4-6 and Table 4-12 list the AC characteris-

tics of the PCI interface. PCICLKx stands for any

PCI device clock input.

Figure 4-6. PCI Timing Diagram

HCLK

PCICLKx

PCICLKI

T

clkx

T

low

high

T

hclk

T

cycle

STPC.output

STPC.input

T

output (min)

output (max)

T

setup

hold

Table 4-12. PCI Bus AC Timings

Min

Typ

5.0

7.5

0.3

Max

5.7

8.5

1.0

Unit

ns

Name

Parameter

HCLK to PCICLKO delay (MD[30:27] = 1111)

HCLK to PCICLKI delay

PCICLKI to PCICLKx skew

PCICLKI Cycle Time

PCICLKI High Time

4.4

6.5

-0.5

30

Thclk

Tclkx

Tcycle

Thigh

Tlow

13

PCICLKI Low Time

13

PCICLKI Rising Time

PCICLKI Falling Time

PCICLKI to any output

Setup to PCICLKI

1.5

-

Hold from PCICLKI

HCLK to any output

-

Setup to HCLK

Hold from HCLK

Note: These timings are for a load of 50pF.

52/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

4.5.5 IPC INTERFACE

Table 4-13 lists the AC characteristics of the IPC

interface.

Figure 4-7. IPC timing diagram

ISACLK2X

ISACLK

T

dly

T

setup

IRQ_MUX[3:0]

DREQ_MUX[1:0]

Table 4-13. IPC Interface AC Timings

Name

Parameter

ISACLK2X to ISACLK delay

Min

Max

Unit

nS

T

dly

ISACLK2X to DACK_ENC[2:0] valid

ISACLK2X to TC valid

nS

T

IRQ_MUX[3:0] Input setup to ISACLK2X

DREQ_MUX[1:0] Input setup to ISACLK2X

0

-

nS

setup

Issue 1.0 - July 24, 2002

53/111

ELECTRICAL SPECIFICATIONS

4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS

Table 4-8 and Table 4-14 list the AC characteris-

tics of the ISA interface.

Figure 4-8 ISA Cycle (ref Table 4-14)

2

15

38

37

14

13

9

12

25

56

18

29

ALE

AEN

22

Valid AENx

3

34

33

LA [23:17]

SA [19:0]

Valid Address

42

11

24

41

57

10

27

Valid Address, SBHE*

26

23

55

58

59

48

47

28

61

64

CONTROL (Note 1)

IOCS16#

MCS16#

54

IOCHRDY

READ DATA

WRITE DATA

V.Data

VALID DATA

Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.

The clock has not been represented as it is dependent on the ISA Slave mode.

Table 4-14. ISA Bus AC Timing

Name

Parameter

Min

Max

Units

2

LA[23:17] valid before ALE# negated

5T

Cycles

3

LA[23:17] valid before MEMR#, MEMW# asserted

3a Memory access to 16-bit ISA Slave

3b Memory access to 8-bit ISA Slave

5T

1T

Cycles

9

SA[19:0] & SBHE valid before ALE# negated

SA[19:0] & SBHE valid before MEMR#, MEMW# asserted

10a Memory access to 16-bit ISA Slave

10b Memory access to 8-bit ISA Slave

SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted

10c Memory access to 16-bit ISA Slave

10

2T

Cycles

10

2T

Cycle

Table 4-8

Note: The signal numbering refers to

54/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

Table 4-14. ISA Bus AC Timing

Name

Parameter

10d Memory access to 8-bit ISA Slave

Min

2T

Max

Units

Cycle

Cycles

10e

SA[19:0] & SBHE valid before IOR#, IOW# asserted

ISACLK2X to IOW# valid

2T

11

11a Memory access to 16-bit ISA Slave - 2BCLK

11b Memory access to 16-bit ISA Slave - Standard 3BCLK

11c Memory access to 16-bit ISA Slave - 4BCLK

11d Memory access to 8-bit ISA Slave - 2BCLK

Memory access to 8-bit ISA Slave - Standard 3BCLK

ALE# asserted before ALE# negated

2T

1T

Cycles

11e

12

13

ALE# asserted before MEMR#, MEMW# asserted

13a Memory Access to 16-bit ISA Slave

13b Memory Access to 8-bit ISA Slave

ALE# asserted before SMEMR#, SMEMW# asserted

13c Memory Access to 16-bit ISA Slave

13d Memory Access to 8-bit ISA Slave

ALE# asserted before IOR#, IOW# asserted

ALE# asserted before AL[23:17]

2T

Cycles

13

2T

Cycles

13e

14

14a Non compressed

15T

Cycles

14b Compressed

15

ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated

15a Memory Access to 16-bit ISA Slave- 4 BCLK

15e Memory Access to 8-bit ISA Slave- Standard Cycle

ALE# negated before LA[23:17] invalid (non compressed)

ALE# negated before LA[23:17] invalid (compressed)

MEMR#, MEMW# asserted before LA[23:17]

11T

14T

Cycles

18a

22

22a Memory access to 16-bit ISA Slave.

13T

Cycles

22b Memory access to 8-bit ISA Slave.

23

24

MEMR#, MEMW# asserted before MEMR#, MEMW# negated

23b Memory access to 16-bit ISA Slave Standard cycle

23e Memory access to 8-bit ISA Slave Standard cycle

9T

Cycles

SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated

23h Memory access to 16-bit ISA Slave Standard cycle

23l Memory access to 16-bit ISA Slave Standard cycle

IOR#, IOW# asserted before IOR#, IOW# negated

23o Memory access to 16-bit ISA Slave Standard cycle

23r Memory access to 8-bit ISA Slave Standard cycle

MEMR#, MEMW# asserted before SA[19:0]

9T

Cycles

9T

Cycles

24b Memory access to 16-bit ISA Slave Standard cycle

24d Memory access to 8-bit ISA Slave - 3BLCK

24e Memory access to 8-bit ISA Slave Standard cycle

24f Memory access to 8-bit ISA Slave - 7BCLK

SMEMR#, SMEMW# asserted before SA[19:0]

10T

Cycles

24

24h

24i

Memory access to 16-bit ISA Slave Standard cycle

Memory access to 16-bit ISA Slave - 4BCLK

Memory access to 8-bit ISA Slave - 3BCLK

Memory access to 8-bit ISA Slave Standard cycle

10T

Cycles

24k

24l

Table 4-8

Note: The signal numbering refers to

Issue 1.0 - July 24, 2002

55/111

ELECTRICAL SPECIFICATIONS

Table 4-14. ISA Bus AC Timing

Name

24

Parameter

IOR#, IOW# asserted before SA[19:0]

Min

Max

Units

24o

24r

I/O access to 16-bit ISA Slave Standard cycle

19T

Cycles

25

MEMR#, MEMW# asserted before next ALE# asserted

25b

25d

Memory access to 16-bit ISA Slave Standard cycle

Memory access to 8-bit ISA Slave Standard cycle

10T

Cycles

SMEMR#, SMEMW# asserted before next ALE# asserted

25e

25f

Memory access to 16-bit ISA Slave - 2BCLK

Memory access to 16-bit ISA Slave Standard cycle

Memory access to 8-bit ISA Slave Standard cycle

10T

Cycles

25h

25

26

28

IOR#, IOW# asserted before next ALE# asserted

25i

I/O access to 16-bit ISA Slave Standard cycle

10T

Cycles

25k

MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted

26b

26d

Memory access to 16-bit ISA Slave Standard cycle

Memory access to 8-bit ISA Slave Standard cycle

12T

Cycles

SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted

26f

Memory access to 16-bit ISA Slave Standard cycle

Memory access to 8-bit ISA Slave Standard cycle

12T

Cycles

26h

IOR#, IOW# asserted before next IOR#, IOW# asserted

26i

I/O access to 16-bit ISA Slave Standard cycle

I/O access to 8-bit ISA Slave Standard cycle

12T

Cycles

26k

Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted

28a

28b

Memory access to 16-bit ISA Slave

Memory access to 8-bit ISA Slave

3T

Cycles

Any command negated to IOR#, IOW# asserted

28c I/O access to ISA Slave

3T

1T

Cycles

29a

29b

29c

33

MEMR#, MEMW# negated before next ALE# asserted

SMEMR#, SMEMW# negated before next ALE# asserted

IOR#, IOW# negated before next ALE# asserted

LA[23:17] valid to IOCHRDY negated

33a

33b

Memory access to 16-bit ISA Slave - 4 BCLK

Memory access to 8-bit ISA Slave - 7 BCLK

8T

Cycles

14T

34

37

LA[23:17] valid to read data valid

34b

34e

Memory access to 16-bit ISA Slave Standard cycle

Memory access to 8-bit ISA Slave Standard cycle

8T

Cycles

14T

ALE# asserted to IOCHRDY# negated

37a

37b

37c

37d

Memory access to 16-bit ISA Slave - 4 BCLK

Memory access to 8-bit ISA Slave - 7 BCLK

I/O access to 16-bit ISA Slave - 4 BCLK

I/O access to 8-bit ISA Slave - 7 BCLK

6T

12T

6T

Cycles

12T

38

ALE# asserted to read data valid

38b

38e

38h

38l

Memory access to 16-bit ISA Slave Standard Cycle

Memory access to 8-bit ISA Slave Standard Cycle

I/O access to 16-bit ISA Slave Standard Cycle

I/O access to 8-bit ISA Slave Standard Cycle

4T

10T

4T

Cycles

10T

Table 4-8

Note: The signal numbering refers to

56/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

Table 4-14. ISA Bus AC Timing

Name

41

Parameter

SA[19:0] SBHE valid to IOCHRDY negated

Min

Max

Units

41a

41b

41c

41d

Memory access to 16-bit ISA Slave

Memory access to 8-bit ISA Slave

I/O access to 16-bit ISA Slave

I/O access to 8-bit ISA Slave

6T

12T

6T

Cycles

12T

42

47

48

54

SA[19:0] SBHE valid to read data valid

42b

42e

42h

42l

Memory access to 16-bit ISA Slave Standard cycle

Memory access to 8-bit ISA Slave Standard cycle

I/O access to 16-bit ISA Slave Standard cycle

I/O access to 8-bit ISA Slave Standard cycle

4T

10T

4T

Cycles

10T

MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated

47a

47b

47c

47d

Memory access to 16-bit ISA Slave

Memory access to 8-bit ISA Slave

I/O access to 16-bit ISA Slave

I/O access to 8-bit ISA Slave

2T

5T

2T

5T

Cycles

MEMR#, SMEMR#, IOR# asserted to read data valid

48b

48e

48h

48l

Memory access to 16-bit ISA Slave Standard Cycle

Memory access to 8-bit ISA Slave Standard Cycle

I/O access to 16-bit ISA Slave Standard Cycle

I/O access to 8-bit ISA Slave Standard Cycle

2T

5T

2T

5T

Cycles

IOCHRDY asserted to read data valid

54a

54b

54c

54d

Memory access to 16-bit ISA Slave

Memory access to 8-bit ISA Slave

I/O access to 16-bit ISA Slave

I/O access to 8-bit ISA Slave

1T(R)/2T(W)

Cycles

IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, SMEMW#,

IOR#, IOW# negated

55a

1T

Cycles

55b

56

57

58

59

61

IOCHRY asserted to MEMR#, SMEMR# negated (refresh)

IOCHRDY asserted to next ALE# asserted

1T

2T

0T

Cycles

IOCHRDY asserted to SA[19:0], SBHE invalid

MEMR#, IOR#, SMEMR# negated to read data invalid

MEMR#, IOR#, SMEMR# negated to data bus float

Write data before MEMW# asserted

61a

Memory access to 16-bit ISA Slave

2T

Cycles

Memory access to 8-bit ISA Slave (Byte copy at end of

start)

61b

61

Write data before SMEMW# asserted

61c

61d

Memory access to 16-bit ISA Slave

Memory access to 8-bit ISA Slave

2T

Cycles

Write Data valid before IOW# asserted

61e

61f

I/O access to 16-bit ISA Slave

I/O access to 8-bit ISA Slave

2T

1T

Cycles

64a

MEMW# negated to write data invalid - 16-bit

MEMW# negated to write data invalid - 8-bit

SMEMW# negated to write data invalid - 16-bit

SMEMW# negated to write data invalid - 8-bit

64b

64c

64d

Table 4-8

Note: The signal numbering refers to

Issue 1.0 - July 24, 2002

57/111

ELECTRICAL SPECIFICATIONS

Table 4-14. ISA Bus AC Timing

Name

Parameter

Min

Max

Units

64e

IOW# negated to write data invalid

1T

Cycles

MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte

by ISA Master

64f

1T

Cycles

IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by

ISA Master

64g

Table 4-8

Note: The signal numbering refers to

58/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

4.5.7 LOCAL BUS INTERFACE

Figure 4-3 to Figure 4-12 and Table 4-16 list the

AC characteristics of the Local Bus interface.

Figure 4-9. Synchronous Read Cycle

HCLK

PA[ ] bus

CSx#

T

hold

setup

active

BE#[1:0]

PRD#

PD[15:0]

Figure 4-10. Asynchronous Read Cycle

HCLK

PA[ ] bus

CSx#

T

hold

setup

end

BE#[1:0]

PRD#

PD[15:0]

PRDY

Issue 1.0 - July 24, 2002

59/111

ELECTRICAL SPECIFICATIONS

Figure 4-11. Synchronous Write Cycle

HCLK

PA[ ] bus

CSx#

T

hold

setup

active

BE#[1:0]

PWR#

PD[15:0]

Figure 4-12. Asynchronous Write Cycle

HCLK

PA[ ] bus

CSx#

T

hold

setup

end

BE#[1:0]

PWR#

PD[15:0]

PRDY

60/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

The Table 4-15 below refers to Vh, Va, Vs which

are the register value for Setup time, Active Time

and Hold time, as described in the Programming

Manual.

Table 4-15. Local Bus cycle lenght

Cycle

T

Unit

setup

active

hold

end

Memory (FCSx#)

Peripheral (IOCSx#)

4 + Vh

2 + Va

4 + Vs

4

HCLK

Table 4-16. Local Bus Interface AC Timing

Name

Parameters

HCLK to PA bus

HCLK to PD bus

HCLK to FCS#[1:0]

HCLK to IOCS#[3:0]

HCLK to PWR#, PRD#

HCLK to BE#[1:0]

PD[15:0] Input setup to HCLK

PD[15:0] Input hold to HCLK

PRDY Input setup to HCLK

PRDY Input hold to HCLK

Min

-

2

-

Max

15

4

Units

nS

-

4

-

2

Issue 1.0 - July 24, 2002

61/111

ELECTRICAL SPECIFICATIONS

4.5.8 PCMCIA INTERFACE

Table 4-17 lists the AC characteristics of the

PCMCIA interface.

Table 4-17. PCMCIA Interface AC Timing

Name

t27

t28

t29

t30

t31

t32

t33

t34

t35

t36

t37

t38

Parameters

Min

24

5

-

2

0

2

7

2

Max

Units

nS

Input setup to ISACLK2X

Input hold from ISACLK2X

ISACLK2X to IORD

ISACLK2X to IORW

ISACLK2X to AD[25:0]

ISACLK2X to OE#

55

25

55

35

55

65

55

ISACLK2X to WE#

ISACLK2X to DATA[15:0]

ISACLK2X to INPACK

ISACLK2X to CE1#

ISACLK2X to CE2#

ISACLK2X to RESET

62/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

4.5.9 IDE INTERFACE

Figure 4-13, Figure 4-14 and Table 4-18 lists the

AC characteristics of the IDE interface.

Figure 4-13. IDE PIO timing diagram

CS#,DA[2:0]

T

hold

DIOR#,DIOW#

T

setup

DD[15:0]

IORDY

Figure 4-14. IDE DMA timing diagram

CS#

REQ

ACK#

T

hold

DIOR#,DIOW#

T

setup

DD[15:0] read

DD[15:0] write

Table 4-18. IDE Interface Timing

Name

Tsetup

Thold

Parameters

DD[15:0] setup to PIOR#/SIOR# falling

DD[15:0} hold to PIOR#/SIOR# falling

Min

15

0

Max

-

Units

ns

Issue 1.0 - July 24, 2002

63/111

ELECTRICAL SPECIFICATIONS

4.5.10 VGA INTERFACE

Table 4-19 lists the AC characteristics of the VGA

interface.

Table 4-19. Graphics Adapter (VGA) AC Timing

Name

Parameter

Min

Max

Unit

ns

DCLK (input) Cycle Time

DCLK (input) High Time

DCLK (input) Low Time

DCLK (input) Rising Time

DCLK (input) Falling Time

DCLK (input) to R,G,B valid

DCLK (input) to HSYNC valid

DCLK (input) to VSYNC valid

DCLK (input) to COL_SEL valid

DCLK (output) Cycle Time

DCLK (output) High Time

DCLK (output) Low Time

DCLK (output) to R,G,B valid

DCLK (output) to HSYNC valid

DCLK (output) to VSYNC valid

DCLK (output) to COL_SEL valid

4.5.11 TFT INTERFACE

Table 4-20 lists the AC characteristics of the TFT

interface.

Table 4-20. TFT Interface Timings

Name

Parameters

DCLK (input) to R[5:0], G[5:0], B[5;0]

DCLK (input) to FPLINE

Min

Max

Units

nS

DCLK (input) to FPFRAME

nS

DCLK (output) to R[5:0], G[5:0], B[5;0]

DCLK (output) to FPLINE

DCLK (output) to FPFRAME

15

nS

64/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

4.5.12 VIDEO INPUT PORT

Table 4-21 lists the AC characteristics of the VIP

interface.

Table 4-21. Video Input AC Timings

Name

Parameter

Min

Max

Unit

ns

VCLK Cycle Time

VCLK High Time

VCLK Low Time

VCLK Rising Time

VCLK Falling Time

VIN[7:0] setup to VCLK

VIN[7:0] hold from VCLK

ODD_EVEN setup to VCLK

ODD_EVEN hold from VCLK

VCS setup to VCLK

VCS hold from VCLK

Issue 1.0 - July 24, 2002

65/111

ELECTRICAL SPECIFICATIONS

4.5.13 USB INTERFACE

The USB interface integrated into the STPC

device is compliant with the USB 1.1 standard.

4.5.14 KEYBOARD & MOUSE INTERFACES

Table 4-22 and Table 4-23 list the AC

characteristics of the Keyboard and Mouse

interfaces.

Table 4-22. Keyboard Interface AC Timing

Name

Parameters

Min

Max

-

Units

nS

Input setup to KBCLK

Input hold to KBCLK

KBCLK to KBDATA

5

1

-

12

nS

Table 4-23. Mouse Interface AC Timing

Name

Parameters

Min

Max

-

Units

nS

Input setup to MCLK

Input hold to MCLK

MCLK to MDATA

5

1

-

12

nS

4.5.15 IEEE1284 INTERFACE

Table 4-24 lists the AC characteristics of the

Keyboard and Mouse interfaces.

Table 4-24. Parallel Interface AC Timing

Name

Parameters

Min

0

Max

Units

nS

STROBE# to BUSY setup

PD bus to AUTPFD# hold

PB bus to BUSY setup

-

0

nS

66/111

Issue 1.0 - July 24, 2002

ELECTRICAL SPECIFICATIONS

4.5.16 JTAG INTERFACE

Figure 4-15 and Table 4-21 list the AC

characteristics of the JTAG interface.

Figure 4-15. JTAG timing diagram

T

reset

TRST

T

cycle

TCK

TMS,TDI

TDO

T

jset

jhld

T

jout

STPC.input

STPC.output

T

pset

phld

T

pout

Table 4-25. JTAG AC Timings

Name

Treset

Tcycle

Parameter

Min

1

Max

Unit

Tcycle

ns

TRST pulse width

TCLK period

400

TCLK rising time

TCLK falling time

TMS setup time

TMS hold time

20

ns

Tjset

Tjhld

Tjset

Tjhld

Tjout

Tpset

Tphld

Tpout

200

ns

TDI setup time

ns

TDI hold time

ns

TCLK to TDO valid

STPC pin setup time

STPC pin hold time

TCLK to STPC pin valid

30

ns

30

ns

Issue 1.0 - July 24, 2002

67/111

ELECTRICAL SPECIFICATIONS

4.5.17 INTENSIONNALLY BLANK

68/111

Issue 1.0 - July 24, 2002

MECHANICAL DATA

5. MECHANICAL DATA

Dimensions are shown in Figure 5-2, Table 5-1

and Figure 5-3, Table 5-2.

5.1. 516-PIN PACKAGE DIMENSION

The pin numbering for the STPC 516-pin Plastic

BGA package is shown in Figure 5-1.

Figure 5-1. 516-Pin PBGA Package - Top View

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

A

B

C

D

E

F

G

H

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

Issue 1.0 - July 24, 2002

69/111

MECHANICAL DATA

Figure 5-2. 516-pin PBGA Package - PCB Dimensions

A1 Ball Pad Corner

A

B

A

D

E

F

Detail

G

C

516-pin PBGA Package - PCB Dimensions

Table 5-1.

mm

Typ

inches

Symbols

Min

Max

35.20

1.32

0.90

1.67

0.25

0.15

0.85

Min

Typ

Max

A

B

C

D

E

F

34.80

1.22

0.60

1.57

0.15

0.05

0.75

35.00

1.27

0.76

1.62

0.20

0.10

0.80

1.370

0.048

0.024

0.062

0.006

0.002

0.030

1.378

0.050

0.030

0.064

0.008

0.004

0.032

1.386

0.052

0.035

0.066

0.001

0.006

0.034

G

70/111

Issue 1.0 - July 24, 2002

MECHANICAL DATA

Figure 5-3. 516-pin PBGA Package - Dimensions

C

F

D

E

Solderball

Solderball after collapse

B

G

A

516-pin PBGA Package - Dimensions

Table 5-2.

mm

inches

Symbols

Min

0.50

1.12

0.60

0.52

0.63

0.60

Typ

0.56

1.17

0.76

0.53

0.78

0.63

30.0

Max

0.62

1.22

0.92

0.54

0.93

0.66

Min

Typ

Max

A

B

C

D

E

F

0.020

0.044

0.024

0.020

0.025

0.024

0.022

0.046

0.030

0.021

0.031

0.025

11.8

0.024

0.048

0.036

0.022

0.037

0.026

G

Issue 1.0 - July 24, 2002

71/111

MECHANICAL DATA

5.2. 516-PIN PACKAGE THERMAL DATA

The structure in shown in Figure 5-4.

Thermal dissipation options are illustrated in

Figure 5-5 and Figure 5-6.

516-pin PBGA package has a Power Dissipation

Capability of 4.5W which increases to 6W when

used with a Heatsink.

Figure 5-4. 516-Pin PBGA Structure

Signal layers

Power & Ground layers

Thermal balls

Figure 5-5. Thermal Dissipation Without Heatsink

Board

Board dimensions:

Junction

Ambient

Case

- 10.2 cm x 12.7 cm

Rca

Rjc

- 4 layers (2 for signals, 1 GND, 1VCC)

6

The PBGA is centred on board

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

Board

8.5

Case

125

Junction

Board

Rjb

Rba

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

Ambient

Airflow = 0

Rja = 13 °C/W

Board temperature taken at the centre balls

72/111

Issue 1.0 - July 24, 2002

MECHANICAL DATA

Figure 5-6. Thermal Dissipation With Heatsink

Board

Board dimensions:

Junction

Ambient

- 10.2 cm x 12.7 cm

Rca

Rjc

- 4 layers (2 for signals, 1 GND, 1VCC)

Case

The PBGA is centred on board

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

3

6

Board

8.5

Case

50

Junction

Board

Rjb

Rba

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

Ambient

Airflow = 0

Ambient

Board temperature taken at the centre balls

Heat sink is 11.1°C/W

Rja = 9.5 °C/W

Issue 1.0 - July 24, 2002

73/111

MECHANICAL DATA

5.3. SOLDERING RECOMMENDATIONS

Dryout section is used primarily to ensure that

the solder paste is fully dried before hitting reflow

temperatures.

High quality, low defect soldering requires

identifying the optimum temperature profile for

reflowing the solder paste, therefore optimizing

the process. The heating and cooling rise rates

must be compatible with the solder paste and

components. A typical profile consists of a

preheat, dryout, reflow and cooling sections.

Solder reflow is accomplished in the reflow zone,

where the solder paste is elevated to

a

temperature greater than the melting point of the

solder. Melting temperature must be exceeded by

°

approximately 20 C to ensure quality reflow.

In reality the profile is not a line, but rather a range

of temperatures all solder joints must be

exposed. The total temperature deviation from

component thermal mismatch, oven loading and

oven uniformity must be within the band.

The most critical parameter in the preheat

section is to minimize the rate of temperature rise

to less than C / second, in order to minimize

thermal shock on the semi-conductor

components.

2°

Figure 5-7. Reflow soldering temperature range

Temperature ( °C )

250

200

150

100

50

PREHEAT

DRYOUT

REFLOW

COOLING

0

Time ( s )

0

240

74/111

Issue 1.0 - July 24, 2002

DESIGN GUIDELINES

6. DESIGN GUIDELINES

These protocols have room for dedicated data

channels in case the terminal is not ’thin’ and can

execute locally some applications, hence

optimizing the bandwidth usage. For example, if a

terminal has browsing or MPEG decoding

capability, the server will provide internet source

files or MPEG streaming.

6.1. TYPICAL APPLICATIONS

The STPC Atlas is well suited for many

applications.

Some

of

the

possible

implementations are described below.

6.1.1. THIN CLIENT

TM

The same hardware can run X-terminal protocol

and can be reconfigured by the server when

booting on the network by uploading a different

OS and application.

A Thin-Client is a terminal running ICA

(Citrix)

TM

or RDP

(Microsoft) protocol. The display is

computed by the server and sent in a compressed

way to the terminal for display. The same

streaming approach is used for sending the

keyboard/mouse/USB data to the server.

Figure 6-1. Thin-Client - Block Diagram

SDRAM

FLASH

LAN

64

16

VGA

TFT

STPC

ATLAS

PCI

MPEG

DECODER

USB

CCIR

IEEE1284

Kbd / Mouse

IDE / PCI

AUDIO

Issue 1.0 - July 24, 2002

75/111

DESIGN GUIDELINES

6.1.2. INTERNET TERMINAL

amount of horizontal frequencies and simplifies

the CRT driving stage:

The internet terminal described here is an

optimized implementation where the STPC Atlas

board is integrated into the CRT itself. The

advantages are a reduced overall cost and a good

image definition.

- 1024x768: 56.5KHz horizontal, 70Hz vertical

- 800x600: 53.7KHz horizontal, 85Hz vertical

Like for the Thin-Client, an external MPEG

decoder can be connected to the STPC Atlas

through the PCI bus and the Video Input Port.

The same concept can be applied using a TFT

display instead of a CRT.

The STPC Atlas platform being integrated into the

monitor itself enables the choice of a limited

Figure 6-2. Internet Terminal - Block Diagram

VSYNC

HSYNC

SDRAM

FLASH

64

16

V

BOOSTER

YOKE

H

PCI

STV2001

MODEM

YOKE

STPC

RS232

SmartCard

ATLAS

R,G,B

IDE / PCI

R,G,B

AUDIO

3

TDA9535

USB

DC

2

RESTORING

QUAD

DAC

E

IEEE1284

PROM

Kbd / Mouse

GPIOs

TILT

2

I C

KEY+

KEY- SEL

76/111

Issue 1.0 - July 24, 2002

DESIGN GUIDELINES

Main STPC modes

6.2. STPC CONFIGURATION

Table 6-2.

Mode

HCLK

MHz

CPU clock MCLK

The STPC is a very flexible product thanks to

decoupled clock domains and to strap options

enabling a user-optimized configuration.

C

clock ratio

MHz

1

2

Synchronous

Asynchronous

66

133 (x2)

66

133 (x2)

90

As some trade off are often necessary, it is

important to do an analysis of the application

needs prior to design a system based on this

product. The applicative constraints are usually

the following:

The advantage of the synchronous mode

compared to the asynchronous mode is a lower

latency when accessing SDRAM from the CPU or

the PCI (saves 4 MCLK cycles for the first access

of the burst). For the same CPU to Memory

transfer performance, MCLK has to be roughly

higher by 20MHz between SYNC and ASYNC

modes to get the same system performance level

(example: 66MHz SYNC = 86MHz ASYNC) .

In all cases, use SDRAM with CAS Latency

equals to 2 (CL2) for the best performances.

- CPU performance

- graphics / video performances

- power consumption

- PCI bandwidth

- booting time

- EMC

Some other elements can help to tune the choice:

- Code size of CPU Consuming tasks

- Data size and location

The advantage of the asynchronous mode is the

capability to reprogram the MCLK speed on the

fly. This could help for applications where power

consumption must be optimized.

On the STPC side, the configurable parameters

are the following:

- synchronous / asynchronous mode

- HCLK speed

The last, and more complex, information to

consider is the behaviour of the software. In case

high CPU or FPU computation is needed, it is

sometime better to be in DX2-133/MCLK=66

synchronous mode than DX2-133/MCLK=90

asynchronous mode. This depends on the locality

of the number crunching code and the amount of

data manipulated.

- MCLK speed

- Local Bus / ISA bus

6.2.1. LOCAL BUS / ISA BUS

The selection between the ISA bus and the Local

Bus is relatively simple. The first one is a standard

bus but slow. The Local Bus is fast and

programmable but doesn't support any DMA nor

external master mechanisms. The Table 6-1

below summarize the selection:

The Table 6-3 below gives some examples. The

right column correspond to the configuration

number as described in Table 6-2:

Clock mode selection

Table 6-3.

Bus mode selection

Table 6-1.

Constraints

C

Need

Selection

Need CPU power

1

Legacy I/O device (Floppy, ...), Super I/O

DMA capability (Soundblaster)

Flash, SRAM, basic I/O device

Fast boot

ISA Bus

Critical code fits into L1 cache

Need CPU power

3

Local Bus

Code or data does not fit into L1 cache

Need high PCI bandwitdh

3

2

Boot flash of 4MB or more

Programmable Chip Select

Need flexible SDRAM speed

Obviously, the values for HCLK or MCLK can be

reduced compared to Table 6-2 in case there is no

need to push the device at its limits, or when

avoiding to use specific frequency ranges (FM

radio band for example).

Before implementing a function requiring DMA

capability on the ISA bus, it is recommended to

check if it exists on PCI, or if it can be

implemented differently, in order to use the local

bus mode.

6.3. ARCHITECTURE RECOMMENDATIONS

6.2.2. CLOCK CONFIGURATION

This

section

describes

the

recommend

The CPU clock and the memory clock are

independent unless the "synchronous mode"

strap option is set (see the STRAP OPTIONS

chapter). The potential clock configurations are

then relatively limited as listed in Table 6-2.

implementations for the STPC interfaces. For

more

Schematics

details,

download

the

Reference

from the STPC web site.

Issue 1.0 - July 24, 2002

77/111

DESIGN GUIDELINES

6.3.1. POWER DECOUPLING

minimum. The use of multiple capacitances with

values in decade is the best (for example: 10pF,

1nF, 100nF, 10uF), the smallest value, the closest

to the power pin. Connecting the various digital

power planes through capacitances will reduce

furthermore the overall impedance and electrical

noise.

An appropriate decoupling of the various STPC

power pins is mandatory for optimum behaviour.

When insufficient, the integrity of the signals is

deteriorated, the stability of the system is reduced

and EMC is increased.

6.3.1.1. PLL decoupling

6.3.2. 14MHZ OSCILLATOR STAGE

This is the most important as the STPC clocks are

generated from a single 14MHz stage using

multiple PLLs which are highly sensitive analog

cells. The frequencies to filter are the 25-50 KHz

range which correspond to the internal loop

bandwidth of the PLL and the 10 to 100 MHz

frequency of the output. PLL power pins can be

tied together to simplify the board layout.

The 14.31818 MHz oscillator stage can be

implemented using a quartz, which is the

preferred and cheaper solution, or using an

external 3.3V oscillator.

The crystal must be used in its series-cut

fundamental mode and not in overtone mode. It

must have an Equivalent Series Resistance (ESR,

sometimes referred to as Rm) of less than 50

Ohms (typically 8 Ohms) and a shunt capacitance

(Co) of less than 7 pF. The balance capacitors of

16 pF must be added, one connected to each pin,

as described in Figure 6-4.

Figure 6-3. PLL decoupling

PWR

VDD_PLL

In the event of an external oscillator providing the

master clock signal to the STPC Atlas device, the

LVTTL signal should be connected to XTALI, as

described in Figure 6-4.

100nF 47uF

VSS_PLL

As this clock is the reference for all the other on-

GND

chip

generated

clocks,

it

is

strongly

Connections must be as short as possible

recommended to shield this stage, including

the 2 wires going to the STPC balls, in order to

reduce the jitter to the minimum and reach the

optimum system stability.

6.3.1.2. Decoupling of 3.3V and Vcore

A power plane for each of these supplies with one

decoupling capacitance for each power pin is the

Figure 6-4. 14.31818 MHz stage

XTALI

XTALO

XTALI

XTALO

3.3V

15pF

78/111

Issue 1.0 - July 24, 2002

DESIGN GUIDELINES

6.3.3. SDRAM

memory and extends to the top of populated

SDRAM. Bank 0 must always be populated.

The STPC provides all the signals for SDRAM

control. Up to 128 MBytes of main memory are

supported. All Banks must be 64 bits wide. Up to 4

memory banks are available when using 16Mbit

devices. Only up to 2 banks can be connected

when using 64Mbit and 128Mbit components due

to the reallocation of CS2# and CS3# signals. This

is described in Table 6-4 and Table 6-5.

Figure 6-5, Figure 6-6 and Figure 6-7 show some

typical implementations.

The purpose of the serial resistors is to reduce

signal oscillation and EMI by filtering line

reflections. The capacitance in Figure 6-5 has a

filtering effect too, while it is used for propagation

delay compensation in the 2 other figures.

Graphics memory resides at the beginning of

Bank 0. Host memory begins at the top of graphics

Figure 6-5. One Memory Bank with 4 Chips (16-bit)

MCLKI

Length(MCLKI) = Length(MCLKy) with y = {A,B,C,D}

MCLKO

10pF

MCLKA

MCLKD

MCLKC

MCLKB

Reference Knot

CS0#

MA[12:0]

BA[1:0]

RAS0#

CAS0#

WE#

DQM[7:6]

MD[63:48]

DQM[5:4]

MD[47:32]

DQM[3:2]

MD[31:16]

DQM[1:0]

MD[15:0]

DQM[7:0]

MD[63:0]

Issue 1.0 - July 24, 2002

79/111

DESIGN GUIDELINES

Figure 6-6. One Memory Banks with 8 Chips (8-bit)

MCLKI

10pF

Length(MCLKI) = Length(MCLKy) with y = {A,B,C,D,E,F,G,H}

MCLKO

CY2305

H

G

F

E

D

C

B

A

CS0#

MA[12:0]

BA[1:0]

RAS0#

CAS0#

WE#

DQM[7:0]

MD[63:0]

DQM[7]

MD[63:56]

DQM[1]

MD[15:8]

DQM[0]

MD[7:0]

Figure 6-7. Two Memory Banks with 8 Chips (8-bit)

MCLKI

y = {A,B,C,D,E,F,G,H}

x = {0,1}

x

22pF

Length(MCLKI) = Length(MCLKy ) with

MCLKO

CY2305

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H

G

G F

F

E

D

D C

C B

B A

A

CS1#

CS0#

MA[12:0]

BA[1:0]

RAS0#

CAS0#

WE#

DQM[7:0]

MD[63:0]

DQM[7]

MD[63:56]

DQM[1] DQM[0]

MD[15:8]

MD[7:0]

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For other implementations like 32-bit SDRAM

devices, refers to the SDRAM controller signal

multiplexing and address mapping described in

the following Table 6-4 and Table 6-5.

DIMM Pinout

Table 6-4.

SDRAM Density

16 Mbit

64/128 Mbit

2 Banks

64/128 Mbit

4 Banks

STPC I/F

Internal Banks

2 Banks

DIMM Pin Number

...

MA[10:0]

MA11

MA[10:0]

MA11

MA[10:0]

CS2# (MA11)

CS3# (MA12)

CS3# (BA1)

BA0

123

126

39

-

MA12

-

BA1 (MA12)

BA0 (MA13)

122

BA0 (MA11)

BA0 (MA13)

Address Mapping

Table 6-5.

Address Mapping: 16 Mbit - 2 internal banks

STPC I/F BA0 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0

RAS Address A11

CAS Address A11

A22

0

A21 A2

A19 A18 A17 A16 A15 A14 A13 A12

A8 A7 A6 A5 A4 A3

A24 A23 A10 A9

Address Mapping: 64/128 Mbit - 2 internal banks

STPC I/F BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0

RAS Address A11 A24

CAS Address A11

A23

0

A22

0

A21 A20 A19 A18 A17 A16 A15 A14 A13 A12

A26 A25 A10 A9 A8 A7 A6 A5 A4 A3

0

Address Mapping: 64/128 Mbit - 4 internal banks

STPC I/F BA0 BA1 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0

RAS Address A11 A12

CAS Address A11 A12

A24

0

A23

0

A22 A21 A20 A19 A18 A17 A16 A15 A14 A13

A26 A25 A10 A9 A8 A7 A6 A5 A4 A3

6.3.4. PCI BUS

PCI_CLKO must be connected to PCI_CLKI

through a 10 to 33 Ohms resistor. Figure 6-8

shows a typical implementation.

The PCI bus is always active and the following

control signals must be pulled-up to 3.3V or 5V

through 2K2 resistors even if this bus is not

connected to an external device: FRAME#,

TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,

SERR#, PERR#, PCI_REQ#[2:0].

For more information on layout constraints, go to

the place and route recommendations section.

Figure 6-8. Typical PCI clock routing

PCICLKI

0 - 33pF

PCICLKA

Device A

PCICLKB

Device B

PCICLKO

PCICLKC

Device C

0 - 22

10 - 33

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In the case of higher clock load it is recommended

to use a zero-delay clock buffer as described in

Figure 6-9. This approach is also recommended

when implementing the delay on PCICLKI

according to the PCI section of the Electrical

Specifications chapter.

Figure 6-9. PCI clock routing with zero-delay clock buffer

PCICLKI

PLL

PCICLKO

Device A

Device B

Device C

Device D

Device A

Device B

Device C

Device D

CY2305

Implementation 1

Implementation 2

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DESIGN GUIDELINES

6.3.5. LOCAL BUS

Figure 6-10 describes how to connect a 16-bit

boot flash (the corresponding strap options must

be set accordingly).

The local bus has all the signals to directly

connect flash devices or I/O devices.

Figure 6-10. Typical 16-bit boot flash implementation

3V3

22

PA[22:1]

A[22:1]

CE

FCS0#

PRD#

PWR#

B

CLK

RB

LE

OE

W

16

PD[15:0]

DQ[15:0]

RP

SYSRSTI#

R

GND

STPC

M58LW064A

RESET#

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DESIGN GUIDELINES

6.3.6. IPC

When an interrupt line is used internally, the

corresponding input can be grounded. In most of

the embedded designs, only few interrupts lines

are necessary and the glue logic can be simplified.

Most of the IPC signals are multiplexed: Interrupt

inputs, DMA Request inputs, DMA Acknowledge

outputs. The figure below describes a complete

implementation of the IRQ[15:0] time-multiplexing.

Figure 6-11. Typical IRQ multiplexing

74x153

1C0

IRQ[0]

Timer 0

IRQ[1]

IRQ[2]

IRQ[3]

IRQ[4]

IRQ[5]

IRQ[6]

IRQ[7]

Keyboard

Slave PIC

COM2/COM4

COM1/COM3

LPT2

1C1

1C2

1C3

2C0

2C1

2C2

2C3

A

1Y

IRQ_MUX[0]

IRQ_MUX[1]

2Y

Floppy

LPT1

B

1G 2G

74x153

1C0

Floppy

IRQ[8]

IRQ[9]

IRQ[10]

IRQ[11]

IRQ[12]

IRQ[13]

IRQ[14]

IRQ[15]

RTC

1C1

1C2

1C3

2C0

2C1

2C2

2C3

A

1Y

IRQ_MUX[2]

IRQ_MUX[3]

Mouse

FPU

PCI / IDE

2Y

B

1G 2G

ISA_CLK2X

ISA_CLK

When the interface is integrated into the STPC,

the corresponding interrupt line can be grounded

as it is connected internally.

For example, if the integrated IDE controller is

activated, the IRQ[14] and IRQ[15] inputs can be

grounded.

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The figure below describes

a

complete

logic can be simplified when only few DMA

channels are used in the application.

This glue logic is not needed in Local bus mode as

it does not support DMA transfers.

implementation of the external glue logic for DMA

Request time-multiplexing and DMA Acknowledge

demultiplexing. Like for the interrupt lines, this

Figure 6-12. Typical DMA multiplexing and demultiplexing

74x153

1C0

DRQ[0]

DRQ[1]

DRQ[2]

DRQ[3]

ISA, Refresh

ISA, PIO

ISA, FDC

ISA, PIO

1C1

1C2

1C3

2C0

2C1

2C2

2C3

A

1Y

DREQ_MUX[0]

DREQ_MUX[1]

DRQ[4]

Slave DMAC

DRQ[5]

DRQ[6]

DRQ[7]

ISA

2Y

B

1G 2G

ISA_CLK2X

ISA_CLK

74x138

Y0#

DACK0#

DACK1#

DACK2#

DACK3#

Y1#

Y2#

Y3#

Y4#

Y5#

Y6#

Y7#

DMA_ENC[0]

DMA_ENC[1]

DMA_ENC[2]

A

B

C

DACK5#

DACK6#

DACK7#

G1

G2A G2B

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6.3.7. IDE / ISA DYNAMIC DEMULTIPLEXING

describes how to implement the external glue

logic to demultiplex the IDE and ISA interfaces. In

Local Bus mode the two buffers are not needed

and the NAND gates can be simplified to inverters.

Some of the ISA bus signals are dynamically

multiplexed to optimize the pin count. Figure 6-13

Figure 6-13. Typical IDE / ISA Demultiplexing

A

B

STPC bus / DD[15:0]

RMRTCCS#

KBCS#

RTCRW#

RTCDS

SA[19:8]

74xx245

MASTER#

ISAOE#

DIR

OE

PCS1#

PCS3#

SCS1#

SCS3#

LA[22]

LA[23]

LA[24]

LA[25]

6.3.8. BASIC AUDIO USING IDE INTERFACE

low cost solution is not CPU consuming thanks to

the DMA controller implemented in the IDE

controller and can generate 16-bit stereo sound.

The clock speed is programmable when using the

speaker output.

When the application requires only basic audio

capabilities, an audio DAC on the IDE interface

can avoid using a PCI-based audio device. This

Figure 6-14. Basic audio on IDE

16

DD[15:0]

PCS1

D[15:0]

Right

CS#

*

Audio Out

PDIOW#

PDRQ

WR#

Left

A/B

SYSRSTO#

Stereo DAC

Vcc

PR

D

Q

D

Q

Speaker

RST

74xx74

STPC

Vcc

Note * : the inverter can be removed when the DAC CS# is directly connected to GND

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DESIGN GUIDELINES

6.3.9. VGA INTERFACE

COL_SEL can be used when implementing the

Picture-In-Picture function outside the STPC, for

example when multiplexing an analog video

source. In that case, the CRTC of the STPC has to

be genlocked to this analog source.

The STPC integrates a voltage reference and

video buffers. The amount of external devices is

then limited to the minimum as described in the

Figure 6-15.

DCLK is usually used by the TFT display which

has RGB inputs in order to synchronise the picture

at the level of the pixel.

All the resistors and capacitors have to be as

close as possible to the STPC while the circuit

protector DALC112S1 must be close to the VGA

connector.

When the VGA interface is not needed, the signals

R, G, B, HSYNC, VSYNC, COMP, RSET can be

left unconnected, VSS_DAC and VDD_DAC must

then be connected to GND.

The DDC[1:0] lines, not represented here, have

also to be protected when they are used on the

VGA connector.

Figure 6-15. Typical VGA implementation

VDD_DAC

COMP

2.5V

10nF

VREF_DAC

RSET

143

1%

100nF 100nF 47uF

VSS_DAC

AGND

COL_SEL

DCLK

HSYNC

VSYNC

R

G

B

75 1%

DALC112S1

3.3V AGND

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6.3.10. USB INTERFACE

the ESD protection circuits USBDF01W5 and a

USB power supply controller. Figure 6-16

describes a typical implementation using these

devices.

The STPC integrates a USB host interface with a

2-port Hub. The only external device needed are

Figure 6-16. Typical USB implementation

Connector

1

(Note1)

USBDF02W5

1

R = 15 Ohm

USBDMNS[0]

USBDPLS[0]

9

3

4

2

3

1

5

10

1

2

R = 15 Ohm

4

(Note1)

USBDF02W5

5

6

7

8

1

R = 15 Ohm

USBDMNS[1]

USBDPLS[1]

11

12

3

4

1

5

1

2

R = 15 Ohm

GND

5V

USBVCC

2,3

OC

5

4

6,7,8

TPS2014

1

100nF

POWERON

100nF 2x 47uF

TPS2014

Power Decoupling

STPC

Note1; TheESD protection will beadequatefor most applications. In someinstances, problems may occur if the devices on the

USB chain do not have enough power to drivethesignals adequately. We therefore recommend that you replacethepart with de-

screte components and reduce the value of the capacitor.

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DESIGN GUIDELINES

6.3.11. KEYBOARD/MOUSE INTERFACE

needed are the ESD protection circuits

KBMF01SC6. Figure 6-17 describes a typical

implementation using a dual minidin connector.

The STPC integrates a PC/AT+ keyboard and

PS/2 mouse controller. The only external devices

Figure 6-17. Typical Keyboard / Mouse implementation

5V

MiniDIN

MDATA

MCLK

10

4

13

3

KBMF01SC6

14

2

6

7

8

9

5V

11

15 12

KBDATA

KBCLK

1

5

16

17

KBMF01SC6

STPC

GND

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6.3.12. PARALLEL PORT INTERFACE

circuits ST1284-01A8. Figure 6-18 describes a

typical implementation using this device.

The STPC integrates a parallel port where the

only external device needed is the ESD protection

Figure 6-18. Typical parallel port implementation

Connector

ACK#

BUSY

PE

SLCT

SLCTIN#

INIT#

ERR#

AUTOFD#

STROBE#

ST1284-01A8

5V

PD[7:0]

8

STPC

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6.3.13. JTAG INTERFACE

device needed are the pull up resistors. Figure 6-

19 describes a typical implementation using these

devices.

The STPC integrates a JTAG interface for scan-

chain and on-board testing. The only external

Typical JTAG implementation

Figure 6-19.

3V3

Connector

10

8

9

7

5

3

1

TCLK

TDO

6

4

TMS

TDI

2

TRST

STPC

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DESIGN GUIDELINES

6.4. PLACE AND ROUTE

RECOMMENDATIONS

All clock signals have to be routed first and

shielded for speeds of 27MHz or higher. The high

speed signals follow the same constraints, as for

the memory and PCI control signals.

6.4.1. GENERAL RECOMMENDATIONS

The next interfaces to be routed are Memory, PCI,

and Video/graphics.

Some STPC Interfaces run at high speed and

need to be carefully routed or even shielded like:

All the analog noise-sensitive signals have to be

routed in a separate area and hence can be

routed indepedently.

1) Memory Interface

2) PCI bus

3) Graphics and video interfaces

4) 14 MHz oscillator stage

Figure 6-20. Shielding signals

ground ring

shielded signal line

ground pad

shielded signal lines

6.4.2. PLL DEFINITION AND IMPLIMENTATION

or one wire for each, or any solution in between

which help the layout of the board can be used.

PLLs are analog cells which supply the internal

STPC Clocks. To get the cleanest clock, the jitter

on the power supply must be reduced as much as

possible. This will result in a more stable system.

Powering these pins with one Ferrite

+

capacitances is enough. We recommend at least

2 capacitances: one 'big' (few uF) for power

storage, and one or 2 smalls (100nF + 1nF) for

noise filtering.

Each of the integrated PLL has a dedicated power

pin so a single power plane for all of these PLLs,

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6.4.3. MEMORY INTERFACE

6.4.3.1. Introduction

DIMM PCB is no longer present but it is then up to

the user to verify the timings.

6.4.3.2. SDRAM Clocking Scheme

In order to achieve SDRAM memory interfaces

which work at clock frequencies of 90 MHz and

above, careful consideration has to be given to the

timing of the interface with all the various electrical

and physical constraints taken into consideration.

The guidelines described below are related to

SDRAM components on DIMM modules. For

applications where the memories are directly

soldered to the motherboard, the PCB should be

laid out such that the trace lengths fit within the

constraints shown here. The traces could be

slightly shorter since the extra routing on the

The SDRAM Clocking Scheme deserves a special

mention here. Basically the memory clock is

generated on-chip through a PLL and goes

directly to the MCLKO output pin of the STPC. The

nominal frequency is 90 MHz. Because of the high

load presented to the MCLK on the board by the

DIMMs it is recommended to rebuffer the MCLKO

signal on the board and balance the skew to the

clock ports of the different DIMMs and the MCLKI

input pin of STPC.

Figure 6-21. Clock Scheme

MCLKO

MCLKI

PLL

MA[ ] + Control

MD[63:0]

SDRAM

CONTROLLER

6.4.3.3. Board Layout Issues

and ground planes to provide a low impedance

path between the planes for the return paths for

signal routings which change layers. If possible,

the traces should be routed adjacent to the same

power or ground plane for the length of the trace.

The physical layout of the motherboard PCB

assumed in this presentation is as shown in Figure

6-22. Because all of the memory interface signal

balls are located in the same region of the STPC

device, it is possible to orientate the device to

reduce the trace lengths. The worst case routing

length to the DIMM1 is estimated to be 100 mm.

For the SDRAM interface, the most critical signal

is the clock. Any skew between the clocks at the

SDRAM components and the memory controller

will impact the timing budget. In order to get well

matched clocks at all components it is

recommended that all the DIMM clock pins, STPC

Solid power and ground planes are a must in order

to provide good return paths for the signals and to

reduce EMI and noise. Also there should be ample

high frequency decoupling between the power

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DESIGN GUIDELINES

Figure 6-22. DIMM placement

35mm

STPC

35mm

15mm

SDRAM I/F

DIMM2

DIMM1

10mm

116mm

memory clock input (MCLKI) and any other

component using the memory clock are

individually driven from a low skew clock driver

with matched routing lengths. In other words, all

clock line lengths that go from the buffer to the

memory chips (MCLKx) and from the buffer to the

STPC (MCLKI) must be identical.

This is shown in Figure 6-23.

Figure 6-23. Clock Routing

L

Low skew clock driver:

MCLKO

DIMM CKn input

STPC MCLKI

L+75mm*

20pF

* No additional 75mm when SDRAM directly soldered on board

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The maximum skew between pins for this part is

250ps. The important factors for the clock buffer

are a consistent drive strength and low skew

between the outputs. The delay through the buffer

is not important so it does not have to be a zero

delay PLL type buffer. The trace lengths from the

clock driver to the DIMM CKn pins should be

matched exactly. Since the propagation speed

can vary between PCB layers, the clocks should

be routed in a consistent way. The routing to the

STPC memory input should be longer by 75 mm to

compensate for the extra clock routing on the

DIMM. Also a 20 pF capacitor should be placed as

near as possible to the clock input of the STPC to

compensate for the DIMM’s higher clock load. The

impedance of the trace used for the clock routing

should be matched to the DIMM clock trace

row DIMMs or one dual-row DIMM can be

controlled.

6.4.3.4. Summary

For unbuffered DIMMs the address/control signals

will be the most critical for timing. The simulations

show that for these signals the best way to drive

them is to use a parallel termination. For

applications where speed is not so critical series

termination can be used as this will save power.

Using a low impedance such as 50Ω for these

critical traces is recommended as it both reduces

the delay and the overshoot.

The other memory interface signals will typically

be not as critical as the address/control signals.

Using lower impedance traces is also beneficial

for the other signals but if their timing is not as

critical as the address/control signals they could

use the default value. Using a lower impedance

implies using wider traces which may have an

impact on the routing of the board.

impedance (60-75 ohms)

To minimise crosstalk

.

the clocks should be routed with spacing to

adjacent tracks of at least twice the clock trace

width. For designs which use SDRAMs directly

mounted on the motherboard PCB all the clock

trace lengths should be matched exactly.

The DIMM sockets should be populated starting

with the furthest DIMM from the STPC device first

(DIMM1). There are two types of DIMM devices;

single-row and dual-row. The dual-row devices

require two chip select signals to select between

the two rows. A STPC device with 4 chip select

control lines could control either 4 single-row

DIMMs or 2 dual-row DIMMs. When only 2 chip

select control lines are activated, only two single-

The layout of this interface can be validated by an

electrical simulation using the IBIS model

available on the STPC web site.

6.4.3.5. Clock topology for on-board SDRAM

Figure 6-24 and Figure 6-25 give the recommend-

ed clock topology and the resulting IBIS simulation

in the case of four on-board SDRAM devices and

no clock buffer.

Figure 6-24. Recommended topology for 4 on-board SDRAMs (IBIS model)

MCLKO

18 Ohms

MCLKI

3500 mils

MCLK0

MCLK1

MCLK2

MCLK3

400 mils

Track impedance= 75 Ohms

Trace thickness = 0.72 mil

Trace width = 4 to 8 mils

6.4.3.6. Clock topology for standard DIMM

ed clock topology and the resulting IBIS simulation

in the case of a standard DIMM with the use of a

clock buffer.

Figure 6-26 and Figure 6-27 give the recommend-

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DESIGN GUIDELINES

Figure 6-25. IBIS Simulation for on-board SDRAM / 90MHz

(V)

MCLKI

3

MCLKI

MCLKx

2.0 V

2

1

833ps

0.8 V

791ps

Time

Figure 6-26. Recommended topology for DIMM (IBIS model)

22 Ohms

3000 mils

Buffer out

MCLKI

18 Ohms

2000 mils

DIMM

Track impedance= 75 Ohms

Trace thickness = 0.72 mil

Trace width = 4 to 8 mils

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Figure 6-27. IBIS Simulation for DIMM / 90MHz

(V)

3

MCLKx

MCLKI

Buffer output

2.0 V

1.40 ns

2

1

0.8 V

1.20 ns

Time

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6.4.4. PCI INTERFACE

6.4.4.1. Introduction

6.4.4.2. PCI Clocking Scheme

The PCI Clocking Scheme deserves a special

mention here. Basically the PCI clock (PCICLKO)

is generated on-chip from HCLK through a

programmable delay line and a clock divider. The

nominal frequency is 33MHz. This clock must be

looped to PCICLKI and goes to the internal South

Bridge through a deskewer. On the contrary, the

internal North Bridge is clocked by HCLK, putting

In order to achieve a PCI interface which work at

clock frequencies up to 33MHz, careful

consideration has to be given to the timing of the

interface with all the various electrical and

physical constraints taken into consideration.

some additionnal constraints on T and T .

0

1

Figure 6-28. Clock Scheme

HCLK

HCLK PLL

T

0

1

PCICLKO

1/2

1/3

1/4

clock

delay

T

2

MD[30:27]

MD[17,4]

T

Strap Options

MD[7:6]

PCICLKI

AD[31:0]

Deskewer

South

Bridge

MUX

North

Bridge

STPC

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6.4.4.3. Board Layout Issues

words, all clock line lengths that go from the

resistor to the PCI chips (PCICLKx) must be

identical.

The physical layout of the motherboard PCB

assumed in this presentation is as shown in Figure

6-29. For the PCI interface, the most critical signal

is the clock. Any skew between the clocks at the

PCI components and the STPC will impact the

timing budget. In order to get well matched clocks

at all components it is recommended that all the

PCI clocks are individually driven from a serial

resistance with matched routing lengths. In other

The figure below is for PCI devices soldered on-

board. In the case of a PCI slot, the wire length

must be shortened by 2.5" to compensate the

clock layout on the PCI board. The maximum

clock skew between all devices is 2ns according

to PCI specifications.

Figure 6-29. Typical PCI clock routing

Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}

PCICLKI

PCICLKA

Device A

PCICLKB

Device B

PCICLKO

PCICLKC

Device C

Note: The value of 22 Ohms corresponds to tracks with Z = 70 Ohms.

0

The Figure 6-30 describes a typical clock delay

implementation. The exact timing constraints are

listed in the PCI section of the

Electrical

Chapter.

Specifications

Figure 6-30. Clocks relationships

HCLK

PCICLKO

PCICLKI

PCICLKx

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6.4.5. THERMAL DISSIPATION

6.4.5.1. Power saving

With such configuration the Plastic BGA package

does 90% of the thermal dissipation through the

ground balls, and especially the central thermal

balls which are directly connected to the die. The

remaining 10% is dissipated through the case.

Adding a heat sink reduces this value to 85%.

Thermal dissipation of the STPC depends mainly

on supply voltage. When the system does not

need to work at the upper voltage limit, it may

therefore be beneficial to reduce the voltage to the

lower voltage limit, where possible. This could

save a few 100’s of mW.

As a result, some basic rules must be followed

when routing the STPC in order to avoid thermal

problems.

As the whole ground layer acts as a heat sink, the

ground balls must be directly connected to it, as

illustrated in Figure 6-31. If one ground layer is not

enough, a second ground plane may be added.

The second area to look at is unused interfaces

and functions. Depending on the application,

some input signals can be grounded, and some

blocks not powered or shutdown. Clock speed

dynamic adjustment is also a solution that can be

used along with the integrated power

management unit.

When possible, it is important to avoid other

devices on-board using the PCB for heat

dissipation, like linear regulators, as this would

heat the STPC itself and reduce the temperature

range of the whole system, In case these devices

can not use a separate heat sink, they must not be

located just near the STPC

6.4.5.2. Thermal balls

The standard way to route thermal balls to ground

layer implements only one via pad for each ball

pad, connected using a 8-mil wire.

Figure 6-31. Ground Routing

Pad for ground ball

Thru hole to ground layer

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DESIGN GUIDELINES

When considering thermal dissipation, one of the

most important parts of the layout is the

connection between the ground balls and the

ground layer.

A 1-wire connection is shown in Figure 6-32. The

use of a 8-mil wire results in a thermal resistance

of 105°C/W assuming copper is used (418 W/

m.°K). This high value is due to the thickness (34

µm) of the copper on the external side of the PCB.

Figure 6-32. Recommended 1-wire Power/Ground Pad Layout

Pad for ground ball (diameter = 25 mil)

Solder Mask (4 mil)

Connection Wire (width = 12.5 mil)

Via (diameter = 24 mil)

Hole to ground layer (diameter = 12 mil)

1 mil = 0.0254 mm

Considering only the central matrix of 36 thermal

balls and one via for each ball, the global thermal

resistance is 2.9°C/W. This can be easily

improved using four 12.5 mil wires to connect to

the four vias around the ground pad link as in

Figure 6-33. This gives a total of 49 vias and a

global resistance for the 36 thermal balls of 0.5°C/

W.

Figure 6-33. Recommended 4-wire Ground Pad Layout

4 via pads for each ground ball

The use of a ground plane like in Figure 6-34 is

even better.

Issue 1.0 - July 24, 2002

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DESIGN GUIDELINES

To avoid solder wicking over to the via pads during

soldering, it is important to have a solder mask of

4 mil around the pad (NSMD pad). This gives a

diameter of 33 mil for a 25 mil ground pad.

To obtain the optimum ground layout, place the

vias directly under the ball pads. In this case no

local board distortion is tolerated.

Figure 6-34. Optimum Layout for Central Ground Ball - top layer

Clearance = 6mil

External diameter = 37 mil

Via to Ground layer

hole diameter = 14 mil

Solder mask

diameter = 33 mil

Pad for ground ball

diameter = 25 mil

connections = 10 mil

6.4.5.3. Heat dissipation

heat and hence the thermal dissipation of the

board.

The thickness of the copper on PCB layers is

typically 34 µm for external layers and 17 µm for

internal layers. This means that thermal

dissipation is not good; high board temperatures

are concentrated around the devices and these

fall quickly with increased distance.

The possibility of using the whole system box for

thermal dissipation is very useful in cases of high

internal

temperatures

and

low

outside

temperatures. Bottom side of the PBGA should be

thermally connected to the metal chassis in order

to propagate the heat flow through the metal.

Thermally connecting also the top side will

improve furthermore the heat dissipation. Figure

6-35 illustrates such an implementation.

Where possible, place a metal layer inside the

PCB; this improves dramatically the spread of

Figure 6-35. Use of Metal Plate for Thermal Dissipation

Die

Board

Metal planes

Thermal conductor

102/111

Issue 1.0 - July 24, 2002

DESIGN GUIDELINES

As the PCB acts as a heat sink, the layout of top

and ground layers must be done with care to

maximize the board surface dissipating the heat.

The only limitation is the risk of losing routing

channels. Figure 6-36 and Figure 6-37 show a

routing with a good thermal dissipation thanks to

an optimized placement of power and signal vias.

The ground plane should be on bottom layer for

the best heat spreading (thicker layer than internal

ones) and dissipation (direct contact with air). .

Figure 6-36. Layout for Good Thermal Dissipation - top layer

1

A

STPC ball

Via

GND ball

3.3V ball

Not Connected ball

2.5V ball (Core / PLLs)

Issue 1.0 - July 24, 2002

103/111

DESIGN GUIDELINES

Figure 6-37. Recommend signal wiring (top & ground layers) with corresponding heat flow

GND

Power

GND

Power

Power/GND balls

Internal row

Signal balls

External row

Keep-Out = 6 mils

Power/GND balls

Signal balls

104/111

Issue 1.0 - July 24, 2002

DESIGN GUIDELINES

CPU clock mode, this clock must be limited to

66MHz.

6.5. DEBUG METHODOLOGY

In order to bring a STPC-based board to life with

the best efficiency, it is recommended to follow the

check-list described in this section.

PCI_CLKI and PCI_CLKO must be connected as

described in Figure 6-19 and not be higher than

33MHz. Their speed depends on HCLK and on

the divider ratio defined by the MD[4] and MD[17]

strap options as described in Section 3.

6.5.1. POWER SUPPLIES

To ensure a correct behaviour of the device, the

PCI deskewing logic must be configured properly

by the MD[7:6] strap options according to Section

3. For timings constraints, refers to Section 4.

In parallel with the assembly process, it is useful to

get a bare PCB to check the potential short-

circuits between the various power and ground

planes. This test is also recommended when the

first boards are back from assembly. This will

avoid bad surprises in case of a short-circuit due

to a bad soldering.

1) MCLKI and MCLKO must be connected as

described in Figure 6-3 to Figure 6-5 depending

on the SDRAM implementation. The memory

clock must run at HCLK speed when in

synchronous mode and must not be higher than

90MHz in any case. The MCLK interface will run

100MHz operation is possible but board layout is

so critical that 90MHz maximum operation is

recommended.

When the system is powered, all power supplies,

including the PLL power pins must be checked to

be sure the right level is present. See Table 4-2 for

the exact supported voltage range:

VDD_CORE: 2.5V

VDD_xxxPLL: 2.5V

VDD: 3.3V

6.5.2.4. Reset output

6.5.2. BOOT SEQUENCE

6.5.2.1. Reset input

If SYSRSTI# and all clocks are correct, then the

SYSRSTO# output signal should behave as

described in Figure 4-3

.

The checking of the reset sequence is the next

step. The waveform of SYSRSTI# must complies

with the timings described in Figure 4-3. This

signal must not have glitches and must stay low

until the 14.31818MHz output (OSC14M) is at the

right frequency and the strap options are

stabilized to a valid configuration.

6.5.3. ISA MODE

Prior to check the ISA bus control signals,

PCI_CLKI, ISA_CLK, ISA_CLK2X, and DEV_CLK

must be running properly. If it is not the case, it is

probably because one of the previous steps has

not been completed.

In case this clock is not present, check the 14MHz

oscillator stage (see Figure 6-3).

6.5.3.1. First code fetches

When booting on the ISA bus, the two key signals

to check at the very beginning are RMRTCCS#

and FRAME#.

6.5.2.2. Strap options

The STPC has been designed in a way to allow

configurations for test purpose that differs from the

functional configuration. In many cases, the

troubleshootings at this stage of the debug are the

resulting of bad strap options. This is why it is

mandatory to check they are properly setup and

sampled during the boot sequence.

The first one is a Chip Select for the boot flash

and is multiplexed with the IDE interface. It should

toggle together with ISAOE# and MEMRD# to

fetch the first 16 bytes of code. This corresponds

to the loading of the first line of the CPU cache.

In case RMRTCCS# does not toggle, it is then

necessary to check the PCI FRAME# signal.

Indeed the ISA controller is part of the South

Bridge and all ISA bus cycles are visible on the

PCI bus.

The list of all the strap options is summarized at

the beginning of Section 3.

6.5.2.3. Clocks

Once OSC14M is checked and correct, the next

signals to measure are the Host clock (HCLK),

PCI clocks (PCI_CLKO, PCI_CLKI) and Memory

clock (MCLKO, MCLKI).

If there is no activity on the PCI bus, then one of

the previous steps has not been checked properly.

If there is activity then there must be something

conflicting on the ISA bus or on the PCI bus.

HCLK must run at the speed defined by the

corresponding strap options (see Table 3-1). In x2

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DESIGN GUIDELINES

6.5.3.2. Boot Flash size

toggle together with PRD# to fetch the first 16

bytes of code. This corresponds to the loading of

the first line of the CPU cache.

In case FCS0# does not toggle, then one of the

previous steps has not been done properly, like

HCLK speed and CPU clock multiplier (x1, x2).

The ISA bus supports 8-bit and 16-bit memory

devices. In case of a 16-bit boot flash, the signal

MEMCS16#

must

be

activated

during

RMRTCCS# cycle to inform the ISA controller of a

16-bit device.

6.5.4.2. Boot Flash size

6.5.3.3. POST code

The Local Bus support 16-bit boot memory

devices only.

Once the 16 first bytes are fetched and decoded,

the CPU core continue its execution depending on

the content of these first data. Usually, it

corresponds to a JUMP instruction and the code

fetching continues, generating read cycles on the

ISA bus.

6.5.4.3. POST code

Like in ISA mode, POST codes can be

implemented on the Local Bus. The difference is

that an IOCS# must be programmed at I/O

address 80H prior to writing these code, the POST

display being connected to this IOCS# and to the

lower 8 bits of the bus.

Most of the BIOS and boot loaders are reading the

content of the flash, decompressing it in SDRAM,

and then continue the execution by jumping to the

entry point in RAM. This boot process ends with a

JUMP to the entry point of the OS launcher.

6.5.5. SUMMARY

These various steps of the booting sequence are

codified by the so-called POST codes (Power-On

Self-Test). A 8-bit code is written to the port 80H at

the beginning of each stage of the booting process

(I/O write to address 0080H) and can be displayed

on two 7-segment display, enabling a fast visual

check of the booting completion level.

Here is a check-list for the STPC board debug

from power-on to CPU execution.

For each step, in case of failure, verify first the

corresponding balls of the STPC:

- check if the voltage or activity is correct

- search for potential shortcuts.

For troubleshooting in steps 5 to 10, verify the

related strap options:

- value & connection. Refer to Section 3.

- see Figure 4-3 for timing constraints

Usually, the last POST code is 0x00 and

corresponds to the jump into the OS launcher.

When the execution fails or hangs, the lastest

written code stays visible on that display,

indicating either the piece of code to analyse,

either the area of the hardware not working

properly.

Steps 8a and 9a are for debug in ISA mode while

steps 8b and 9b are for Local Bus mode.

6.5.4. LOCAL BUS MODE

6.5.6. PCMCIA MODE

As the STPC uses the RMRTCCS# signal for

booting in that mode, the methodology is the same

as for the ISA bus. The PCMCIA cards being 3.3V

or 5V, the boot flash device must be 5V tolerant

when directly connected on the address and data

busses. An other solution is to isolate the flash

from the PCMCIA lines using 5V tolerant LVTTL

buffers.

As the Local Bus controller is located into the Host

interface, there is no access to the cycles on the

PCI, reducing the amount of signals to check.

6.5.4.1. First code fetches

When booting on the Local Bus, the key signal to

check at the very beginning is FCS0#. This signal

is a Chip Select for the boot flash and should

Check:

How?

Troubleshooting

Verify that voltage is within specs:

- this must include HF & LF noise

- avoid full range sweep

Measure voltage near STPC balls:

- use very low GND connection.

Add some decoupling capacitor:

- the smallest, the nearest to STPC balls.

Power

supplies

1

2

Refer to Table 4-1 for values

The 2 capacitors used with the quartz must

match with the capacitance of the crystal.

14.318 MHz

Verify OSC14M speed

Try other values.

106/111

Issue 1.0 - July 24, 2002

DESIGN GUIDELINES

Check:

How?

Troubleshooting

Verify reset generation circuit:

- device reference

- components value

Measure SYSRSTI# of STPC

See Figure 4-3 for waveforms.

SYSRSTI#

(Power Good)

3

5

Measure HCLK is at selected frequency

25MHz < HCLK < 66MHz

HCLK

HCLK wire must be as short as possible

Measure PCICLKO:

Verify PCICLKO loops to PCICLKI.

Verify maximum skew between any PCI clock

branch is below 2ns.

- maximum is 33MHz by standard

- check it is at selected frequency

- it is generated from HCLK by a division

(1/2, 1/3 or 1/4)

6

PCI clocks

In Synchronous mode, check MCLKI.

Check PCICLKI equals PCICLKO

Measure MCLKO:

- use a low-capacitance probe

- maximum is 90MHz

- check it is at selected frequency

- In SYNC mode MCLK=HCLK

- in ASYNC mode, default is 66MHz

Check MCLKI equals MCLKO

Verify load on MCLKI.

Verify MCLK programming (BIOS setting).

Memory

clocks

7

4

Verify SYSRSTI# duration.

Verify SYSRSTI# has no glitch

Verify clocks are running.

Measure SYSRSTO# of STPC

SYSRSTO#

PCI cycles

See

for waveforms.

Figure 4-3

Check PCI signals are toggling:

- FRAME#, IRDY#, TRDY#, DEVSEL#

- these signals are active low.

Check, with a logic analyzer, that first

PCI cycles are the expected ones:

memory read starting at address with

lower bits to 0xFFF0

Verify PCI slots

If the STPC don’t boot

- verify data read from boot memory is OK

- ensure Flash is correctly programmed

- ensure CMOS is cleared.

8a

Verify MEMCS16#:

- must not be asserted for 8-bit memory

ISA

cycles

to

Check RMRTCCS# & MEMRD#

Check directly on boot memory pin

9a

Verify IOCHRDY is not be asserted

Verify ISAOE# pin:

- it controls IDE / ISA bus demultiplexing

boot memory

Check FCS0# & PRD#

Check directly on boot memory pin

8b

9b

Verify HCLK speed and CPU clock mode.

Local Bus

cycles

Check, with a logic analyzer, that first

Local Bus cycles are the expected one:

memory read starting at the top of boot

memory less 16 bytes

If the STPC don’t boot

to

- verify data read from boot memory is OK

- ensure Flash is correctly programmed

- ensure CMOS is cleared.

boot memory

The CPU fills its first cache line by fetching 16 bytes from boot memory.

Then, first instructions are executed from the CPU.

10

Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU

=> Minimum hardware is correctly set, CPU executes code.

Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.

Issue 1.0 - July 24, 2002

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DESIGN GUIDELINES

6.5.7.

108/111

Issue 1.0 - July 24, 2002

ORDERING DATA

7. ORDERING DATA

7.1. ORDERING CODES

ST

PC

I2

H

E

Y

C

STMicroelectronics

Prefix

Product Family

PC: PC Compatible

Product ID

I2: Atlas

Core Speed

G: 120 MHz

H: 133 MHz

Memory Speed

D: 90 MHz

E: 100 MHz

Package

Y: 516 Overmoulded BGA

Temperature Range

C: Commercial

Tcase = 0 to +85°C

I: Industrial

Tcase = -40 to +115°C

Issue 1.0 - July 24, 2002

109/111

ORDERING DATA

7.2. AVAILABLE PART NUMBERS

Core Frequency

Memory Interface

Speed (MHz)

Tcase Range

(C)

Operating Voltage

(V)

Part Number

(MHz)

CPU Mode

1

STPCI2HEYC

STPCI2GDYI

133

120

X2

90

0°C to +85°C

2.45 - 2.7

3.0 - 3.6

-40°C to +115°C

Note 1:

The STPC Atlas MClock signal can run up to 100MHz reliably, but PCB layout is so critical that the maximum guaranteed

speed is 90MHz

110/111

Issue 1.0 - July 24, 2002

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

111

Issue 1.0


型号：	STPCATLAS
厂家：	ST
描述：	X86 Core PC Compatible System-on-Chip for Terminals X86核心的PC兼容系统级芯片的终端 PC
文件：	总111页 (文件大小：1892K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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