STLC2415 [STMICROELECTRONICS]
BLUETOOTH BASEBAND WITH INTEGRATED FLASH; 具有内置闪光灯蓝牙基带
| 型号： | STLC2415 |
| 厂家： | 
ST |
| 描述： | BLUETOOTH BASEBAND WITH INTEGRATED FLASH |
| 文件： | 总22页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLC2415
BLUETOOTH® BASEBAND WITH INTEGRATED FLASH
PRELIMINARY DATA
1 FEATURES
Figure 1. Package
■ Bluetooth® V1.1 specification compliant
■ SW compatible with STLC2410B-M28R400CT
combination
■ 2 layer class 4 PCB compatible
■ Point-to-point, point-to-multi-point (up to 7
slaves) and scatternet capability
LFBGA120 (10x10x1.4mm)
Table 1. Order Codes
■ Asynchronous Connection Less (ACL) link
support giving data rates up to 721 kbps
■ Synchronous Connection Oriented (SCO) link
■ Standard BlueRF bus interface
Part Number
Package
LFBGA120
Temp. Range
STLC2415
-40 to +85 °C
stack with profiles
■ Clock support
– Support of UART and USB HCI transport layers.
■ Idle and power down modes
– Ultra low power in idle mode
– Low standby current
– System clock input: 13 MHz external clock
– LPO clock input at 3.2 and 32 kHz or via the
embedded 32 kHz crystal oscillator cell
■ ARM7TDMI 32-bit CPU
■ Memory organization
1.1 Applications Features
– Integrated 4 Mbit flash
Typical applications in which the STLC2415 can
be used are:
– 64 KByte on-chip RAM
– 4 KByte on-chip boot ROM
– Hold-acknowledge bus arbitration support
■ HW support for all packet types
– ACL: DM1, 3, 5 and DH1, 3, 5
– SCO: HV1, 2, 3 and DV1
■ Cable replacement
■ Portable computers, PDA
■ Modems
■ Handheld data transfer devices
■ Cameras
■ Communication interfaces
■ Computer peripherals
■ Other type of devices that require the wireless
– Serial Synchronous Interface
– Two enhanced 16550 UART's with 128 byte
fifo depth
communication provided by Bluetooth®
– 12 Mbps USB interface
2 DESCRIPTION
– Fast master I2C bus interface
– Multi slot PCM interface
The STLC2415 from STMicroelectronics is a Blue-
tooth® baseband controller with integrated 4 Mbit
flash memory. Together with a Bluetooth® Radio
this product offers a compact and complete solu-
tion for short-range wireless connectivity. It incor-
porates all the lower layer functions of the
Bluetooth® protocol.
– 16 programmable GPIO
– 2 external interrupts and various interrupt
possibilities through other interfaces
■ Ciphering support for up to 128-bit key
■ Receiver Signal Strenght Indication (RSSI)
support for power-controlled links
■ Separate control for external power amplifier
(PA) for class1 power support.
The microcontroller allows the support of all data
packets of Bluetooth® in addition to voice. The em-
bedded controller can be used to run the Blue-
tooth® protocol and application layers if required.
The software is located in the integrated flash
memory.
■ Software support
– Low level (up to HCI) stack or embedded
Rev. 2
1/22
September 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
STLC2415
3 QUICK REFERENCE DATA
3.1 Absolute Maximum Ratings
Operation of the device beyond these conditions is not guaranteed.
Sustained exposure to these limits will adversely affect device reliability
Table 2. Absolute Maximum Ratings
Symbol
Conditions
Supply voltage baseband core
Min
Max
2.5
2.5
13
Unit
V
V
V
V
V
0.5
DD
SS –
SS –
SS –
V
DDF
Supply voltage flash
0.5
0.5
V
V
PP
Fast Program Voltage
V
V
Supply voltage baseband I/O
Supply voltage flash I/O
4
V
DDIO
V
V
V
0.5
0.5
2.5
V
DDQ
SS –
V
Input voltage on any digital pin (excluding FLASH input pins)
Operating ambient temperature
Storage temperature
V + 0.3
DDIO
V
IN
SS –
T
-40
+85
+150
+240
°C
°C
°C
amb
T
-55
stg
T
Lead temperature < 10s
lead
3.2 Operating Ranges
Operating ranges define the limits for functional operation and parametric characteristics of the device.
Functionality outside these limits is not implied.
Table 3. Operating Ranges
Symbol
Conditions
Supply voltage baseband core and EMI pads
Supply voltage flash
Min
1.55
1.55
2.7
Typ
1.8
1.8
3.3
1.8
Max
1.95
1.95
3.6
Unit
V
V
DD
V
V
DDF
V
Supply voltage baseband I/O
V
DDIO
V
Supply voltage flash I/O (V
≤ V )
DDF
1.55
-40
1.95
+85
V
DDQ
DDQ
T
amb
Operating ambient temperature
°C
3.3 I/O Specifications
Depending on the interface, the I/O voltage is typical 1.8V (interface to the flash memory) or typical 3.3V
(all the other interfaces). These I/Os comply to the EIA/JEDEC standard JESD8-B.
3.3.1 Specifications for 3.3V I/Os
Table 4. LVTTL DC Input Specification (3V<VDDIO<3.6V)
Symbol
Vil
Parameter
Low level input voltage
Conditions
Min
Typ
Max
Unit
V
0.8
Vih
High level input voltage
Schmitt trigger hysteresis
2
V
Vhyst
0.4
V
Table 5. LVTTL DC Output Specification (3V<VDDIO<3.6V)
Symbol
Vol
Parameter
Low level output voltage
High level output voltage
Conditions
Iol = X mA
Min
Typ
Max
0.15
Unit
V
V
Voh
Ioh =-X mA
VDDIO-0.15
Note: X is the source/sink current under worst case conditions according to the drive capability. (See table 8, pad information for value of X).
2/22
STLC2415
3.3.2 Specifications for 1.8V I/Os
Table 6. DC Input Specification (1.55V<VDD<1.95V)
Symbol
Vil
Parameter
Low level input voltage
Conditions
Min
Typ
Max
Unit
V
0.35*VDD
Vih
High level input voltage
Schmitt trigger hysteresis
0.65*VDD
0.2
V
Vhyst
0.3
0.5
V
Table 7. DC Output Specification (1.55V<VDD<1.95V)
Symbol
Vol
Parameter
Low level output voltage
High level output voltage
Conditions
Iol = X mA
Min
Typ
Max
Unit
V
0.15
Voh
Ioh =-X mA
VDD-0.15
V
Note: X is the source/sink current under worst case conditions according to the drive capability. (See table 8, pad information for value of X).
3.4 Current Consumption
Table 8. Typical Power Consumption of the STLC2415 (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO
3.3V)
=
Core
STLC2415 State
IO
Unit
Slave
5.10
0.94
7.60
7.90
8.70
127
Master
5.10
0.94
6.99
7.20
7.90
n.a.
Standby (no low power mode)
0.13
0.13
0.13
0.13
0.14
5
mA
mA
mA
mA
mA
µA
Standby (low power mode enabled)
ACL connection (no transmission)
ACL connection (data transmission)
SCO connection (no codec connected)
Inquiry and Page scan (low power mode enabled)
Low Power mode (32 kHz crystal)
20
20
0
µA
3/22
STLC2415
Figure 2. Block Diagram and Electrical Schematic
JTAG
5
4
2
PCM
PCM
VDD
INTERRUPT
CONTROLLER
100nF
EXT._INT1/2
2
2
USB
I2C
USB
VDDIO
100nF
I2C
VDDIO
4
APB
BRIDGE
100nF
SPI
SPI
ARM7
TDMI
16
13
TIMER
GPIO
GPIO(O..15)
RADIO
I/F
BLUETOOTH
CORE
RF BUS
D
M
A
8
START
DETECT
RAM
UART
UART
UART2
UART1
(*)
22pF
22pF
LPOCLKP
2
2
BOOT
ROM
UART
FIFO
LPO
Y2
32KHz
NRESET
SYS_CLK_REQ
SYSTEM
CONTROL
LPOCLKN
DATA(0..15)
ADDR(0..19)
WRN
16
16
DATA(0..15)
ADDR(1..18)
NW
20
18
VDDPLL
VDD
4Mbit
FLASH
VDD
EMI
100nF
RDN
1
1
NG
100nF
CSN(0)
NE
1
2
1
5
16
1
1
D03TL582A
BOOT
CSN(1..2)
XIN
RDN/NG ADDR DATA(0..15)
(0,2,17,18,19)
NRP NWP
CSN(0)
NE
(**)
(*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal
(**) For device testing only (should not be connected in the application.
4/22
STLC2415
4 PINOUT
Figure 3. Pinout (Bottom view)
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
uart1_ uart1_ i2c_ i2c_ pcm_ pcm_ usb_ uart2_ uart2_ uart2_ uart2_
spi_ spi_
nreset nrp
xin
vddio vdd
vss
rxd
txd
dat
clk
sync
a
dn
rxd
txd
i1
o2
frm
clk
A
B
C
D
E
F
spi_txd
sys_cl
k_req
pcm_ pcm- usb_ uart2_ uart2_ uart2_ uart2_
n.c.
vssio
tms
int2
int1 vddio vssio
vssio rdn/ng
ne
spi_rxd
csn1
clk
b
dp
i2
o1
io1
io2
tck
tdo
csn0
addr0
n.c.
csn2
ntrst
tdi
vdd
btxen
brxen
bpktcl
btxd
vddio
ant_sw
bpaen
bdclk
bmosi
bmiso
bnden
gpio14
gpio15
vss
G
H
J
nwp
addr2
vdd
vpp
vddf
vss
K
L
brclk
brxd
vssf
addr17
addr18
addr19
data0
vddq
n.c.
M
bsen
gpio12
gpio10
N
P
R
T
n.c.
data3
data1
data2
vdd
gpio11
gpio9
gpio13 vsspll vssio vddio gpio3 gpio1 boot vss
vdd data8 data7 data6 data5 data4
U
V
lpo_ lpo_
clk_n clk_p
gpio8 gpio7 gpio6 vddpll gpio5 gpio4 gpio2 gpio0
data15 data14 data13 data12 data11 data10 data9 vss
D03TL583
4.1 Pin Description and Asthe signment
Table 9 shows the pin list of STLC2415. There are 91 functional pins of which 25 are used for device test-
ing only (should not be connected in the application) and 24 supply pins. The column "PU/PD" shows the
pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This can not replace
an external pull-up/down.
The pads are grouped according to two different power supply values, as shown in column "VDD":
– V1 for 3.3 V typical 2.7 - 3.6 V range
– V2 for 1.8 V typical 1.55 - 1.95 V range
Finally the column "DIR" describes the pin directions:
– I for inputs
– O for outputs
– I/O for input/outputs
– O/t for tristate outputs
5/22
STLC2415
Table 9. Pin List
Name
Pin #
Description
DIR
PU/PD VDD
PAD
Clock and test pins
xin
B18
A18
A17
H3
System clock
Reset
I
CMOS, 3.3V TTL
compatible
schmitt trigger
V1
nreset
nrp
I
I
External flash reset
Flash Write Protect
System clock request
V2
V2
nwp
I
CMOS 1.8V
sys_clk_req C18
I/O
CMOS, 3.3V TTL
compatible, 2mA
tristate
V1
slew rate control
(1)
lpo_clk_p
lpo_clk_n
int1
V9
Low power oscillator + / Slow clock input
Low power oscillator -
I
O
I
V2
V10
C14
C15
(1)
External Interrupt used also as external wakeup
Second external interrupt
CMOS, 3.3V TTL
compatible
V1
(1)
int2
I
schmitt trigger
(1)
boot
T10
Select external boot from EMI or internal from ROM
I
V2
CMOS 1.8V
SPI interface
spi_frm
spi_clk
A2
Synchronous Serial Interface frame sync
Synchronous Serial Interface clock
I/O
I/O
CMOS, 3.3V TTL
compatible, 2mA
tristate
slew rate control
schmitt trigger
A1
V1
V1
spi_txd
spi_rxd
B1
C1
Synchronous Serial Interface transmit data
Synchronous Serial Interface receive data
O/t
I
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
(1)
CMOS, 3.3V TTL
compatible
V1
schmitt trigger
UART interface
uart1_txd
uart1_rxd
uart2_o1
uart2_o2
A15
Uart1 transmit data
Uart1 receive data
Uart2 modem output
Uart2 modem output
O/t
I
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
(2)
A16
C7
CMOS, 3.3V TTL
compatible
schmitt trigger
V1
O
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
V1
A6
O/t
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
(2)
uart2_i1
uart2_i2
uart2_io1
uart2_io2
A7
C8
C6
C5
Uart2 modem input
I
V1
CMOS, 3.3V TTL
compatible
(2)
Uart2 modem input
I
V1
(2)
Uart2 modem input/output
Uart2 modem input/output
I/O
I/O
V1
CMOS, 3.3V TTL
compatible, 2mA
tristate slew rate
control
(2)
V1
6/22
STLC2415
Table 9. Pin List (continued)
Name
Pin #
Description
Uart2 transmit data
DIR
PU/PD VDD
PAD
uart2_txd
A8
O/t
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
(2)
uart2_rxd
A9
Uart2 receive data
I
CMOS, 3.3V TTL
compatible
V1
I2C interface
i2c_dat
(3)
A14
A13
I2C data pin
I2C clock pin
I/O
I/O
V1
CMOS, 3.3V TTL
compatible, 2mA
tristate
(3)
i2c_clk
V1
slew rate control
USB interface
(1)
usb_dn
usb_dp
A10
C9
USB - pin
USB + pin
I/O
I/O
V1
(1)
V1
GPIO interface
gpio0
gpio1
gpio2
gpio3
V11
Gpio port 0
Gpio port 1
Gpio port 2
Gpio port 3
I/O
I/O
I/O
I/O
PU
CMOS, 3.3V TTL
compatible, 4mA
tristate
T11
V12
T12
PU
PU
PU
V1
V1
slew rate control
CMOS, 3.3V TTL
compatible, 4mA
tristate
slew rate control
schmitt trigger
gpio4
V13
V14
V16
V17
V18
U18
R18
T18
P18
T16
P16
R16
Gpio port 4
Gpio port 5
Gpio port 6
Gpio port 7
Gpio port 8
Gpio port 9
Gpio port 10
Gpio port 11
Gpio port 12
Gpio port 13
Gpio port 14
Gpio port 15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
CMOS, 3.3V TTL
compatible, 4mA
tristate
gpio5
V1
gpio6
slew rate control
gpio7
gpio8
gpio9
gpio10
gpio11
gpio12
gpio13
gpio14
gpio15
CMOS, 3.3V TTL
compatible, 2mA
tristate
V1
slew rate control
JTAG interface
ntrst
F18
JTAG pin
JTAG pin
I
I
PD
CMOS, 3.3V TTL
compatible
V1
V1
(1)
tck
D18
CMOS, 3.3V TTL
compatible
schmitt trigger
tms
tdi
E16
F16
JTAG pin
JTAG pin
I
I
PU
PU
CMOS, 3.3V TTL
compatible
V1
7/22
STLC2415
Table 9. Pin List (continued)
Name
tdo
Pin #
Description
DIR
PU/PD VDD
PAD
E18
JTAG pin (should be left open)
O/t
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
PCM interface
pcm_a
pcm_b
A11
C10
PCM data
I/O
I/O
I/O
I/O
PD
CMOS, 3.3V TTL
compatible, 2mA
tristate
PCM data
PD
PD
PD
V1
V1
slew rate control
pcm_sync A12
pcm_clk C11
PCM 8kHz sync
PCM clock
CMOS, 3.3V TTL
compatible, 2mA
tristate
slew rate control
schmitt trigger
Radio interface
(1)
(1)
brclk
brxd
L18
Transmit clock
Receive data
I
I
CMOS, 3.3V TTL
compatible
schmitt trigger
V1
V1
M18
bmiso
M16
RF serial interface input data
I
CMOS, 3.3V TTL
compatible
bnden
bmosi
bdclk
btxd
N16
L16
K16
K18
N18
J16
H18
G18
J18
H16
RF serial interface control
RF serial interface output data
RF serial interface clock
Transmit data
O
O
O
O
O
O
O
O
O
O
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
bsen
Synthesizer ON
Open PLL
V1
bpaen
brxen
btxen
bpktctl
ant_sw
Receive ON
Transmit ON
Packet ON
Antenna switch
CMOS, 3.3V TTL
compatible, 8mA
slew rate control
V1
(1) Should be strapped to vssio if not used
(2) Should be strapped to vddio if not used
(3) Must have a 10 kOhm pull-up.
8/22
STLC2415
Table 9. Pin List (continued)
Name
Pin #
Description
Power Supply
vsspll
vddpll
vdd
T15 PLL ground
V15 1.8V supply for PLL
A4
F1
J1
1.8V Digital supply
vdd
1.8V Digital supply
vdd
1.8V Digital supply
vdd
U1
T8
K3
M3
J3
1.8V Digital supply
vdd
1.8V Digital supply
vddf
1.8V Digital supply Flash
1.8V I/O's supply Flash
12V fast program supply Flash
vddq
vpp
vddio
vddio
vddio
vddio
vss
C13 3.3V I/O's supply
A5 3.3V I/O's supply
T13 3.3V I/O's supply
G16 3.3V I/O's supply
A3
G1
K1
V1
T9
L3
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground Flash
vss
vss
vss
vss
vssf
vssio
vssio
vssio
vssio
C12 I/O's ground
C4 I/O's ground
T14 I/O's ground
D16 I/O's ground
9/22
STLC2415
Table 9. Pin List (continued)
Name
Pin #
Description
DIR
PU/PD VDD
PAD
To be connected together on the PCB’s top layer
ne
D3
E3
I
Flash chip enable
csn0
O
External chip select bank 0
Test Only (Do NOT connect)
rdn/ng
csn1
C3
D1
E1
F3
H1
L1
External read
O
O
External chip select bank 1
External chip select bank 2
External address bit 0
External address bit 2
External address bit 17
External address bit 18
External address bit 19
External data bit 0
External data bit 1
External data bit 2
External data bit 3
External data bit 4
External data bit 5
External data bit 6
External data bit 7
External data bit 8
External data bit 9
External data bit 10
External data bit 11
External data bit 12
External data bit 13
External data bit 14
External data bit 15
csn2
O
addr0
addr2
addr17
addr18
addr19
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
O
O
O
CMOS 1.8V
4mA
M1
N1
P1
R1
T1
R3
T3
T4
T5
T6
T7
V2
V3
V4
V5
V6
V7
V8
O
V2
O
slew rate control
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
CMOS 1.8V
4mA
slew rate control
PD
V2
PD
PD
PD
PD
PD
Not Connected
n.c. C16, Not Connected
G3,
N3,
P3
10/22
STLC2415
5 FUNCTIONAL DESCRIPTION
5.1 Baseband
5.1.1 Overview
The baseband is based on Ericsson Technology Licensing Baseband Core (EBC) and it is fully compliant
with the Bluetooth® specification 1.1:
– Point to multipoint (up to 7 Slaves)
– Asynchronous Connection Less (ACL) link support giving data rates up to 721 kbps.
– Synchronous Connection Oriented (SCO) link with support for 1 voice channel over the air interface.
– HW support for all packet types:
– ACL: DM1, 3, 5 and DH1, 3, 5
– SCO: HV1, 2, 3, and DV1.
– Support for three PCM channels in the PCM interface .
– Architecture gives ultra-low power consumption.
– Ciphering support up to 128 bits key, configurable by software.
– Receiver Signal Strenght Indication (RSSI) support for power-controlled links
– Flexible voice formats to Host and over air (CVSD, PCM 16/8-bit, A-law, µ-law)
– High quality filtering of voice packets enabling excellent audio quality.
– Scatternet support, communication between two simultaneously running piconets.
– Full Bluetooth® software stack available.
– Low level link controller.
– Specific external power amplifier (PA) control for class1 support
– Extended wake-up and interrupt functionality for HID support
5.2 Processor and Memory
– ARM7TDMI
– 64 Kbyte of static RAM.
– 4 Kbyte of metal programmable ROM
– Extension of the ARM Bus to access the program in the integrated 4 MBit FLASH
5.3 Integrated Flash Memory
– 4 Mbit size
– 8 parameter blocks of 4 Kword (top configuration)
– 7 main blocks of 32 Kword
– 120 ns access time
– See datasheet of standalone product M28R400CT for more detailed information.
11/22
STLC2415
Figure 4. Block Addresses
M28R400CT
Top Boot Block Addresses
3FFFF
3F000
4 KWords
Total of 8
4 KWord Blocks
38FFF
4 KWords
38000
37FFF
32 KWords
30000
Total of 7
32 KWord Blocks
0FFFF
32 KWords
32 KWords
08000
07FFF
00000
5.3.1 Flash Signal Descriptions
– Write Protect (nwp)
Write protect is an input that gives an additional hardware protection for each block. When Write Protect
is ≤ 0.4V the Lock-Down is enabled and the protection status of the flash blocks cannot be changed.
When Write Protect is ≥ (vddq - 0.4V), the Lock-Down is disabled and the flash memory blocks can be
locked or unlocked.
– Reset (nrp)
The Reset input provides a hardware reset of the memory. When reset is ≤ 0.4V, the memory is in reset
mode: the outputs are high impedant and the current consumption is minimized. After Reset all blocks
are in Locked state. When Reset is ≥ (vddq - 0.4V), the device is in normal operation. Exiting reset mode
the device enters read array mode, but a negative transition of Chip Enable or a change of the address
is required to ensure valid data outputs.
– Vdd Supply Voltage (vddf)
Vdd provides the power supply to the internal core of the flash memory device. It is the main power sup-
ply for all operations (Read, Program and Erase)
– Vddq Supply Voltage (vddq)
Vddq provides the power supply to the I/O pins and enables all Outputs to be powered independently
from Vddf. Vddq can be tied to Vddf or can use separate supply.
12/22
STLC2415
– Vpp Program Supply Voltage (vpp)
Vpp is both a control input and a power supply pin. The two functions are selected by the voltage range
applied to the pin. The supply voltage Vddf and the program supply voltage Vpp can be applied in any
order.
If Vpp is kept in a low voltage range (0V to 3.6V) Vpp is seen as a control input. In this case a voltage
lower than 1V gives protection agains program or block erase, while 1.65V<Vpp<3.6V enables these
functions. Vpp is only sampled at the beginning of a program or block erase; a change in its value after
the operation has started does not have any effect and program or erase opereations continue.
If Vpp is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition Vpp must be stable
until the Program/Erase algorithm is completed.
– Vssf Flash Ground (vssf)
Vssf is the reference for all voltage measurements.
*
*
–
Address Inputs (Addr(1-18)/Addr(0-19)) , Data Input/Output (Data(0-15)/Data(0-15)) , Chip Enable (ne/
csn(0)) , Ouput Enable (ng/rdn) , Write Enable (nw/wrn) are connected and controlled by the Bluetooth®
*
*
*
baseband controller.
*( flash memory signals / baseband controller signals )
13/22
STLC2415
6 GENERAL SPECIFICATION
6.1 System Clock
The STLC2415 works with a single clock provided on the XIN pin. The value of this external clock should
be 13MHz ±20ppm (overall).
6.1.1 Slow Clock
The slow clock is used by the baseband as reference clock during the low power modes. Compared to the
13MHz clock, the slow clock only requires an accuracy of ±250ppm (overall).
Several options are foreseen in order to adjust the STLC2415 behaviour according to the features of the
radio used:
– if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and no slow
clock is provided by the system, a 32 kHz crystal must be used by the STLC2415 (default mode).
– if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and the system
provides a slow clock at 32kHz or 3.2kHz, this signal is simply connected to the STLC2415 (lpo_clk_p).
– if the system clock (e.g. 13MHz) is provided at all times, the STLC2415 generates from the 13MHz ref-
erence clock an internal 32kHz clock. This mode is not an optimized mode for power consumption.
6.2 Boot Procedure
The boot code instructions are the first that ARM7TDMI executes after an HW reset. All the internal de-
vice's registers are set to their default value.
There are 2 types of boot:
– Flash boot.
When boot pin is set to `1` (connected to VDD), the STLC2415 boots on its flash memory.
– UART download boot from ROM.
When boot pin is set to `0` (connected to GND), the STLC2415 boots on its internal ROM (needed to
download the new firmware in the flash). When booting on the internal ROM, the STLC2415 will monitor
the UART interface for approximately 1.4 second. If there is no request for code downloading during this
period, the ROM jumps to flash.
6.3 Clock Detection
The STLC2415 has an automatic slow clock frequency detection (32kHz, 3.2kHz or none).
6.4 Master Reset
When the device's reset is held active (NRESET is low), UART1_TXD and UART2_TXD are set to input
state. When the NRESET returns high, the device starts to boot.
Remark: The device should be held in active reset for minimum 20ms in order to guarantee a complete
reset of the device.
6.5 Interrupts/Wake-up
The external pins int1 and int2, and up to 8 GPIOs can be used both as external interrupt source and as
wake-up source. In addition the chip can be woken-up by USB, UART1_RXD, UART2_RXD.
14/22
STLC2415
7 INTERFACES
7.1 UART Interface
The chip contains two enhanced (128 byte transmit FIFO and 128 byte receive FIFO, sleep mode, 127 Rx
and 128 Tx interrupt tresholds) UARTs, named UART1 and UART2, compatible with the standard M16550
UART.
For UART1, only Rx and Tx signals are available (used for debug purposes).
UART2 features:
– standard HCI UART transport layer:
– all HCI commands as described in the Bluetooth® specification 1.1
– ST specific HCI command (check STLC2415 Software Interface document for more information)
– RXD, TXD, CTS, RTS on permanent external pins
– 128-byte FIFOs, for transmit and for receive
– Default configuration: 57.600 kbps
– Specific HCI command to change to the following baud rates:
Table 10. List of Supported Baud Rates
Baud rate
–
57.6 kbps (default)
38.4 k
4800
2400
1800
1200
900
921.6k
460.8 k
230.4 k
153.6 k
115.2 k
76.8 k
28.8 k
19.2 k
14.4 k
9600
600
300
7200
7.2 Synchronous Serial Interface
The Synchronous Serial Interface (SSI) (or the Synchronous Peripheral Interface (SPI)) is a flexible mod-
ule supporting full-duplex and half-duplex synchronous communications with external devices in Master
and Slave mode. It allows the STLC2415 to communicate with peripheral devices.
The Synchronous Serial Interface is also capable of inter processor communications in a multiple-master
system. This interface is flexible enough to interface directly with numerous standard product peripherals.
This Synchronous Serial Interface peripheral features:
– full duplex, four-wire synchronous transfers.
– Microwire half duplex transfer using 8-bit control message
– programmable clock polarity and phase.
– transmit data pin tri state able when not transmitting
– Master or Slave operation
– Programmable clock bit rate up to XIN/4
– Programmable data frame from 4 bits to 16 bits.
– Independent transmit and receive 16 words FIFO.
– Internal loopback
7.3 I2C Interface
Used to access I2C peripherals.
The interface is a fast master I2C; it has full control of the interface at all times. I2C slave functionality is
not supported.
15/22
STLC2415
7.4 USB Interface
A USB device interface compliant to USB specification v1.1 is connected to the ARM processor. This al-
lows the chip to be connected to a Universal Serial Bus that can transmit data and/or voice through the
internal USB transceiver.
Figure 5 gives an overview of the main components needed for supporting the USB interface, as specified
in the Bluetooth® Core Specification (Part H:2). For clarity, the serial interface (including the UART Trans-
port Layer) is also shown.
Figure 5. USB Interface
HCI
USB TRANSPORT LAYER
UART TRANSPORT LAYER
SERIAL DRIVER
RTOS
USB
DEVICE
REGISTERS
FIFOs
UART
DEVICE
REGISTERS
FIFOs
USB DRIVER
IRQ
IRQ
STLC2415 HW
D03TL588
The USB device registers and FIFOs are memory mapped. The USB Driver will use these registers to ac-
cess the USB interface. The equivalent exists for the HCI communication over UART.
For transmission to the host, the USB & Serial Drivers interface with the HW via a set of registers and
FIFOs, while in the other direction, the hardware may trigger the Drivers through a set of interrupts (iden-
tified by the RTOS, and directed to the appropriate Driver routines).
7.5 JTAG Interface
The JTAG interface is compliant with the JTAG IEEE Std 1149.1. Its allows both the boundary scan of the
digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 devel-
opment tools.
7.6 RF Interface
The STLC2415 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirection-
al serial interface for control).
7.7 PCM Voice Interface
The PCM interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or STw5094)
16/22
STLC2415
including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), µ-Law (8bit) or
A-Law (8bit). By default the codec interface is configured as master. The encoding on the air interface is
programmable to be CVSD, A-Law or µ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
– PCM_CLK : PCM clock
– PCM_SYNC : PCM 8kHz sync
– PCM_A : PCM data
– PCM_B : PCM data
Directions of PCM_A and PCM_B are software configurable.
Figure 6. PCM (A-law, µ-law) Standard Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCM_CLK
PCM_SYNC
PCM_A
B
B
B
PCM_B
B
D02TL558
125µs
Figure 7. Linear Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
D02TL559
125µs
Table 11. PCM Interface Timing.
Symbol
Description
Min
Typ
Max
Unit
PCM Interface
Fpcm_clk
Frequency of PCM_CLK (master)
-
2048
8
kHz
kHz
ns
F
Frequency of PCM_SYNC
High period of PCM_CLK
Low period of PCM_CLK
High period of PCM_SYNC
pcm_sync
t
200
200
200
100
100
100
WCH
t
ns
WCL
WSH
t
ns
t
Setup time, PCM_SYNC high to PCM_CLK low
ns
SSC
SDC
HCD
DCD
t
Setup time, PCM_A/B input valid to PCM_CLK low
Hold time, PCM_CLK low to PCM_A/B input invalid
Delay time, PCM_CLK high to PCM_A/B output valid
ns
t
t
ns
150
ns
17/22
STLC2415
Figure 8. PCM Interface Timing
t
WCL
PCM_CLK
t
WCH
t
SSC
PCM_SYNC
t
SDC
t
WSH
t
HCD
MSB
MSB-1 MSB-2 MSB-3 MSB-4
PCM_A/B in
t
DCD
MSB
MSB-1 MSB-2 MSB-3 MSB-4
D02TL557
PCM_B/A out
8 HCI UART TRANSPORT LAYER
The UART Transport Layer has been specified by the Bluetooth® SIG ( Part H:3), and allows HCI level
communication between a host controller (STLC2415) and a host (e.g. PC), via a RS232 interface.
The objective of this HCI UART Transport Layer is to make it possible to use the Bluetooth® HCI over a
serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the
UART communication is free from line errors.
8.1 UART Settings
The HCI UART Transport Layer uses the following settings:
– Baud rate: Configurable (Default baud rate: 57.600 kbps)
– Number of data bits: 8
– Parity bit: no parity
– Stop bit: 1 stop bit
– Flow control: RTS/CTS
– Flow-off response time: 3 ms
Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for
flow control of HCI, since HCI has its own flow control mechanisms for HCI commands, HCI events and
HCI data.
If CTS is 1, then the Host/Host Controller is allowed to send.
If CTS is 0, then the Host/Host Controller is not allowed to send.
The flow-off response time defines the maximum time from setting RTS to 0 until the byte flow actually
stops. The signals should be connected in a null-modem fashion; i.e. the local TXD should be connected
to the remote RXD and the local RTS should be connected to the remote CTS and vice versa.
Figure 9. UART Transport Layer
BLUETHOOTH
HOST
CONTROLLER
BLUETHOOTH HCI
BLUETHOOTH
HOST
HCI UART TRANSPORT LAYER
D02TL556
18/22
STLC2415
9 HCI USB TRANSPORT LAYER
The USB Transport Layer has been specified by the Bluetooth® SIG (Part H:2), and allows HCI level com-
munication between a host controller (STLC2415) and a host (e.g. PC), via a USB interface. The USB
Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares
it for transmission over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from
USB data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Lay-
er does not interprete the contents (payload) of the HCI messages; it only examines the header.
10 POWER CLASS1 SUPPORT
The chip can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this
purpose in order to avoid digital/analog noise loops in the radio.
The Class1_En register enables the alternate functions of GPIO[15:6] to generate the signals for driving
an external PA in a Bluetooth® power class1 application.
Every bit enables a dedicated signal on a GPIO pin, as described in table 12.
Table 12. Power Class 1 Functionality
Class1_En bit
rxon
involved GPIO
gpio[6]
description (when class1_En bit = ‘1’)
outputs a copy of rx_on pin to switch LNA/RF switch on/off
outputs an inverted copy of rx_on pin to switch LNA/RF switch on/off
Bit 0 of the PA value for the current connection
Bit 1 of the PA value for the current connection
Bit 2 of the PA value for the current connection
Bit 3 of the PA value for the current connection
Bit 4 of the PA value for the current connection
Bit 5 of the PA value for the current connection
Bit 6 of the PA value for the current connection
Bit 7 of the PA value for the current connection
not rxon
PA0
gpio[7]
gpio[8]
PA1
gpio[9]
PA2
gpio[10]
gpio[11]
gpio[12]
gpio[13]
gpio[14]
gpio[15]
PA3
PA4
PA5
PA6
PA7
rx_on is the same as the rx_on output pin. Not rx_on is the inverted signal, in order to save components
on the application board.
PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the base-
band core. The Power Level programmed for a certain Bluetooth® connection is manged by the firmware,
as specified in the Bluetooth® SIG spec.
19/22
STLC2415
Figure 10. LFBGA120 (Low Fne Ball Grid Array) Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN. TYP. MAX. MIN.
TYP. MAX.
0.055
OUTLINE AND
MECHANICAL DATA
A
A1
A2
b
1.40
0.20
0.008
1
0.039
0.25
0.30
0.35 0.010 0.012 0.014
D
9.90 10.00 10.10 0.390 0.394 0.398
D1
D2
E
8.50
6.50
0.335
0.256
9.90 10.00 10.10 0.390 0.394 0.398
E1
E2
eD
eE
FD
FE
mD
mE
n
8.50
6.50
0.335
0.256
0.50 basic
0.50 basic
0.75
0.020 basic
0.020 basic
0.029
0.75
0.029
18
18
120 balls
SE
SD
0.25 basic
0.25 basic
0.0098 basic
0.0098 basic
Body: 10 x 10 x 1.4mm
Tolerance
aaa
bbb
ddd
eee
fff
0.15
0.10
0.08
0.15
0.05
0.006
0.0039
0.0031
0.006
LFBGA120
Low Fine Ball Grid Array
0.002
7513355 A
20/22
STLC2415
Table 13. Revision History
Date
Revision
Description of Changes
First Issue in EDOCS DMS.
August 2004
September 2004
1.1
2
Editorial corrections.
Clock support added in section 1.
Section 2 corrected.
Modified the figures 2 and 3.
Modified the tables 5, 7 and 8.
‘To be connected’ added in table 9.
Section 5.3.1 modified.
Section 6.2 corrected.
Section 6.5 modified.
Section 7.3 updated and figure removed.
21/22
STLC2415
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
The BLUETOOTH® word mark and logos are owned by the Bluetooth SIG, Inc. and any use of such marks by STMicroelectronics is under license.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
22/22
相关型号：
©2020 ICPDF网 联系我们和版权申明