STLC2411 [STMICROELECTRONICS]
BLUETOOTH BASEBAND; 蓝牙基带
| 型号： | STLC2411 |
| 厂家： | 
ST |
| 描述： | BLUETOOTH BASEBAND |
| 文件： | 总25页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLC2411
BLUETOOTH™ BASEBAND
PRELIMINARY DATA
1 FEATURES
Figure 1. Package
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Pin to pin compatible with the previous version
STLC2410B
Ericsson Technology Licensing Baseband Core
(EBC)
Bluetooth™ specification compliance: V1.1 and
V1.2
Point-to-point, point-to-multi-point (up to 7 slaves)
and scatternet capability
Asynchronous Connection Oriented (logical
transport) link
Synchronous Connection Oriented (SCO) links: 2
simultaneous SCO channels
Supports Pitch-Period Error Concealment (PPEC)
– Improves speech quality in the vicinity of in-
terference
– Improves coexistence with WLAN
– Works at receiver, no Bluetooth implication
Adaptive Frequency Hopping (AFH): hopping
kernel, channel assessment as Master and as Slave
Faster Connection: Interlaced scan for Page and
Inquiry scan, first FHS without random backoff,
RSSI used to limit range
Extended SCO (eSCO) links
Standard BlueRF bus interface
QoS Flush
Clock support
– System clock input:
TFBGA132 (8x8x1.2mm)
Table 1. Order Codes
Temp. Range
Part Number
Package
STLC2411
TFBGA132
-40 to +85 °C
– eSCO: EV3, 5
Communication interfaces
■
– Synchronous Serial Interface, supporting up
to 32 bit data and different industry standards
– Two enhanced 16550 UARTs with 128 byte
FIFO depth
■
■
– 12Mbps USB interface
– Fast master I2C bus interface
– Multi slot PCM interface
– 16 programmable GPIOs
– 2 external interrupts and various interrupt
possibilities through other interfaces
Ciphering support for up to 128-bit key
Efficient support for WLAN coexistence in
collocated scenario
Receiver Signal Strength Indication (RSSI) support
for power-controlled links
Separate control for external power amplifier (PA)
for class1 power support.
Software support
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any integer value from 12 … 33 MHz
– LPO clock input at 3.2 and 32 kHz or via the
embedded 32 kHz crystal oscillator cell
ARM7TDMI 32-bit CPU
Memory organization
– 64KByte on-chip RAM
■
■
– Low level (up to HCI) stack or embedded
stack with profiles
– 4KByte on-chip boot ROM
– Programmable external memory interface (EMI)
– Supports byte and half word access
– Supports up to 3 external RAM banks (1
Mbyte/ bank)
– Supports up to 2 Mbyte external flash
memory
Low power architecture with 2 different low power
levels:
– Sleep Mode
– Deep Sleep Mode
HW support for packet types
– ACL: DM1, 3, 5 and DH1, 3, 5
– SCO: HV1, 3 and DV
– Support of UART and USB HCI transport layers
Compliant to automotive specification AEC-Q100
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1.1 Applications Features
Typical applications in which the STLC2411 can
be used are:
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Portable computers, PDA
Modems
Handheld data transfer devices
Cameras
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Computer peripherals
Other type of devices that require the wireless
communication provided by Bluetooth™
Cable replacement
■
REV. 1
1/25
June 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STLC2411
2 DESCRIPTION
The STLC2411 offers a compact and complete solution for short-range wireless connectivity. It incorpo-
rates all the lower layer functions of the Bluetooth™ protocol. The microcontroller allows the support of all
data packets of Bluetooth™ in addition to voice. The embedded controller can be used to run the Blue-
tooth™ protocol and application layers if required. The software is located in an external memory accessed
through the external memory interface.
3 QUICK REFERENCE DATA
3.1 Absolute Maximum Ratings
Operation of the device beyond these conditions is not guaranteed.
Sustained exposure to these limits will adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
VDD
Conditions
Min
Max
2.5
Unit
V
Supply voltage core
Supply voltage I/O
VSS - 0.5
VDDIO
VIN
4
V
Input voltage on any digital pin
Storage temperature
VSS - 0.5
-65
VDDIO + 0.3
+150
V
Tstg
°C
°C
Tlead
Lead temperature < 10s
+250
3.2 Operating Ranges
Operating ranges define the limits for functional operation and parametric characteristics of the device.
Functionality outside these limits is not implied.
Table 3. Operating Ranges
Symbol
Conditions
Min
1.55
2.7
Typ
1.8
3.3
Max
1.95
3.6
Unit
V
VDD
Supply voltage digital core and emi pads
VDDIO_RADIO Supply voltage radio interface
(Values are given for the STLC2150 BT radio.)
V
VDDIO
Tamb
Supply voltage digital IO
Operating ambient temperature
1.65
-40
3.3
3.6
V
+85
°C
3.3 I/O specifications
Depending on the interface, the I/O voltage is typical 1.8V (interface to the flash memory) or typical 3.3V
(all the other interfaces). These I/Os comply with the EIA/JEDEC standard JESD8-B.
3.3.1 Specifications for 3.3V I/Os
Table 4. LVTTL DC Input Specification (3V<VDDIO<3.6V)
Symbol
Vil
Parameter
Low level input voltage
Conditions
Min
Typ
Max
Unit
V
0.8
Vih
High level input voltage
Schmitt trigger hysteresis
2
V
Vhyst
0.4
V
2/25
STLC2411
Table 5. LVTTL DC Output Specification (3V<VDDIO<3.6V)
Symbol
Vol
Parameter
Conditions
Min
Typ
Max
Unit
V
Low level output voltage Iol = X mA
High level output voltage Ioh =-X mA
0.15
Voh
VDDIO-0.15
V
Note: X is the source/sink current under worst-case conditions according to the drive capability. (See table 8, pad information for value of X).
3.3.2 Specifications for 1.8V I/Os
Table 6. DC Input Specification (1.55V<VDD<1.95V)
Symbol
Vil
Parameter
Conditions
Min
Typ
Max
Unit
V
Low level input voltage
High level input voltage
Schmitt trigger hysteresis
0.35*VDD
Vih
0.65*VDD
0.2
V
Vhyst
0.3
0.5
V
Table 7. DC Output Specification (1.55V<VDD<1.95V)
Symbol
Vol
Parameter
Conditions
Min
Typ
Max
Unit
V
Low level output voltage Iol = X mA
0.15
Voh
High level output
voltage
Ioh =-X mA
VDD-0.15
V
Note: X is the source/sink current under worst-case conditions according to the drive capability. (See table 8, pad information for value of X).
3.4 Current Consumption
Table 8. Typical power consumption of the STLC2411 and External STM Flash (M28R400CB) using
UART (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) (Indicative only)
Core
STLC2411 State
IO
Unit
Slave
5.10
0.94
7.60
7.90
8.70
127
Master
5.10
0.94
6.99
7.20
7.90
n.a.
Standby (no low power mode)
0.13
0.13
0.13
0.13
0.14
5
mA
mA
mA
mA
mA
µA
Standby (low power mode enabled)
ACL connection (no transmission)
ACL connection (data transmission)
SCO connection (no codec connected)
Inquiry and Page scan (low power mode enabled)
Low Power mode (32 kHz crystal)
20
20
0
µA
3/25
STLC2411
4 BLOCK DIAGRAM AND ELECTRICAL SCHEMA
Figure 2. Block Diagram and Electrical Schematic
JTAG
5
4
2
VDD
PCM
PCM
100nF
INTERRUPT
CONTROLLER
EXT._INT1/2
2
2
USB
I2C
USB
VDDIO
100nF
I2C
VDDIO
ARM7
TDMI
4
APB
BRIDGE
100nF
SPI
SPI
BLUETOOTH®
CORE
13
16
RADIO
I/F
RF BUS
TIMER
GPIO
GPIO(O..15)
D
M
A
RAM
8
START
DETECT
UART
UART
UART2
UART1
(*)
2
2
22pF
22pF
BOOT
ROM
UART
FIFO
LPOCLKP
LPO
Y2
32kHz
NRESET
SYS_CLK_REQ
SYSTEM
CONTROL
LPOCLKN
VDDPLL
EMI
VDD
VDD
100nF
4
3
20
16
100nF
D02TL550A
XIN
BOOT WAIT CSN(0..2)
RDN/WRN
ADDR(0..19) DATA(0..15)
(*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal
4/25
STLC2411
5 PINOUT
Figure 3. Pin out (Bottom view)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
vddio_
radio
gpio9 gpio11gpio14
brxd bmosi bdclk bpaen brxen ant_sw tdi
ntrst test
xin
A
sys_
clk_req
n.c. gpio10gpio13 n.c. brclk bnden btxd vdd btxen vddio tdo
gpio8 vddpll gpio12gpio15 vssio bmiso bsen vss bpktctl vssio tms
vsspll gpio6 gpio7
tck nreset
B
C
D
E
F
uart1_ uart1_ i2c_
rxd
txd
dat
i2c_clk int1
int2
pcm_
sync
gpio3 gpio4 gpio5
vddio vssio
pcm_
gpio0 gpio1 gpio2
pcm_a pcm_b
clk
lpo_ lpo_
boot
uart2_ usb_ usb_
rxd dp dn
clk_p clk_n
G
H
J
data data
wait
uart2_ uart2_ uart2_
i2 i1 txd
14
15
data data data
uart2_ uart2_ uart2_
13
12
11
io1
o2
o1
data data
uart2_
io2
vss
vss
vdd
10
9
K
L
vdd
vss
vdd
spi_frm vssio vddio
spi_ spi_
data8 data7 data6 data0 addr17 vss addr13 addr10 addr5 addr2 vdd csn1
txd
clk
M
N
P
spi_
rxd
data5 data4 data2 addr19 addr16 vdd addr12 addr9 addr6 addr3 vss csn2 wrn
data3 n.c. data1 addr18 addr15 addr14 addr11 addr8 addr7 addr4 addr1 addr0 csn0 rdn
D02TL551
5.1 Pin Description and Assignment
Table 9 shows the pin list of the STLC2411. There are 107 digital functional pins and 22 supply pins. The
column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left
open. This cannot replace an external pull-up/down.
The pads are grouped according to three different power supply values, as shown in column "VDD":
– V1
– V1_radio for 3.3 V typical 2.7 - 3.6 V range (for STLC2150 BT radio)
– V2 for 1.8 V typical 1.55 - 1.95 V range
for 3.3 V typical 1.65 - 3.6 V range
Note:
V1 and V1_radio can be connected together to the same 3.3 V typical supply for STLC2150 BT radio.
Finally the column "DIR" describes the pin directions:
– I for Inputs
– O for Outputs
– I/O for Input/Outputs
– O/t for tri-state outputs
5/25
STLC2411
Table 9. STLC2411 Pin List
Name
Pin #
Description
DIR
PU/PD VDD
PAD
Interface to external memory (supports up to 2 Mbyte Flash and byte access for up to1 Mbyte RAM.)
(1)
int1
int2
D2
D1
External Interrupt used also as external wakeup
Second external interrupt
I
I
CMOS, 3.3V TTL
compatible
schmitt trigger
V1
V2
(1)
(1)
boot
G14
H12
P1
Select external boot from EMI or internal from ROM
EMI external wait signal (left open)
External read
I
I
CMOS 1.8V
wait
PD
rdn
O
wrn
N2
External write
O
csn0
P2
External chip select bank 0
External chip select bank 1
External chip select bank 2
External address bit 0
External address bit 1
External address bit 2
External address bit 3
External address bit 4
External address bit 5
External address bit 6
External address bit 7
External address bit 8
External address bit 9
External address bit 10
External address bit 11
External address bit 12
External address bit 13
External address bit 14
External address bit 15
External address bit 16
External address bit 17
External address bit 18
External address bit 19
External data bit 0
O
csn1
M3
N3
O
csn2
O
addr0
addr1
addr2
addr3
addr4
addr5
addr6
addr7
addr8
addr9
addr10
addr11
addr12
addr13
addr14
addr15
addr16
addr17
addr18
addr19
data0
data1
data2
data3
data4
data5
P3
O
P4
O
M5
N5
O
O
P5
O
M6
N6
O
O
CMOS 1.8V
4mA
P6
O
V2
slew rate control
P7
O
N7
O
M7
P8
O
O
N8
O
M8
P9
O
O
P10
N10
M10
P11
N11
M11
P12
N12
P14
N13
N14
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
PD
PD
PD
PD
PD
PD
External data bit 1
External data bit 2
CMOS 1.8V 4mA
slew rate control
V2
External data bit 3
External data bit 4
External data bit 5
6/25
STLC2411
Table 9. STLC2411 Pin List (continued)
Name
data6
Pin #
M12
M13
M14
K13
K14
J12
Description
DIR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PU/PD VDD
PAD
External data bit 6
External data bit 7
External data bit 8
External data bit 9
PD
PD
PD
PD
data7
data8
data9
CMOS 1.8V
4mA
slew rate control
data10
data11
data12
data13
data14
data15
SPI interface
spi_frm
spi_clk
External data bit 10
External data bit 11
External data bit 12
External data bit 13
External data bit 14
External data bit 15
PD
V2
PD
J13
PD
PD
PD
PD
J14
H14
H13
L3
Synchronous Serial Interface frame sync
Synchronous Serial Interface clock
I/O
I/O
CMOS, 3.3V TTL
compatible, 2mA
tri-state
slew rate control
schmitt trigger
M1
V1
V1
spi_txd
spi_rxd
M2
N1
Synchronous Serial Interface transmit data
Synchronous Serial Interface receive data
O/t
I
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
(1)
CMOS, 3.3V TTL
compatible
V1
schmitt trigger
UART interface
uart1_txd
uart1_rxd
uart2_o1
uart2_o2
C2
C3
J1
Uart1 transmit data
Uart1 receive data
Uart2 modem output
Uart2 modem output
O/t
I
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
(2)
CMOS, 3.3V TTL
compatible
schmitt trigger
V1
O
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
V1
J2
O/t
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
(2)
uart2_i1
uart2_i2
uart2_io1
uart2_io2
H2
H3
J3
Uart2 modem input
I
V1
CMOS, 3.3V TTL
compatible
(2)
Uart2 modem input
I
V1
(2)
Uart2 modem input/output
Uart2 modem input/output
I/O
I/O
V1
CMOS, 3.3V TTL
compatible, 2mA
tri-state slew rate
control
(2)
K1
V1
uart2_txd
H1
Uart2 transmit data
O/t
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
7/25
STLC2411
Table 9. STLC2411 Pin List (continued)
Name
Pin #
Description
DIR
PU/PD VDD
PAD
(2)
uart2_rxd
G3
Uart2 receive data
I
CMOS, 3.3V TTL
compatible
V1
I2C interface
i2c_dat
(3)
C1
D3
I2C data pin
I2C clock pin
I/O
I/O
V1
CMOS, 3.3V TTL
compatible, 2mA
tri-state
(3)
i2c_clk
V1
slew rate control
USB interface
(1)
usb_dn
usb_dp
G1
G2
USB - pin (Needs a series resistor of 27 Ω ±5%)
USB + pin (Needs a series resistor of 27 Ω ±5%)
I/O
I/O
V1
(1)
V1
GPIO interface
gpio0
gpio1
gpio2
gpio3
F14
Gpio port 0
Gpio port 1
Gpio port 2
Gpio port 3
I/O
I/O
I/O
I/O
PU
CMOS, 3.3V TTL
compatible, 4mA
tri-state
F13
F12
E14
PU
PU
PU
V1
V1
slew rate control
CMOS, 3.3V TTL
compatible, 4mA
tri-state
slew rate control
schmitt trigger
gpio4
E13
E12
D13
D12
C14
A14
B13
A13
C12
B12
A12
C11
Gpio port 4
Gpio port 5
Gpio port 6
Gpio port 7
Gpio port 8
Gpio port 9
Gpio port 10
Gpio port 11
Gpio port 12
Gpio port 13
Gpio port 14
Gpio port 15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
CMOS, 3.3V TTL
compatible, 4mA
tri-state
gpio5
V1
gpio6
slew rate control
gpio7
gpio8
gpio9
gpio10
gpio11
gpio12
gpio13
gpio14
gpio15
CMOS, 3.3V TTL
compatible, 2mA
tri-state
V1
slew rate control
Clock and test pins
xin
A1
B2
System clock
Reset
I
I
CMOS, 3.3V TTL
compatible
schmitt trigger
V1
nreset
sys_clk_req B1
System clock request
I/O
CMOS, 3.3V TTL
compatible, 2mA
tri-state
V1
V2
slew rate control
(1)
lpo_clk_p
lpo_clk_n
G13
G12
Low power oscillator + / Slow clock input
Low power oscillator -
I
O
8/25
STLC2411
Table 9. STLC2411 Pin List (continued)
Name
test
Pin #
Description
DIR
PU/PD VDD
PAD
A2
Test mode
I
PD
V1
CMOS, 3.3V TTL
compatible
JTAG interface
ntrst
A3
JTAG pin
JTAG pin
I
I
PD
V1
CMOS, 3.3V TTL
compatible
(1)
tck
B3
CMOS, 3.3V TTL
compatible
V1
schmitt trigger
tms
tdi
C4
A4
B4
JTAG pin
JTAG pin
I
I
PU
V1
PU
CMOS, 3.3V TTL
compatible
tdo
JTAG pin (should be left open)
O/t
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
PCM interface
pcm_a
pcm_b
F2
F1
PCM data
I/O
I/O
I/O
I/O
PD
CMOS, 3.3V TTL
compatible, 2mA
tri-state
PCM data
PD
PD
PD
V1
V1
slew rate control
pcm_sync E1
pcm_clk F3
PCM 8kHz sync
PCM clock
CMOS, 3.3V TTL
compatible, 2mA
tri-state
slew rate control
schmitt trigger
Radio interface
(1)
(1)
brclk
brxd
B10
Transmit clock
Receive data
I
I
CMOS, 3.3V TTL
compatible
schmitt trigger
V1_radio
V1_radio
A10
C9
bmiso
RF serial interface input data
I
CMOS, 3.3V TTL
compatible
bnden
bmosi
bdclk
btxd
B9
A9
A8
B8
C8
A7
A6
B6
C6
A5
RF serial interface control
RF serial interface output data
RF serial interface clock
Transmit data
O
O
O
O
O
O
O
O
O
O
CMOS, 3.3V TTL
V1_radio compatible, 2mA
slew rate control
bsen
Synthesizer ON
Open PLL
bpaen
brxen
btxen
bpktctl
ant_sw
Receive ON
Transmit ON
Packet ON
Antenna switch
CMOS, 3.3V TTL
V1_radio compatible, 8mA
slew rate control
(1) Should be strapped to vssio if not used
(2) Should be strapped to vddio if not used
(3) Must have a 10 kOhm pull-up.
9/25
STLC2411
Table 9. Pin List (continued)
Name
Pin #
Description
Power Supply
vsspll
vddpll
vdd
D14 PLL ground
C13 1.8V supply for PLL
B7
K2
1.8V Digital supply
1.8V Digital supply
vdd
vdd
L12 1.8V Digital supply
L14 1.8V Digital supply
vdd
vdd
M4
N9
1.8V Digital supply
1.8V Digital supply
vdd
vddio_radio A11 3.3V Supply voltage radio interface
vddio
vddio
vddio
vss
B5
E3
L1
C7
K3
3.3V Supply voltage digital IO
Digital ground
Digital ground
vss
vss
K12 Digital ground
L13 Digital ground
vss
vss
M9
N4
C5
Digital ground
Digital ground
I/O's ground
vss
vssio
vssio
vssio
vssio
C10 I/O's ground
E2
L2
I/O's ground
I/O's ground
10/25
STLC2411
6 FUNCTIONAL DESCRIPTION
6.1 Baseband
– WLAN coexistence. See also 7.12. WLAN.
6.1.1 Baseband 1.1 Features
The baseband is based on Ericsson Technology Licensing Baseband Core (EBC) and it is compliant with
the Bluetooth specification 1.1:
– Point to multipoint (up to 7 Slaves)
– Asynchronous Connection Less (ACL) link support giving data rates up to 721 kbps
– Synchronous Connection Oriented (SCO) link with support for 2 voice channels over the air interface.
– Flexible voice format to host and over the air (CVSD, PCM 13/16 bits, A-law, µ-law)
– HW support for packet types: DM1, 3, 5; DH1, 3, 5; HV1, 3; DV
– Scatternet capabilities (Master in one piconet and Slave in the other one; Slave in two piconets). All
scatternet v.1.1 errata supported.
– Ciphering support up to 128 bits key
– Paging modes R0, R1, R2
– Channel Quality Driven Data Rate
– Full Bluetooth software stack available
– Low-level link controller
6.1.2 Baseband 1.2 Features
The baseband part is also compliant with the Bluetooth specification 1.2:
– Extended SCO (eSCO) links: supports EV3 and EV5 packets. See also 7.6. eSCO.
– Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave. See
also 7.7. AFH.
– Faster Connection: Interlaced scan for Page and Inquiry scan, answer FHS at first reception, RSSI used
to limit range. See also 7.8. Faster Connection.
– QoS Flush. See also 7.9. QoS.
– Synchronization: the local and the master BT clock are available via HCI commands for synchronization
of parallel applications on different slaves.
– L2CAP Flow & Error control
– LMP Improvements
– LMP SCO handling
– Parameter Ranges update
11/25
STLC2411
7 GENERAL SPECIFICATION
7.1 SYSTEM CLOCK
The STLC2411 works with a single clock provided on the XIN pin. The value of this external clock should
be any integer value from 12 … 33 MHz ±20ppm (overall).
7.1.1 SLOW CLOCK
The slow clock is used by the baseband as reference clock during the low power modes. The slow clock
requires an accuracy of ±250ppm (overall).
Several options are foreseen in order to adjust the STLC2411 behaviour according to the features of the
radio used:
– If the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and no slow
clock is provided by the system, a 32 kHz crystal must be used by the STLC2411 (default mode).
– If the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and the system
provides a slow clock at 32kHz or 3.2kHz, this signal is simply connected to the STLC2411 (lpo_clk_p).
– If the system clock (e.g. 13MHz) is provided at all times, the STLC2411 generates from the reference
clock an internal 32kHz clock. This mode is not an optimized mode for power consumption.
7.2 BOOT PROCEDURE
The boot code instructions are the first that ARM7TDMI executes after a HW reset. All the internal device's
registers are set to their default value.
There are 2 types of boot:
– External memory boot.
When boot pin is set to `1` (connected to VDD), the STLC2411 boots on its external memory
– UART download boot from ROM.
When boot pin is set to `0` (connected to GND), the STLC2411 boots on its internal ROM (needed to
download the new firmware in the external memory).
When booting on the internal ROM, the STLC2411 will monitor the UART interface for approximately 1.4
second. If there is no request for code downloading during this period, the ROM jumps to external memory.
7.3 CLOCK DETECTION
The STLC2411 has an automatic slow clock frequency detection (32kHz, 3.2kHz or none).
7.4 MASTER RESET
When the device's reset is held active (nreset is low), uart1_txd and uart2_txd are set to input state. When
the nreset returns high, the device starts to boot.
Remark: The device should be held in active reset for minimum 20ms in order to guarantee a complete
reset of the device.
7.5 INTERRUPTS/WAKE-UP
All GPIOs can be used both as external interrupt source and as wake-up source. In addition, the chip can
be woken-up by USB, uart1_rxd, uart2_rxd, int1, int2.
7.6 V1.2 detailed functionality - Extended SCO
User Perspective - Extended SCO
This function gives improved voice quality since it enables the possibility to retransmit lost or corrupted
voice packets in both directions.
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STLC2411
Technical perspective - Extended SCO
eSCO incorporates CRC, negotiable data rate, negotiable retransmission window and multi-slot packets.
Retransmission of lost or corrupted packets during the retransmission window guarantees on-time deliv-
ery.
Figure 4. eSCO
SCO
SCO
SCO
SCO
ACL
ACL
SCO
SCO
t
eSCO retransmission window
7.7 V1.2 detailed functionality - Adaptive Frequency Hopping
User Perspective - Adaptive Frequency Hopping
In the Bluetooth spec 1.1 the Bluetooth devices hop in the 2.4 GHz band over 79-channels. Since WLAN
802.11 has become popular, there are specification improvements in the 1.2-SIG spec for Bluetooth
where the Bluetooth units can avoid the jammed bands and thereby provide an improved co-existence
with WLAN.
Technical perspective - Adaptive Frequency Hopping
Figure 5. AFH
AFH(79)
f
WLAN used frequency
t
f
AFH(19<N<79)
WLAN used frequency
t
First the Master and/or the Slaves identify the jammed channels. The Master decides on the channel dis-
tribution and informs the involved slaves. The Master and the Slaves, at a predefined instant, switch to the
new channel distribution scheme.
No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses the same hop
frequency for transmission as for reception.
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STLC2411
7.8 V1.2 detailed functionality - Faster Connection
User Perspective - Faster Connection
This feature gives the User about 65% faster connection on average when enabled compared to Bluetooth
spec 1.1 connection procedure.
Technical perspective - Faster Connection
The faster Inquiry functionality is based on a removed/shortened random back off and also a new Inter-
laced Inquiry scan scheme.
The faster Page functionality is based on Interlaced Page Scan.
7.9 V1.2 detailed functionality - Quality of Service
User Perspective - Quality of Service
Small changes to the BT1.1 spec regarding Quality of Service makes a large difference by allowing all
QoS parameters to be communicated over HCI to the link manager that enables efficient BW manage-
ment. Here after a short list of user perspectives:
1) Flush timeout: enables time-bounded traffic such as video streaming to become more robust when the
channel degrades. It sets the maximum delay of an L2CAP frame. It does not enable multiple streams
in one piconet, or heavy data transfer at the same time.
2) Simple latency control: allows the host to set the poll interval. Provides enough support for HID devic-
es mixed with other traffic in the piconet.
7.10 Low power modes
To save power, two low power modes are supported. Depending of the Bluetooth and of the Host's activ-
ity, the STLC2411 autonomously decides to use Sleep Mode or Deep Sleep Mode.
Table 10. Low power modes
Low power mode
Sleep Mode
Description
The STLC2411:
- Accepts HCI commands from the Host.
- Supports page- and inquiry scans.
- Supports Bluetooth links that are in Sniff, Hold or Park.
- Can transfer data over Bluetooth links.
- The system clock is still active in part of the design.
Deep Sleep Mode
The STLC2411:
- Does not accept HCI commands from the Host.
- Keeps track of page- and inquiry scan activities.
Switches between sleep and active mode when it is time to scan.
- Supports Bluetooth links that are in Sniff, Hold or Park.
- Does not transfer data over Bluetooth links.
- The system clock is not active in any part of the design.
Note: Deep Sleep mode is not compatible with a USB transport layer.
Some examples of the low power modes usage:
7.10.1 SNIFF OR PARK
The STLC2411 is in active mode with a Bluetooth connection, once the connection is concluded the SNIFF
or the PARK is programmed. Once one of these two states is entered the STLC2411 goes in Sleep Mode.
After that, the Host may decide to place the STLC2411 in Deep Sleep Mode by putting the UART LINK in
low power mode. The Deep Sleep Mode allows smaller power consumption. When the STLC2411 needs
to send or receive a packet (e.g. at TSNIFF or at the beacon instant) it will require the clock and it will go in
active mode for the needed transmission/reception. Immediately afterwards it will go back to the Deep
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STLC2411
Sleep Mode. If some HCI transmission is needed, the UART link will be reactivated, using one of the two
ways explained in 7.5, and the STLC2411 will move from the Deep Sleep Mode to the Sleep Mode.
7.10.2 INQUIRY/PAGE SCAN
When only inquiry scan or page scan is enabled, the STLC2411 will go in Sleep Mode or Deep Sleep
Mode outside the receiver activity. The selection between Sleep Mode and Deep Sleep Mode depend on
the UART activity like in SNIFF or PARK.
7.10.3 NO CONNECTION
If the Host places the UART in low power and there is no activity, then the STLC2411 can be placed in
Deep Sleep Mode.
7.10.4 ACTIVE LINK
When there is an active link (SCO or ACL), the STLC2411 cannot go in Deep Sleep Mode whatever the
UART state is. But the STLC2411 baseband is made such that whenever it is possible, depending on the
scheduled activity (number of link, type of link, amount of data exchanged), it goes in Sleep Mode.
7.11 SW initiated low power mode
A wide set of wake up mechanisms are supported.
7.12 Bluetooth - WLAN coexistence in collocated scenario
The coexistence interface uses 4 GPIO pins, when enabled.
Bluetooth and WLAN 802.11 b/g technologies occupy the same 2.4 GHz ISM band. STLC2411 imple-
ments a set of mechanisms to avoid interference in a collocated scenario.
The STLC2411 supports 5 different algorithms in order to provide efficient and flexible simultaneous func-
tionality between the two technologies in collocated scenarios:
– Algorithm 1: PTA (Packet Traffic Arbitration) based coexistence algorithm defined in accordance with
the IEEE 802.15.2 recommended practice.
– Algorithm 2: the WLAN is the master and it indicates to the STLC2411 when not to operate in case of
simultaneous use of the air interface.
– Algorithm 3: the STLC2411 is the master and it indicates to the WLAN chip when not to operate in case
of simultaneous use of the air interface.
– Algorithm 4: Two-wire mechanism
– Algorithm 5: Alternating Wireless Medium Access (AWMA), defined in accordance with the WLAN
802.11 b/g technologies.
The algorithm is selected via HCI command. The default algorithm is algorithm 1.
7.12.1 Algorithm 1: PTA (Packet Traffic Arbitration)
The Algorithm is based on a bus connection between the STLC2411 and the WLAN chip:
STLC2411
WLAN
By using this coexistence interface it's possible to dynamically allocate bandwidth to the two devices when
simultaneous operations are required while the full bandwidth can be allocated to one of them in case the
other one does not require activity. The algorithm involves a priority mechanism, which allows preserving
the quality of certain types of link. A typical application would be to guarantee optimal quality to the Blue-
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STLC2411
tooth voice communication while an intensive WLAN communication is ongoing.
Several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for
the priority handling. Those algorithms can be activated via specific HCI commands.
The combination of a time division multiplexing techniques to share the bandwidth in case of simultaneous
operations and of the priority mechanism avoid the interference due to packet collision and it allows the
maximization of the 2.4 GHz ISM bandwidth usage for both devices while preserving the quality of some
critical types of link.
7.12.2 Algorithm 2: WLAN master
In case the STLC2411 has to cooperate, in a collocated scenario, with a WLAN chip not supporting a PTA
based algorithm, it's possible to put in place a simpler mechanism.
The interface is reduced to 1 line:
RF_NOT_ALLOWED
STLC2411
WLAN
When the WLAN has to operate, it alerts HIGH the RF_NOT_ALLOWED signal and the STLC2411 will
not operate while this signals stays HIGH.
This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but
cannot provide guaranteed quality over the Bluetooth links.
7.12.3 Algorithm 3: Bluetooth master
This algorithm represents the symmetrical case of section 7.12.2. Also in this case the interface is reduced
to 1 line:
RF_NOT_ALLOWED
WLAN
STLC2411
When the STLC2411 has to operate it alerts HIGH the RF_NOT_ALLOWED signal and the WLAN will not
operate while this signals stays HIGH.
This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth, it pro-
vides high quality for all Bluetooth links but cannot provide guaranteed quality over the WLAN links.
7.12.4 Algorithm 4: Two-wire mechanism
Based on algorithm 2 and 3, the Host decides, on a case-by-case basis, whether WLAN or Bluetooth is
master.
7.12.5 Algorithm 5: Alternating Wireless Medium Access (AWMA)
AWMA utilizes a portion of the WLAN beacon interval for Bluetooth operations. From a timing perspective,
the medium assignment alternates between usage following WLAN procedures and usage following Blue-
tooth procedures.
The timing synchronization between the WLAN and the STLC2411 is done by the HW signal
MEDIUM_FREE.
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STLC2411
Table 11. WLAN HW signal assignment
Scenario 2:
WLAN master
Scenario 3: BT
master
Scenario 5:
AWMA
WLAN
Scenario 1: PTA
Scenario 4: 2-wire
WLAN 1
TX_ CONFIRM
BT_RF_NOT_
ALLOWED
Not used
BT_RF_NOT_
ALLOWED
MEDIUM_FREE
WLAN 2
TX_ REQUEST
Not used
WLAN_RF_ NOT_ WLAN_RF_ NOT_
Not used
ALLOWED
Not used
Not used
ALLOWED
Not used
Not used
WLAN 3
STATUS
Not used
Not used
Not used
Not used
WLAN 4 OPTIONAL_ SIGNAL
8 INTERFACES
8.1 UART Interface
The chip contains two enhanced (128 byte transmit FIFO and 128 byte receive FIFO, sleep mode, 127 Rx
and 128 Tx interrupt thresholds) UARTs named UART1 and UART2 compatible with the standard M16550
UART.
For UART1, only Rx and Tx signals are available (used for debug purposes).
UART2 features:
– standard HCI UART transport layer:
– all HCI commands as described in the Bluetooth™ specification 1.1
– ST specific HCI command (check STLC2411 Software Interface document for more information)
– RXD, TXD, CTS, RTS on permanent external pins
– 128-byte FIFOs, for transmit and for receive
– Default configuration: 57.600 kbps
– Specific HCI command to change to the following baud rates:
Table 12. List of supported baud rates
Baud rate
–
57.600 kbps (default)
4800
2400
1800
1200
900
921.6k
460.8 k
230.4 k
153.6 k
115.2 k
76.8 k
38.4 k
28.8 k
19.2 k
14.4 k
9600
600
300
7200
8.2 Synchronous Serial Interface
The Synchronous Serial Interface (SSI) (or the Synchronous Peripheral Interface (SPI)) is a flexible mod-
ule supporting full-duplex and half-duplex synchronous communications with external devices in Master
and Slave mode. It enables a microcontroller unit to communicate with peripheral devices or allows inter-
processor communications in a multiple-master environment. This Interface is compatible with the Motor-
ola SPI standard, with the Texas Instruments Synchronous Serial frame format and with National Semi-
conductor Microwire standard.
Special extensions are implemented to support the Agilent SPI interface for optical mouse applications
and the 32 bit data SPI for stereo codec applications.
8.2.1 Feature description: Agilent mode
One application is a combination of a Bluetooth device with an AGILENT optical mouse sensor to build a
Bluetooth Mouse. The AGILENT chip has an SPI interface with one bi-directional data port.
When spi_io from ADNS_2030 is driving, spi_rxd should be active, while spi_txd is set as a tri-state high
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STLC2411
impedance input.
For a read operation, the Bluetooth spi_txd is put in high impedance state after the reception of the ad-
dress.
Note that this feature works independently of the SPI mode, supporting other combinations.
In this case, the devices are connected as described in the figure below.
Figure 6.
Agilent ADNS-2030
STLC2411
spi_clk
spi_clk
spi_frm
spi_txd
spi_io
spi_rxd
8.2.2 Feature description: 32 bit SPI
One application is a Bluetooth stereo headset. In this application, the audio samples are received from the
emitter through the air using the Bluetooth baseband with ACL packets. The samples are decoded by the
embedded ARM CPU (the samples were encoded, for compression, in SBC or MP3 format) and then sent
to a stereo codec though the SPI interface. The application is described in the figure below.
Figure 7.
spi_txd
STw5094A CODEC
STLC2411
Bluetooth
reception
spi_rxd
SPI master mode 32 bits
SPI slave mode 32 bits
stereo headset
spi_frm
spi_clk
32 spi_clk
16 spi_clk
To support this application, the data size is 32 bits. The 32 bits support is implemented for both transmit
and receive.
8.3 I2C Interface
Used to access I2C peripherals.
The interface is a fast master I2C; it has full control of the interface at all times. I2C slave functionality is
not supported.
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STLC2411
8.4 USB Interface
The USB interface is compliant with the USB 2.0 full speed specification. Max throughput on the USB in-
terface is 12 Mbit/s.
Figure 8 gives an overview of the main components needed for supporting the USB interface, as specified
in the Bluetooth™ Core Specification. For clarity, the serial interface (including the UART Transport Layer)
is also shown.
Figure 8. USB Interface
HCI
USB TRANSPORT LAYER
UART TRANSPORT LAYER
SERIAL DRIVER
RTOS
USB
DEVICE
REGISTERS
FIFOs
UART
DEVICE
REGISTERS
FIFOs
USB DRIVER
IRQ
IRQ
STLC2411 HW
0D4TL263
The USB device registers and FIFOs are memory mapped. The USB Driver will use these registers to ac-
cess the USB interface. The equivalent exists for the HCI communication over UART.
For transmission to the host, the USB & Serial Drivers interface with the HW via a set of registers and
FIFOs, while in the other direction, the hardware may trigger the Drivers through a set of interrupts (iden-
tified by the RTOS, and directed to the appropriate Driver routines).
8.5 JTAG Interface
The JTAG interface is compliant with the JTAG IEEE Std 1149.1. Its allows both the boundary scan of the
digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 devel-
opment tools.
8.6 RF Interface
The STLC2411 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirection-
al serial interface for control).
8.7 PCM voice interface
The voice interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or
STw5094) including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), µ-
Law (8bit) or A-Law (8bit). By default the codec interface is configured as master. The encoding on the air
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STLC2411
interface is programmable to be CVSD, A-Law or µ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
PCM clock and data are in master mode available at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
– PCM_CLK :
PCM clock
– PCM_SYNC : PCM 8kHz sync
– PCM_A :
– PCM_B :
PCM data
PCM data
Directions of PCM_A and PCM_B are software configurable.
Three additional PCM_SYNC signals can be provided via the GPIOs. See section 12 for more details.
Figure 9. PCM (A-law, µ-law) standard mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCM_CLK
PCM_SYNC
PCM_A
B
B
B
PCM_B
B
D02TL558
125µs
Figure 10. Linear mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
D02TL559
125µs
Table 13. PCM interface timing.
Symbol
Description
Min
Typ
Max
Unit
PCM Interface
Fpcm_clk
Frequency of PCM_CLK (master)
2048
8
kHz
kHz
ns
F
Frequency of PCM_SYNC
High period of PCM_CLK
Low period of PCM_CLK
High period of PCM_SYNC
pcm_sync
t
200
200
200
100
100
100
WCH
t
ns
WCL
t
ns
WSH
t
Setup time, PCM_SYNC high to PCM_CLK low
ns
SSC
SDC
HCD
DCD
t
Setup time, PCM_A/B input valid to PCM_CLK low
Hold time, PCM_CLK low to PCM_A/B input invalid
Delay time, PCM_CLK high to PCM_A/B output valid
ns
t
t
ns
150
ns
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STLC2411
Figure 11. PCM interface timing
t
WCL
PCM_CLK
t
WCH
t
SSC
PCM_SYNC
t
SDC
t
WSH
t
HCD
MSB
MSB-1 MSB-2 MSB-3 MSB-4
PCM_A/B in
t
DCD
MSB
MSB-1 MSB-2 MSB-3 MSB-4
D02TL557
PCM_B/A out
9 HCI UART TRANSPORT LAYER
The UART Transport Layer is specified by the Bluetooth™ SIG, and allows HCI level communication be-
tween a host controller (STLC2411) and a host (e.g. PC), via a serial line.
The objective of this HCI UART Transport Layer is to make it possible to use the Bluetooth™ HCI over a
serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the
UART communication is free from line errors.
9.1 UART Settings
The HCI UART Transport Layer uses the following settings for RS232:
– Baud rate:
Configurable (Default baud rate: 57.600 kbps)
– Number of data bits:
– Parity bit:
– Stop bit:
8
no parity
1 stop bit
RTS/CTS
– Flow control:
– Flow-off response time: 3 ms
Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for
flow control of HCI, since HCI has its own flow control mechanisms for HCI commands, HCI events and
HCI data.
If CTS is 1, then the Host/Host Controller is allowed to send.
If CTS is 0, then the Host/Host Controller is not allowed to send.
The flow-off response time defines the maximum time from setting RTS low until the byte flow actually
stops. The signals should be connected in a null-modem fashion; i.e. the local TXD should be connected
to the remote RXD and the local RTS should be connected to the remote CTS and vice versa.
Figure 12. UART Transport Layer
BLUETHOOTH
HOST
CONTROLLER
BLUETHOOTH HCI
BLUETHOOTH
HOST
HCI UART TRANSPORT LAYER
D02TL556
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STLC2411
10 HCI USB TRANSPORT LAYER
The USB Transport Layer has been specified by the Bluetooth™ SIG, and allows HCI level communication
between a host controller (STLC2411) and a host (e.g. PC), via a USB interface. The USB Transport Layer
is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmis-
sion over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB data
received from the USB Driver, and sends these messages to the HCI Layer. The Transport Layer does
not interprete the contents (payload) of the HCI messages; it only examines the header.
11 CLASS1 POWER SUPPORT
The chip can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this
purpose in order to avoid digital/analogue noise loops in the radio.
A software controlled register enables the alternate functions of GPIO[15:6] to generate the signals for
driving an external PA in a Bluetooth™ class1 power application.
Every bit enables a dedicated signal on a GPIO pin, as described in Table 14.
12 GPIOS
Table 14. GPIOs alternate functionalities
Involved GPIO
gpio0
Description of alternate dedicated functionality
No dedicated function
gpio1
WLAN 1
gpio2
WLAN 2
gpio3
WLAN 3
gpio4
WLAN 4
gpio5
gpio6
gpio7
gpio8
gpio9
gpio10]
gpio11
gpio12
gpio13
gpio14
gpio15
(Used for USB reset pull.)
Power Class 1 brxen
Power Class 1 not_brxen
Power Class 1 PA0 or PCM sync 1
Power Class 1 PA1 or PCM sync 2
Power Class 1 PA2 or PCM sync 3
Power Class 1 PA3
Power Class 1 PA4
Power Class 1 PA5
Power Class 1 PA6
Power Class 1 PA7
The signal brxen is the same as the brxen radio output pin. The signal not_brxen is the inverted signal, in
order to save components on the application board.
PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the base-
band core. The Power Level programmed for a certain Bluetooth™ connection is managed by the firm-
ware, as specified in the Bluetooth™ SIG spec.
The WLAN signals, as described in section 7.12, can be enabled on GPIO pins.
The extra PCM sync signals, as described in section 8.7, can be flexibly configured on GPIO pins to con-
nect multiple codecs.
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STLC2411
Figure 13. TFBGA132 Mechanical Data & Package Dimensions
mm
inch
OUTLINE AND
DIM.
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.047
A
A1
A2
b
1.010
0.150
1.200 0.040
0.006
0.820
0.032
0.250 0.300 0.350 0.010 0.012 0.014
7.850 8.000 8.150 0.310 0.315 0.321
D
D1
E
6.500
7.850 8.000 8.150 0.310 0.315 0.321
6.500 0.256
0.256
E1
e
Body: 8 x 8 x 1.20mm
0.450 0.500 0.550 0.018 0.020 0.022
0.600 0.750 0.900 0.024 0.029 0.035
f
TFBGA132
Fine Pitch Ball Grid Array
ddd
0.080
0.003
7146828 A
23/25
STLC2411
Table 15. Revision History
Date
Revision
Description of Changes
June 2004
1
First Issue
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STLC2411
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
The BLUETOOTH™ word mark and logos are owned by the Bluetooth SIG, Inc. and any use of such marks by STMicroelectronics is under license.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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