CXD1961AQ [SONY]
DVB-S Frontend IC (QPSK demodulation + FEC); DVB -S前端IC （ QPSK解调+ FEC ）
| 型号： | CXD1961AQ |
| 厂家： | 
SONY CORPORATION |
| 描述： | DVB-S Frontend IC (QPSK demodulation + FEC) |
| 文件： | 总33页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD1961AQ
Preliminary
DVB-S Frontend IC (QPSK demodulation + FEC)
For the availability of this product, please contact the sales office.
Description
100 pin QFP (Plastic)
The CXD1961AQ is a single chip DVB compliant
Satellite Broadcasting Frontend IC, including dual
A/D converter for analog baseband I/Q input, QPSK
demodulator, Viterbi decoder Reed-Solomon decoder
and Energy Dispersal descrambler. It is suitable for
use in a DVB Integrated Receiver Decoder.
Features
• Dual 6 bit A/D converter
Absolute Maximum Rating (Ta = 25°C, GND = 0V)
• QPSK demodulator
• Power Supply
• Input Voltage
• Output Voltage
• I/O Voltage
VDD
–0.5 to +4.6
V
V
Multi-symbol rate operation
Nyquist Roll off filter (α = 0.35)
Clock recovery circuit
VIN
–0.5 to VDD + 0.5
VOUT –0.5 to VDD + 0.5
–0.5 to VDD + 0.5
Vcpuif –0.5 to +5.5
–55 to +150
V
VI/O
V
Carrier recovery circuit
• CPU I/F pin
V
AGC control (PWM output)
• Storage Temperature Tstg
°C
• Viterbi decoder
Constraint length 7
Recommended Operating Condition
(Ta = 0 to 75°C, GND = 0V)
VDD 3.15 to 3.45
VIH 0.7 × VDD to VDD + 0.5V
0.3 to 0.2 × VDD
Truncation length 144
BER monitor of QPSK demodulator output
• Frame synchronization circuit
• Convolutional de-interleaver
• Reed-Solomon decoder (204,188)
BER monitor of Viterbi decoder output
• Energy dispersal descrambler
• CPU interface circuit
• Power Supply
• Input High level
• Input Low level
V
VIL
V
I2C bus interface (5V input capability)
• Package
QFP 100pin
• Operating frequency
• Power consumption
• Process
20 to 30MSPS
750mW (@3.3V 30MSPS typical)
0.4µm CMOS Technology
Application
DVB-S Set Top Box (Satellite)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
PE97854-PS
CXD1961AQ
Block Diagram
100
99 98
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
97
AVS0
RB0
1
2
3
4
5
6
7
8
9
80 VDD9
79 CR7
78 CR6
77 CR5
analog I/O
2ch ADC
Sampling
Clock
PLL
VCO
VDD0
VSS0
TEST1
TEST2
TEST3
TEST4
NC
76
CR4
QPSK
Demodulator
75 VSS8
74 VDD8
73 CR3
72 CR2
VDD1 10
VSS1 11
71
CR1
70 CR0
NCO
Viterbi Decoder
SDAT/SCL 12
13
69 CKV
68 AGCPWM
SCLK
SEN/SDA 14
VDD2 15
67
66
65
64
63
62
61
V
SS7
VDD7
VCK
VDT
XI
VSS2 16
De-interleaver
TCK 17
18
19
TMS
XO
TEST6
AVS3
TEST7 20
CK8OUT
21
60 AVD3
SDA
RESET 22
TE 23
59
58
57
Reed-Solomon
Decoder
CPU I/F
SCL
I2C bus
TEST22
VDD3 24
VSS3 25
56 TEST21
55 TEST20
PKTCLK 26
BYTCLK 27
PKTERR 28
DATA0 29
DATA1 30
Energy Dispersal
54
53
52
51
VSS6
VDD6
decoded data
& clock
TEST19
TEST18
31
32 33
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
34
Typical Block Diagram
QPSK + FEC
I/Q
detector
Amp
Data
LNB
SAW
LPF
LPF
SONY
CXD1961AQ
Clock
VCO
PLL
479.5MHz
90°
LPF
Crystal
Reference
OSC
Micro Controller
– 2 –
CXD1961AQ
Functional Description
(1) A/D Converters
The CXD1961AQ has dual 6 bit A/D converters to quantize the analog baseband I/Q signal. The sampling rate
is two times the symbol rate. The input range is determined by the external resisters. See reference circuit (1).
The DC offset cancellation function is set by setting CPU I/F register 1E,1F(hex).
(2) Clock Recovery Circuit
The CXD1961AQ can operate at multiple symbol rates between 20 to 30MSPS. Initial sampling clock
frequency is set by a 24 bit control word via CPU I/F register 18, 19, 1A (hex). This control word is written to
the numerically controlled oscillator (NCO). The internal clock recovery loop feeds clock error data to the
above NCO to provide sampling timing correction. The relation between the symbol rate and the control word
is;
(symbol rate) = 4 × NCO [23:0] × Fcrystal ÷ 224 (Hz)
where NCO [23:0] is the 24 bit control word and Fcrystal is crystal frequency (Hz).
The clock recovery loop coefficient and the loop gain are set by setting CPU I/Fregister 0C (hex) accordingly.
See reference circuit (2). The recovered symbol clock can be monitored at Pin 69.
There are three internal sub-registers to save the NCO control word. By setting the number of the preset sub-
register, the control word corresponded to the certain symbol rate is set to the internal NCO. Contents of the
sub-register are deleted by power off or reset by pin 22. Refer to the explanation of CPU I/F register 0D (hex).
(3) Carrier Recovery Circuit
Any carrier frequency offset which remains on the analog baseband I/Q input is compensated by the internal
digital costas loop. The capture range is ±Rs/8 (Rs: symbol rate). When the carrier capture is performed,
QPSK lock flag QSYNC goes high. QSYNC is output at Pin 82 and CPU I/F register 09 (hex). In QPSK
synchronization, the carrier offset estimation value is output at CPU I/F register 02 (hex) as AFC [7:0]. The
frequency offset is;
(carrier offset) = Rs × AFC [7:0] ÷ 512 (Hz)
where AFC7 is the sign bit that represents the direction of the offset.
(4) Nyquist Roll off Filter
The Nyquist roll off filter for each channel are embedded. The roll off factor is 0.35.
– 3 –
CXD1961AQ
(5) Auto Gain Control
By comparing the demodulated I/Q amplitude (I2 + Q2) and the reference level which is set via CPU I/F register
21 (hex), the AGC control signal is generated as PWM output at Pin 68. The polarity of the AGC can be
reversed by setting CPU I/F register 10 (hex). For the Tuner interface, see the reference circuit (4).
(6) Viterbi Decoder
The punctured decoding and Viterbi decoding are performed on the demodulated I and Q data. The punctured
rate is programmable from 1/2 to 7/8. When punctured mapping is performed, Viterbi lock flag at CPU I/F
register 09 (hex) goes one. Bit error count at QPSK demodulator output is estimated and output to CPU I/F
register 03, 04 (hex) as 16 bit data.
(7) Frame synchronization and Deinterleaver
By detecting the MPEG2 sync word 47 (hex), the synchronization of the data packet is achieved, and the
convolutional deinterleaver then recovers the original data order.
(8) Reed-Solomon Decoder
In DVB systems, 16 parity bytes are added to the 188 data bytes, so that up to 8 error bytes are correctable by
the Reed-Solomon decoder. If there are more than 8 error bytes in a packet, error correction is not performed
and the packet error flag PKTERR (Pin 28) goes high during the packet to indicate that the packet is not
correctable. The MSB of the second byte of the uncorrectable packet also becomes one. Bit error count at
Viterbi decoder output is estimated and output every 1280 packet (=204 × 8 × 1280 bit) to CPU I/F register 06,
07 (hex) at a resolution of 16 bits.
(9) Energy Dispersal Descrambler
Energy dispersal descrambling is represented by the polynomial X15 + X14 + 1. The initial sequence is loaded
when an inverted MPEG sync word B8 (hex) is detected. When MPEG sync word including inverted one is
detected every 204 bytes, the lock flag of the whole IC "FSYNC" goes high. FSYNC is output at Pin 83 and
CPU I/F register 09 (hex).
– 4 –
CXD1961AQ
(10) CPU Interface
The CXD1961AQ has an I2C bus interface. Serial clock SCL is Pin 58 and serial data in out SDA is Pin 59.
Slave address is "1101 111" (DChex).
<Write data>
During the write operation, the second byte is input as the sub-address of the start position. The third byte then
forms the data to be written to the start register. Successive data bytes are written to the successive sub-
address registers up to 21 (hex). Note that registers of sub-addresses 00 (hex) to 0B (hex) are read only.
Input data for
sub-address
N (hex)
Input data for
sub-address
N + 1 (hex)
Slave address
1101 111
Sub address
N (hex)
0
· · ·
STA: start condition
STP: stop condition
ACK: acknowledge
XACK: no acknowledge
<Read operation>
Before the read operation, the sub-address of the start register to be read is input by using write operation, and
terminated with a stop condition. Read operation then begins with the second byte which is the data of the start
register. Data of the successive sub-address registers are read successively following the second byte. All
registers can be read.
Slave address
1101 111
Sub address
N (hex)
0
Output data for
sub-address
N (hex)
Output data for
sub-address
N + 1 (hex)
Slave address
1101 111
1
· · ·
Both SCL and SDA have 5V input capability.
– 5 –
CXD1961AQ
Pin Configuration
100
99 98
96 95 94 93 92
91 90 89 88 87 86 85 84 83 82 81
97
AVS0
RB0
1
2
3
4
5
6
7
8
9
80 VDD9
CR7
79
78 CR6
VDD0
VSS0
CR5
CR4
77
76
TEST1
TEST2
TEST3
TEST4
NC
75 VSS8
VDD8
74
73 CR3
72 CR2
CR1
CR0
CKV
VDD1 10
VSS1 11
71
70
69
SDAT/SCL 12
13
14
15
68 AGCPWM
67 VSS7
SCLK
SEN/SDA
VDD2
66 VDD7
65
64
63
62
61
VCK
VDT
XI
VSS2 16
TCK 17
TMS
TEST6
18
19
20
21
22
XO
AVS3
TEST7
CK8OUT
RESET
60 AVD3
SDA
59
SCL
TE 23
58
57
56
TEST22
TEST21
VDD3
24
25
VSS3
PKTCLK 26
BYTCLK 27
55 TEST20
VSS6
54
PKTERR
DATA0
28
29
53 VDD6
TEST19
52
51
TEST18
DATA1 30
31
32 33
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
34
– 6 –
CXD1961AQ
Pin List
No.
Symbol
AVS0
I/O type
1
2
Analog VSS
RB0
Ref. voltage input
Digital VDD
3
VDD0
4
VSS0
Digital VSS
5 to 8
9
TEST1 to 4
NC
CMOS input
No Connection
Digital VDD
10
VDD1
11
VSS1
Digital VSS
12
SDAT/SCL
SCLK
3-state CMOS output
3-state CMOS output
In out with Pull up
Digital VDD
13
14
SEN/SDA
VDD2
15
16
VSS2
Digital VSS
17
TCK
Input with pull up
Input with pull up
CMOS input
18
TMS
19
TEST6
TEST7
CK8OUT
RESET
TE
20
Input with pull up
CMOS output
Input with pull up
Input with pull down
Digital VDD
21
22
23
24
VDD3
25
VSS3
Digital VSS
26
PKTCLK
BYTCLK
PKTERR
DATA0 to 4
VDD4
3-state CMOS output
3-state CMOS output
3-state CMOS output
3-state CMOS output
Digital VDD
27
28
29 to 33
34
35
VSS4
Digital VSS
36 to 38
39 to 43
44
DATA5 to 7
TEST8 to 12
VDD5
3-state CMOS output
CMOS in out
Digital VDD
45
VSS5
Digital VSS
46 to 48
49 to 52
TEST13 to 15
TEST16 to 19
CMOS in out
CMOS input
– 7 –
CXD1961AQ
No.
53
Symbol
I/O type
VDD6
Digital VDD
54
VSS6
Digital VSS
55 to 57
58
TEST20 to 22
SCL
CMOS input
5V input
59
SDA
5V open drain in out
Crystal VDD
60
AVD3
AVS3
XO
61
Crystal VSS
62
Oscillator output
Oscillator input
CMOS in out
CMOS in out
Digital VDD
63
XI
64
VDT
65
VCK
66
VDD7
67
VSS7
Digital VSS
68
AGCPWM
CKV
CMOS output
CMOS in out
CMOS output
Digital VDD
69
70 to 73
74
CR0 to 3
VDD8
75
VSS8
Digital VSS
76 to 79
80
CR4 to 7
VDD9
CMOS output
Digital VDD
81
VSS9
Digital VSS
82
QSYNC
FSYNC
AVD4
AVS4
CPOUT
AVD2
VCOC
OPXIN
OPOUT
AVS2
VCOEN
RT1
CMOS output
CMOS output
Analog VDD
83
84
85
Analog VSS
86
3-state CMOS output
Analog VDD
87
88
Analog input
Analog input
Analog output
Analog VSS
89
90
91
92
CMOS input
Ref. voltage input
Analog VDD
93
94
AVD1
– 8 –
CXD1961AQ
No.
95
Symbol
QIN
I/O type
Analog input
96
AVS1
RB1
RT0
AVD0
IIN
Analog VSS
97
Ref. voltage input
Ref. voltage input
Analog VDD
98
99
100
Analog input
Note) Apply 0.1µF capacitor to every power supply terminal and reference voltage input (RB0, RB1, RT0, RT1).
– 9 –
CXD1961AQ
Pin Explanation
1. A/D Converter
ADC for I input
ADC for Q input
Function
Pin No. Pin name Pin No. Pin name
Analog signal input
100
98
2
IIN
95
93
97
94
96
QIN
RT1
Top reference level input
RT0
Bottom reference level input
Analog power supply (+3.3V)
Analog ground
RB0
RB1
99
1
AVD0
AVS0
AVD1
AVS1
See reference circuit (1)
2. Clock Recovery
2-1. Crystal
Function
Pin No. Pin name
Crystal oscillator (output)
62
63
60
61
XO
XI
Crystal oscillator (input)
Crystal oscillator power supply (+3.3V)
Crystal oscillator ground
AVD3
AVS3
See reference circuit (3)
2-2. VCO · OP-Amp
Function
Charge Pump output
Pin No. Pin name
86
84
85
88
92
89
90
87
91
CPOUT
AVD4
Charge pump power supply (+3.3V)
Charge pump ground
AVS4
VCO control voltage input
VCO enable (H: enable)
OP-Amp negative input
VCOC
VCOEN
OPXIN
OPOUT
AVD2
OP-Amp output
VCO · OP-Amp power supply (+3.3V)
VCO · OP-Amp ground
AVS2
See reference circuit (2)
– 10 –
CXD1961AQ
2-3. Clock Recovery
Function
Pin No. Pin name
Clock error output
(for clock recovery by VCXO)
70 to 73 CR0 to 3
76 to 79 CR4 to 7
Recovered symbol clock output
(switchable to sampling clock output)
69
CKV
3. Carrier Recovery
Function
Pin No. Pin name
82 QSYNC
Carrier lock flag (H: lock)
4. AGC
Function
AGC control data (PWM output)
See reference circuit (4)
Pin No. Pin name
68 AGCPWM
5. Viterbi Decoder
Function
Viterbi clock output
Pin No. Pin name
65
64
VCK
VDT
Viterbi decoded data output
These pins can be fixed to ground by setting CPU I/F register 0E (hex).
6. Frame Synchronization
Function
Pin No. Pin name
83 FSYNC
Frame synchronization flag (H: sync)
– 11 –
CXD1961AQ
7. Reed-Solomon Decoder/Data output
Function
Pin No. Pin name
Data output clock
(parallel mode) Byte clock
(Serial mode) Viterbi clock
27
BYTCLK
Packet clock (H: data, L: parity)
Uncorrectable packet flag
26
28
PKTCLK
PKTERR
Data output
(Parallel mode) LSB data
(Serial mode) serial data (MSB first)
29
DATA0
Data output
(Parallel mode) DATA7 = MSB
(Serial mode) Hi-Z
30 to 33 DATA1 to 4
36 to 38 DATA5 to 7
Output mode (Serial or Parallel) is switched by setting CPU I/F register 0F (hex).
8. CPU Interface
Function
Pin No. Pin name
I2C bus serial clock input
I2C bus serial data in out
58
59
SCL
SDA
9. Reset
Function
Pin No. Pin name
22 RESET
Reset (L: reset/fix H for normal use)
10. Power Supply
Function
Pin No. Pin name
10, 15, 24,
Digital power supply (+3.3V)
34, 44, 53, VDD0 to 9
66, 74, 80
11, 16, 25,
Digital ground
35, 45, 54, VSS0 to 9
67, 75, 81
Apply 0.1µF capacitor to every power supply terminal.
– 12 –
CXD1961AQ
11. Test / Others
Function
Pin No.
23
Pin name
TE
Test mode enable (Fix L for normal use)
Test clock (Fix H for normal use)
17
TCK
Test mode Control (Fix H for normal use)
18
TMS
5 to 8, 20 TEST1 to 4, TEST7
Test input (Fix L)
49 to 52
55 to 57
TEST16 to 19
TEST20 to 22
Test output (connect nothing)
Test in out (Fix L)
19
TEST6
39 to 43
46 to 48
TEST8 to 12
TEST13 to 15
Tuner interface
(3 wire mode) Serial data output
12
13
14
SDAT/SCL
SCLK
(I2C bus mode) Serial clock output
Tuner interface (3 wire) Clock output
Tuner interface
(3 wire mode) Latch enable output
(I2C bus mode) Serial data in out
SEN/SDA
Clock output (crystal frequency/8)
No Connection
21
9
CK8OUT
NC
– 13 –
CXD1961AQ
Electrical Characteristics
Description
(Ta = 0 to 75°C, VDD = 3.3V)
Symbol
Rs
Min.
20
Typ.
Max.
30
Unit
MSPS
MHz
Symbol rate
Crystal Frequency
Fxtal
32
DATA0 to 7 – BYTCLK falling edge
(Parallel output mode PBYCK = 0)
tDB0
tPB0
tEB0
tDB1
tPB1
tEB1
tSOC
tDBH
tPBS
tEBH
75
75
75
75
75
75
16
12
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PKTCLK – BYTCLK falling edge
(Parallel output mode PBYCK = 0)
PKTERR – BYTCLK falling edge
(Parallel output mode PBYCK = 0)
DATA0 to 7 – BYTCLK rising edge
(Parallel output mode PBYCK = 1)
PKTCLK – BYTCLK rising edge
(Parallel output mode PBYCK = 1)
PKTERR – BYTCLK rising edge
(Parallel output mode PBYCK = 1)
Serial output mode cycle time
(Serial output mode)
DATA0 to 7 – BYTCLK hold time
(Serial output mode)
PKTCLK, PKTERR – BYTCLK setup time
(Serial output mode)
PKTCLK, PKTERR – BYTCLK hold time
(Serial output mode)
10
I2C bus Serial clock cycle time
I2C bus Data setup time
I2C bus Data hold time
FscI
tDSI
tDHI
400
kHz
ns
100
0
ns
Timing Waveform
(1) Parallel output mode, PBYTCK = 0
tPB0
tEB0
tPB0
tEB0
PKTCLK
PKTERR
BYTCLK
DATA [0:7]
tDB0 tDB0
– 14 –
CXD1961AQ
(2) Parallel output mode, PBYTCK = 1
tPB1
tEB1
tPB1
tEB1
PKTCLK
PKTERR
BYTCLK
DATA [0:7]
tDB1 tDB1
(3) Serial output mode (Example of R = 3/4)
tPBS
tEBH
tEBH
PKTCLK
tSOC
PKTERR
BYTCLK
DATA0
tDBH
(4) I2C Bus interface
0.6µs
tDSI
SDA
SCL
1.3µs
1.3µs
tDHI
0.6µs
0.6µs
– 15 –
CXD1961AQ
CPU Interface Registers
Sub address
MSB
bit7
LSB
bit0
Name
INP_LEV
(hex)
00
01
02
03
04
05
06
07
08
09A
09B
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
bit6
bit5
bit4
bit3
bit2
bit1
INP7
INP6
INP5
INP4
INP3
INP2
INP1
INP0
PWM_VAL PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
AFC_VAL AFC7 AFC6 AFC5 AFC4 AFC3 AFC2 AFC1 AFC0
QBEC_LO QBEC7 QBEC6 QBEC5 QBEC4 QBEC3 QBEC2 QBEC1 QBEC0
QBEC15 QBEC14 QBEC13 QBEC12 QBEC11 QBEC10 QBEC9 QBEC8
QBEC_UP VBEC7 VBEC6 VBEC5 VBEC4 VBEC3 VBEC2 VBEC1 VBEC0
W
R
VBEC_LO
W
VBEC15 VBEC14 VBEC13 VBEC12 VBEC11 VBEC10 VBEC9 VBEC8
—
RO2
OFI2
NAK
RO1
OFI1
—
RO0
OFI0
QBER1 QBER0 VBER1 VBER0
OFI3
OFQ3
OFQ2
OFQ1
—
OFQ0
ID
VBEC_UPR VCOLK
CM7
DC_OFST CM15
FLAG OFC7
CM_LOW MQS3
CM_UPR
FSYNC VSYNC QSYNC
CODE/BER
CM6
CM5
CM13
OFC5
MQS1
CM4
CM12
OFC4
MQS0
CM3
CM11
OFC3
AK1
CM2
CM10
OFC2
AK0
CM1
CM9
OFC1
CE1
CM0
CM8
OFC0
CE0
CM14
OFC6
MQS2
—
RATE2 RATE1 RATE0 SRSAVE
—
SRS1
SRS0
CAR_OFST PBYCK DOH1Z DOPS PPKER PPKCK MBYCK VCKVDT SEL09
MQS/CLK SINV SYSSEL DFSKIP RSSKIP TUNSEL TUNEN MFSYNC AGCLP
CODE/SRS MAGC
OUT_CNT QTH5
MOD_CNT VTH4
PAGC MVSYNC CKVSEL QPRST VTRST RSRST VCORST
QTH4
VTH3
QTH3
VTH2
QTH2
VTH1
QTH1
VTH0
QTH0 TQBEC1 TQBEC0
TVS2 TVS1 TVS0
AGC/RST TUD17 TUD16 TUD15 TUD14 TUD13 TUD12 TUD11 TUD10
QTH
VTH
TUD27 TUD26 TUD25 TUD24 TUD23 TUD22 TUD21 TUD20
TUD37 TUD36 TUD35 TUD34 TUD33 TUD32 TUD31 TUD30
TUN_DAT1 TUD47 TUD46 TUD45 TUD44 TUD43 TUD42 TUD41 TUD40
TUN_DAT2 TUD57 TUD56 TUD55 TUD54 TUD53 TUD52 TUD51 TUD50
TUN_DAT3 NCO7
NCO6
NCO5
NCO4
NCO3
NCO2
NCO1
NCO0
NCO8
TUN_DAT4 NCO15 NCO14 NCO13 NCO12 NCO11 NCO10 NCO9
TUN_DAT5 NCO23 NCO22 NCO21 NCO20 NCO19 NCO18 NCO17 NCO16
SYM_RATE1 CALRST CADRST CLKRST
—
—
RANGE FSYSEL FSYTHD
—
—
SYM_RATE2
—
—
—
—
—
—
SYM_RATE3 BSI3
BSI2
BSI1
BSI0
BSQ3
BSQ2
BSQ1
BSQ0
CAR_RST RSTEN GAIN1 GAIN0 TCAR1 TCAR0 MOFST OFSTEN OFSTGN
N.A.
TQS1
BSC7
REF7
TQS0 FLOOP TRACK FLMOD FLSTEP QTLEV1 QTLEV0
DC_BIAS
CAR/DC
BSC6
REF6
BSC5
REF5
BSC4
REF4
BSC3
REF3
BSC2
REF2
BSC1
REF1
BSC0
REF0
Input "0" to write registers which are not assigned ("—").
– 16 –
CXD1961AQ
Description of CPU Interface Registers
Sub address 00 (hex)
Read
INP_LEV
Input level estimation
INP7 to INP0
(MSB) (LSB)
Upper 8 bit of I2 + Q2 of analog I/Q input.
(Ex.) The value is about 40 (hex) when the analog I/Q amplitude is half the input
range.
Sub address 01 (hex)
PWM7 to PWM0
Read
PWM_VAL
AGC PWM output value
PWM output value of AGC control.
(MSB)
(LSB)
Sub address 02 (hex)
Read
AFC_VAL
Carrier offset value
AFC7 to AFC0
(MSB) (LSB)
AFC7: Sign
Carrier offset estimation
Carrier offset = (Symbol rate) × AFC [7:0] ÷ 512 (Hz)
Ex.) 20MSPS AFC [7:0] = 11110000 (bin)
offset = 20MHz × (–16) ÷ 512
= –625kHz
In this case, by changing tuner PLL value by -625kHz, the offset may be
cancelled.
Sub address 03 (hex)
Sub address 04 (hex)
Read
Read
QBEC_LOW Bit error count at QPSK output
QBEC_UPR Bit error count at QPSK output
QBEC15 to QBEC0
Bit error count at the QPSK output (16 bit).
(MSB)
(LSB)
Measuring period is set by TQBEC [1:0] of CPU I/F register 11 (hex) .
BER is the ratio of QBEC [15:0] and the measuring period.
QBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High.
Sub address 05 (hex)
Sub address 06 (hex)
Read
Read
VBEC_LOW Bit error count at Viterbi output
VBEC_UPR Bit error count at Viterbi output
VBEC15 to VBEC0
Bit error count at the Viterbi output (16 bit).
(MSB)
(LSB)
Measuring period is 204 × 8 × 1280 = 2,088,960.
BER is the ratio of VBEC [15:0] and 2,088,960.
VBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High.
– 17 –
CXD1961AQ
Sub address 07 (hex)
RO2 to RO0
Read
CODE/BER
Code rate and BER
Current punctured rate (code rate)
RO2
RO1
RO0
Code rate
1/2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
2/3
3/4
4/5
5/6
6/7
7/8
QBER1 to QBER0
4 level BER indicator of QPSK output.
This indicator is valid when QSYNC, VSYNC and FSYNC are all High and
TQBEC [1:0] = 10 (bin). TQBEC [1:0] is in register 11 (hex).
QBER1 QBER0
Bit Error Rate
0
0
1
1
0
1
0
1
more than 10–2
10–3
10–4
<
<
<10–2
<10–3
less than 10–4
VBER1 to VBER0
4 level BER indicator of Viterbi output.
This indicator is valid when QSYNC, VSYNC and FSYNC are all High.
VBER1 VBER0
Bit Error Rate
0
0
1
1
0
1
0
1
more than 10–2
10–3
10–4
<
<
<10–2
<10–3
less than 10–4
– 18 –
CXD1961AQ
Sub address 08 (hex)
OFI3 to OFI0
Read
DC_OFST
DC offset level of A to D converter
DC offset value of the I channel A/D converter.
OFI3: Sign
OFQ3 to OFQ0
DC offset value of the Q channel A/D converter.
In both cases, the value is depend on the operation mode.
OFQ3: Sign
MOFST (reg. IE)
0
Operating mode
Offset bias mode
OFI [3:0] / OFQ [3:0]
Current offset value.
Compensation value for each
A/D converter.
1
Offset cancel mode
Refer to the explanation of register 1E (hex).
Sub address 09 (hex)-A
Read
FLAG
Status Flag
Register 09 (hex) has an irregular structure. Two register -A and -B are correspond to the sub-address 09
(hex). When SEL09 of the register 0E (hex) is 0, register 09 (hex)-A is selected, else register 09 (hex)-B is
selected.
VCOLK
NAK
This bit become 0 in case of abnormal oscillation of embedded VCO.
(Tuner interface I2C bus mode)
This bit becomes 1 in case of no acknowledge from the tuner PLL.
FSYNC
VSYNC
This bit becomes 1 iwhen Frame synchronization is achieved.
This bit becomes 1 when the punctured mapping synchronization is achieved.
QSYNC
ID
This bit becomes 1 when carrier lock is achieved.
This bit is always 1.
Sub address 09 (hex)-B
Sub address 0A (hex)
Read
Read
CM_LOW
CM_UPR
Constellation Monitor
Constellation Monitor
These registers can be access when SEL09 of register 0E (hex) is 1.
CM15 to CM0
(MSB) (LSB)
Monitor value of the QPSK constellation. This value depends on the AGC
reference (reg. 21 (hex)). Refer to Fig.1.
– 19 –
CXD1961AQ
Sub address 0B (hex)
Read
CAR_OFST
Carrier Capture offset value
OFC7 to OFC0
OFC7: Sign
Offset frequency at the point of carrier capture
(Latest offset frequency is output to register 02 (hex))
(offset frequency) = (Symbol rate) × OFC [7:0] ÷ 1024 (Hz)
Ex.) 20MSPS OFC [6:0] = 11110000 (bin)
(offset freq.)
= 20MHz × (–16) ÷ 1024
= –312.5kHz
Sub address 0C (hex)
Write
MQS/CLK
Qsync mode/Clock recovery
MQS3 to MQS0
(MSB) (LSB)
Threshold for carrier lock detection
AK1 to AK0
CE1 to CE0
Clock recovery loop filter coefficient
00: Max. 11: min.
Clock recovery loop filter gain
00: Min. 11: Max.
Clock recovery range is approximately ±200ppm with CE (1:0) = 11.
Sub address 0D (hex)
RATE2 to RATE0
Write
CODE/SRS
Code rate select/Symbol rate select
Code rate setting
RATE2 RATE1 RATE0
Code rate R
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1/2
2/3
3/4
4/5
5/6
6/7
7/8
SRSAVE
By saving several NCO control word to sub registers initially, symbol rate can be
changed by setting the number of the sub register in which the desired control
word is saved. There are three sub registers.
– 20 –
CXD1961AQ
SRS1 to SRS0
(To set the symbol rate directly without the above function)
Set SRSAVE = 0, SRS [1:0] = (1,1) and set control word to registers 18, 19, 1A
(hex).
(To save control word to sub registers)
Set SRSAVE = 1 and set sub register No. ((0, 0) or (0, 1) or (1, 0)) to SRS [1:0].
Then set control word to registers 18, 19, 1A (hex).
The control word is set to both the clock recovery circuit and the selected sub
register.
(To set the symbol rate with the above function)
Set SRSAVE = 0, and set sub register No. of control word to be set. The control
word saved in the sub register is set to the clock recovery circuit.
Sub address 0E (hex)
PBYCK
Write
OUT_CNT
Output control and polarity
BYTCLK polarity
0: For falling edge 1: For rising edge
DOH1Z
1: Output Hi-Z mode (PKTCLK, BYTCLK, PKTERR, DATA [7:0])
DOPS
0: Parallel output mode 1: Serial output mode
Refer to Electric characteristics
PPKER
PPKCK
PKTERR polarity
PKTCLK polarity
0: PKTERR: H at uncorrectable packet
1: PKTERR: L at uncorrectable packet
0: PKTCLK: H at data / L at parity
1: PKTCLK: L at data / H at parity
MBYCK
VCKVDT
SEL09
1: BYTCLK mask mode
In this mode BYTCLK is forced Low during parity data output
1: Viterbi decode data VDT (Pin 64) and clock VCK (Pin 65) output enable
0: VDT and VCK are fixed low.
Read register 09 (hex)-A, -B selection
0: 09 (hex)-A is selected
1: 09 (hex)-B is selected
– 21 –
CXD1961AQ
Sub address 0F (hex)
SINV
Write
MOD_CONT Mode Control
I/Q exchange
1: normal operation
SYSSEL
DFSK1P
RSSK1P
TUNSEL
TUNEN
Not assigned. Input 0.
1: Nyquist roll off filter bypass mode
1: Reed-Solomon decoder bypass mode
Tuner interface mode
0: I2C bus mode 1: 3 wire mode
1: Tuner interface enable
TUNSEL
TUNEN
Pin 12
Hi-Z
Pin 13
Hi-Z
Pin 14
Hi-Z
mode
—
Don't care
0
1
1
0
1
clock out
data out
Hi-Z
data in out
I2C bus
3 wire
clock out Latch Enable
Refer to reference circuit (5).
MFSYNC
AGCLP
Parameter for frame synchronization protection
0: normal operation mode
1: powerful protection mode
AGC loop filter gain
1: normal operation
0: large gain
– 22 –
CXD1961AQ
Sub address 10 (hex)
MAGC
Write
AGC/RST
AGC and Reset
AGC mode 0: normal mode 1: bus control mode
In normal mode, PWM output is controlled so that I2 + Q2 (register 00hex) should
become approximately equal to the reference level set in register 21 (hex). In bus
control mode, data of the register 21 (hex) is directly converted to PWM output.
PAGC
AGC polarity 0: For tuner whose gain increases by higher AGC control voltage
1: For tuner whose gain increases by lower AGC control voltage
Select mode according to tuner AGC type.
MVSYNC
CKVSEL
Input 0
CKV (Pin 69) output mode
0: symbol clock output
1: sampling clock output
QPRST
1: QPSK block reset (set 0 for normal operation)
To reset QPSK block, set this bit to 1 and then set this bit to 0 again.
VTRST
RSRST
1: Viterbi block reset (set 0 for normal operation)
Reset operation is same as QPRST.
1: Deinterleaver and Reed-solomon block reset (set 0 for normal operation)
Reset operation is same as QPRST.
VCORST
1: NCO block reset (set 0 for normal operation)
Reset operation is same as QPRST.
– 23 –
CXD1961AQ
Sub address 11 (hex)
Write
QTH
Qsync Threshold and QBEC period
QTH5 to QTH0
(MSB) (LSB)
Threshold for carrier lock detection
These parameters relate to QTLEV [1:0] in register 1F (hex) and
AGC reference 21 (hex).
Ex.) QTLEV [1:0] = 01 AGC ref = 32 (hex)
QTH [5:0] = 101000
TQBEC1 to TQBEC0
Count period of QPSK bit error count
TQBEC1 TQBEC0
Count period
0
0
1
1
0
1
0
1
28
216
219
223
Select TQBEC [1:0] = 10 to use QPSK BER indicator (register 07 (hex))
Sub address 12 (hex)
VTH4 to VTH0
Write
VTH
Viterbi sync threshold and period
Threshold for punctured mapping synchronization
11110: Min. 00000: Max.
TVS2 to TVS0
Detection period for punctured mapping synchronization
110: Min 000: Max.
code rate
1/2
VTH4 to VTH0, TVS2 to TVS0
8B (hex)
2/3
BB (hex)
3/4
CB (hex)
4/5
D3 (hex)
5/6
DB (hex)
6/7
E3 (hex)
7/8
E3 (hex)
– 24 –
CXD1961AQ
Sub address 13 (hex)
Sub address 14 (hex)
Sub address 15 (hex)
Sub address 16 (hex)
Sub address 17 (hex)
Write
Write
Write
Write
Write
TUN_DAT1
TUN_DAT2
TUN_DAT3
TUN_DAT4
TUN_DAT5
Tuner control data
Tuner control data
Tuner control data
Tuner control data
Tuner control data
(I2C bus mode)
Set TUNSEL = 0 and TUNEN = 1 in the register 0F (hex).
13 (hex): Tuner PLL IC slave address + 0 (write mode)
14 to 17 (hex): Write data (tuning parameter)
I2C bus starts write operation when data setting to register 17 (hex) is finished. In
case of no acknowledge from tuner PLL IC, NAK in the register 09 (hex)-A is set
to 1.
(3 wire mode)
Set TUNSEL = 1 and TUEN = 1 in the register 0F (hex). 28 bits data (register 13
to 15 (hex) and upper 4bit of the register 16 (hex)) are transmitted serially. To
start operation, dummy data setting to the register 17 (hex) is needed.
Refer to the reference circuit (5).
Sub address 18 (hex)
Sub address 19 (hex)
Sub address 1A (hex)
Write
Write
Write
SYM_RATE1 Control word for multi-rate oscillation
SYM_RATE2 Control word for multi-rate oscillation
SYM_RATE3 Control word for multi-rate oscillation
NCO23 to NCO0
The relation between symbol rate and the control word of the NCO is:
(MSB)
(LSB)
NCO [23:0] = (symbol rate) × 222 ÷ (crystal frequency)
Ex.) Symbol rate 20MSPS crystal 32MHz
NCO [23:0] = 20 × 106 × 222 ÷ 32 × 10–6
= 2,621,440
= 221 + 219
NCO21 = NCO19 = 1, other = 0
– 25 –
CXD1961AQ
Sub address 1B (hex)
CARRST
Write
CAR_RST
Carrier loop reset
1: Carrier loop filter reset
Reset operation is same as QPRST (register 10hex)
CADRST
CLKRST
RANGE
FSYSEL
FSYTHD
1: Carrier recovery frequency loop reset
Reset operation is same as QPRST (register 10hex)
1: Clock recovery loop reset
Reset operation is same as QPRST (register 10hex)
Carrier capture range
0: Carrier capture range = ±Rs/8
1: Carrier capture range = ±Rs/16
Frame synchronization detector mode 0: Hard decision
1: Soft decision
Frame synchronization threshold
0: Low
1: High
Sub address 1C (hex)
Sub address 1D (hex)
Write
N.A.
Not Assigned
Input 0 to all bits.
Write
DC_BIAS
A/D Converter DC_BIAS
DC offset is added to the output of the A/D converter when MOFST in the
register 1E (hex) is 0.
BSI3 to BSI0
DC offset for I channel A/D converter. BSI3: sign
Offset range is from –8 to +7.
BSQ3 to BSQ0
DC offset for Q channel A/D converter. BSI3: sign
Offset range is from –8 to +7.
– 26 –
CXD1961AQ
Sub address 1E (hex)
RSTEN
Write
CAR/DC
Carrier recovery and DC offset
1:Carrier loop filter reset enable (Set to 1 for normal operation)
GAIN1 to GAIN0
Gain setting for carrier recovery loop
(default ×1)
GAIN1
GAIN0
Gain
×1
0
0
1
1
0
1
0
1
×2
×4
×8
TCAR1 to TCAR0
MOFST
Mode setting for carrier recovery frequency loop: default TCAR [1:0] = 10.
1: A/D converter DC offset cancellation mode
0: A/D converter DC offset addition mode
OFSTEN
OFSTGN
1: A/D converter DC offset control (cancel or add) enable
0: A/D converter DC offset control (cancel or add) disable
A/D converter DC offset cancellation loop filter gain
1: ×1
0: ×1/2
– 27 –
CXD1961AQ
Sub address 1F (hex)
TQS1 to TQS0
Write
CAR_MODE Carrier recovery mode
Carrier lock detection period 00: min. 11: max.
Default is TQS [1:0] = 10
FLOOP
0: Carrier recovery by phase loop
1: Carrier recovery by phase and frequency loop (default)
TRACK
default: 0
FLMOD
1: Carrier offset frequency is set by BSC [6:0].
0: Carrier offset frequency is set by the internal loop. (default)
FLSTEP
default: 1
QTLEV1 to QTLEV0
Gain for carrier lock detection circuit.
Default is QTLEV [1:0] = 00
Sub address 20 (hex)
Write
CAR_BIAS
Carrier frequency offset bias
BSC7 to BSC0
BSC7: sign
Carrier offset frequency setting
This mode is good when FLMOD = 1.
(Carrier offset) = (Symbol rate) × BSC [7:0] ÷ 1024 (Hz)
Sub address 21 (hex)
AGCR7 to AGCR0
Write
AGC_REF
AGC reference
Input level reference for AGC operation
Refer to the explanation of register 10 (hex)
– 28 –
CXD1961AQ
Application Circuit
(1) A/D Converter
390Ω
Analog
VSS
Connect AVD0
and AVD1 to analog
+3.3V supply
0.1µF
0.1µF 0.1µF
0.1µF
1kΩ
0.1µF
0.1µF
Baseband
Q input
1kΩ 390Ω
1kΩ
390Ω
Baseband
I input
0.1µF
100
99
95
94
98
97
96
93
1kΩ
1
2
AVS0
RB0
CXD1961AQ
390Ω
0.1µF
Analog
VSS
(2) Clock Recovery circuit
Connect AVD2
and AVD4 to analog
+3.3V supply
15kΩ
4.7µF
Analog
VSS
2.2µF
100kΩ
22Ω
0.1µF
0.1µF
84
10kΩ
Analog
VSS
1kΩ
92
91
90
89
88
87
86
85
CXD1961AQ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 29 –
CXD1961AQ
(3) Crystal
Crystal
7pF
Crystal
Daishinku AT-49
32.0MHz
63
62
61
60
XI
XO
470kΩ
Connect AVD3 to ditital +3.3V supply
7pF
AVS3
AVD3
Digital
VSS
0.1µF
CXD1961AQ
(4) AGC
This is an example of how to set AGC control
voltage from 0 to 5V.
Power supply for the OP-Amp is 7V.
OP-Amp
20kΩ
68
AGCPWM
To tuner AGC input
5.6kΩ
10kΩ
0.1µF
CXD1961AQ
Analog
VSS
(5) Tuner Interface
(3 wire type) suitable for GEC Plessey SP5658
100Ω
ENABLE
12
13
SDAT/SCL
SCLK
100Ω
DATA
100Ω
CLOCK
SEN/SDA
14
SP5658
CXD1961AQ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 30 –
CXD1961AQ
(5) Tuner Interface
(I2C bus type) suitable to GEC Plessey SP5659 etc. (4 bytes of data can be written)
+3.3V
10kΩ
100Ω
10kΩ
SDA
SCL
12
13
SDAT/SCL
SCLK
100Ω
SEN/SDA
14
SP5659
CXD1961AQ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 31 –
CXD1961AQ
Appendix
Fig.1 Constellation monitor output vs. C/N
104
103
4
6
8
10
12
14
16
18
20
22
24
26
28
C/N [dB]
This figure is an example when AGCREF is set to 32 (hex).
The monitor output value is proportional to AGCREF.
Monitor output : CM [15:0] CPU I/F register 09-B (hex) and 0A (hex)
– 32 –
CXD1961AQ
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.24
0.15
M
+ 0.2
0.1 – 0.05
0° to 15°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
– 33 –
相关型号：
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