CXD2027Q_技术文档

CXD2027Q/R

DBS Audio Signal Processor

For the availability of this product, please contact the sales office.

Description

CXD2027Q

CXD2027R

The CXD2027Q/R are audio signal processors

designed for DBS applications. These LSIs perform

all digital processing from QPSK demodulation to

analog audio output on a single chip.

64 pin QFP (Plastic)

80 pin LQFP (Plastic)

Features

QPSK and PCM demodulators and DAC output

are configured on a single chip.

Descrambler interface according to the COATEC

system and SkyPort system .

Structure

Silicon gate CMOS IC

Functions

QPSK demodulator

Applications

TVs, VCRs with built-in BS tuners

• Carrier, clock and data regeneration

• ALC and VCXO adjustment-free

PCM demodulator

• Frame sync protection by correlation detection

• De-interleaving and descrambling

• BCH error correction, range bit error correction

• Audio data range control

Expansion from 10 to 14 bits in A mode

Upper bit majority correction in B mode

• Control sign integration correction, chargeable

flag integration correction by master frame

synchronization

Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)

• Supply voltage

• Input voltage

• Output voltage

V^DD

Vss – 0.5 to +7.0

V

VI Vss – 0.5 to VDD + 0.5V

V^OVss – 0.5 to VDD + 0.5V

• Storage temperature Tstg

–55 to +150

°C

Operating Conditions

• Supply voltage

• Operating temperature Topr

VDD

4.75 to 5.25

–20 to +75

V

°C

• Interface output for external DAC

• Digital interface output

1-bit DAC output

• Quadruple oversampling filter

• Digital de-emphasis circuit

• 1-bit stereo DAC with 2nd-order ∆∑ format noise

shaper

S/N ratio : 90dB (Typ.)

Distortion: 0.011% (Typ.)

CPU interface

• I²C bus

Descrambler interface

• COATEC system, SkyPort system

Mute functions

• Error occurrence frequency detection mute

• Audio chargeable flag detection mute

• Control sign (B7) detection mute

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94808-ST

CXD2027Q/R

DATB

DATA

DATO

DSLA

TX

SASL

SCLK

SDA

NSYN

DTUP

CC1

BITI

CK2M

DSLB

FRAM

BITO

MCKO

– 2 –

CXD2027Q/R

Pin Configuration 1

CXD2027Q

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

VDD5

M23O

M23I

PHAA

ALCO

VSS9

TST7

RT

VSS6

VSS5

RNO

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

VDD2

RPO

VSS4

TST1

VSS3

LPO

ADIN

ADVD

ADVS

RB

VDD1

LNO

VSS2

VSS1

GR

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

– 3 –

CXD2027Q/R

Pin Configuration 2

CXD2027R

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

N.C.

61

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

N.C.

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

N.C.

SASL

VSS6

VSS5

RNO

N.C.

VDD2

RPO

VSS4

TST1

VSS3

LPO

VDD1

N.C.

LNO

VSS2

VSS1

N.C.

VDD5

M23O

M23I

PHAA

ALCO

VSS9

N.C.

TST7

RT

N.C.

ADIN

ADVD

ADVS

RB

GR

TST0

N.C.

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

– 4 –

CXD2027Q/R

Pin Description 1

CXD2027Q (64pin QFP)

No.

Symbol

I/O

Pin Description

Remarks

1

TST0

I

Test pin; normally low

Internal pull down

Internal pull up

2

MRST

VSS Digital

BITO

Master reset; H: normal operation; L: reset

Digital ground

3

—

O

I

4

Bit stream output after PSK demodulation

Bit stream input after PSK demodulation

External descrambler pin

Data input 2 after BCH correction (for COATEC)

Data input 1 after BCH correction (for SkyPort)

Digital +5V power supply

2.048MHz clock output

5

BITI

TTL input

6

DSLB

DSLA

DATB

DATA

VDD Digital

I

7

I

8

I

9

I

10

—

O

I

11 CK2M

12 FRAM

13 DATO

14 CC1

15 TX

Frame start bit flag

Data output after BCH correction

Control sign first bit output

Digital format audio output

Test pin; normally low

16 TST2

17 TST3

18 TST4

19 TST5

Internal pull down

I

Test pin; normally low

I

Test pin; normally low

I

Test pin; normally high

20

21

VSS Digital

VSS D/A

—

O

—

O

—

I

Digital ground

Analog ground

22 LNO

Lch D/A converter output

Analog +5V power supply

Lch D/A converter output

Analog ground

23

VDD D/A

24 LPO

25

VSS D/A

26 TST1

Test pin; normally low

Internal pull down

27

VSS D/A

—

O

—

O

—

I

Analog ground

28 RPO

Rch D/A converter output

Analog +5V power supply

Rch D/A converter output

Analog ground

29

VDD D/A

30 RNO

31

32

VSS D/A

VSS Digital

Digital ground

33 SASL

34 TST6

I²C bus slave address select (L: D4, H: D6)

Test pin; normally low

Internal pull down

I

– 5 –

CXD2027Q/R

No.

Symbol

I/O

Pin Description

Remarks

35 AUD

36 LRCK

37 BCLK

38 F256

39 DTUP

40 NSYN

O

—

I

Audio data output for external DF/DAC

LR clock output for external DF/DAC

Bit clock output for external DF/DAC

Clock output for external DF/DAC

CCUP: control sign update flag / DED: BCH 2 error detection Switched by I²C bus

Asynchronous flag (H: asynchronous; L: synchronous)

Digital +5V power supply

41

VDD Digital

42 SDA

43 SCLK

SDA (I²C bus)

I²C bus compatible

I

SCL (I²C bus)

44

VSS Digital

—

I

Digital ground

45 TST8

46 MUTE

Test pin; normally low

I

External forced muting input

Digital ground

TTL input

47

V^{SS Digital}

—

O

I

48 MCKO

49 MCKI

50 PHAB

MCKI inversion output

24.576MHz clock input

O

—

O

I

Clock regeneration phase error data output

Digital +5V power supply

M23I inversion output

51

52

VDD Digital

53 M23O

54 M23I

55 PHAA

56 ALCO

22.909088MHz clock input

Carrier regeneration phase error data output

ALC A/D control output

Digital ground

O

—

I

57

VSS Digital

58 TST7

59 RT

60 ADIN

Test pin; normally low

I

A/D converter VRT input

Analog data input

I

61

62

VDD A/D

VSS A/D

—

I

Analog +5V power supply

Analog ground

63 RB

64 GR

A/D converter VRB input; connect to analog ground

A/D converter VGR input; connect to analog ground

I

– 6 –

CXD2027Q/R

Pin Description 2

CXD2027R (80pin LQFP)

No.

Symbol

N.C.

I/O

Pin Description

Remarks

1

—

I

Non-connection

2

MRST

VSS Digital

BITO

Master reset; H: normal operation; L: reset

Digital ground

Internal pull up

3

—

O

I

4

Bit stream output after PSK demodulation

Bit stream input after PSK demodulation

External descrambler pin

Data input 2 after BCH correction (for COATEC)

Data input 1 after BCH correction (for SkyPort)

Digital +5V power supply

2.048MHz clock output

Frame start bit flag

5

BITI

TTL input

6

DSLB

DSLA

DATB

DATA

VDD Digital

I

7

I

8

I

9

I

10

—

O

I

11 CK2M

12 FRAM

13 DATO

14 CC1

15 TX

Data output after BCH correction

Control sign first bit output

Digital format audio output

Test pin; normally low

Test pin; normally high

Non-connection

16 TST2

17 TST3

18 TST4

19 TST5

20 N.C.

21 N.C.

22 N.C.

Internal pull down

I

—

O

—

O

—

I

Non-connection

23

24

VSS Digital

VSS D/A

Digital ground

Analog ground

25 LNO

26 N.C.

Lch DAC output

Non-connection

27

VDD D/A

Analog +5V power supply

Lch DAC output

28 LPO

29

VSS D/A

Analog ground

30 TST1

Test pin; normally low

Analog ground

Internal pull down

31

VSS D/A

—

O

—

32 RPO

Rch DAC output

33

VDD D/A

Analog +5V power supply

Non-connection

34 N.C.

– 7 –

CXD2027Q/R

No.

Symbol

I/O

Pin Description

Rch D/A converter output

Remarks

35 RNO

O

—

I

36

37

VSS D/A

Analog ground

VSS Digital

Digital ground

38 SASL

39 N.C.

40 N.C.

41 N.C.

42 TST6

43 AUD

44 LRCK

45 BCLK

46 F256

47 DTUP

48 NSYN

I²C bus slave address select (L: D4, H: D6)

Non-connection

Internal pull down

—

I

Non-connection

Test pin; normally low

O

—

I

Audio data output for external DF/DAC

LR clock output for external DF/DAC

Bit clock output for external DF/DAC

Clock output for external DF/DAC

CCUP: control sign update flag/DED: BCH 2 error detection

Asynchronous flag (H: asynchronous; L: synchronous)

Digital +5V power supply

SDA (I²C bus)

Switched by I²C bus

49

VDD Digital

50 SDA

51 SCLK

I²C bus compatible

I

SCL (I²C bus)

52

VSS Digital

—

I

Digital ground

53 TST8

54 MUTE

Test pin; normally low

I

External forced muting input

Digital ground

TTL input

55

VSS Digital

—

O

I

56 MCKO

57 MCKI

58 PHAB

MCKI inversion output

24.576MHz clock input

O

—

O

I

Clock regeneration phase error data output

Digital +5V power supply

Non-connection

59

VDD Digital

60 N.C.

61 N.C.

62 N.C.

Non-connection

63

VDD Digital

Digital +5V power supply

M23I inversion output

64 M23O

65 M23I

66 PHAA

67 ALCO

22.909088MHz clock input

Carrier regeneration phase error data output

ALC A/D control output

Digital ground

O

—

I

68

VSS Digital

69 N.C.

70 TST7

Non-connection

Test pin; normally low

– 8 –

CXD2027Q/R

No.

Symbol

I/O

Description

Remarks

71 RT

I

—

I

A/D converter VRT input

Non-connection

72 N.C.

73 ADIN

Analog data input

74

75

VDD A/D

VSS A/D

—

I

Analog +5V power supply

Analog ground

76 RB

A/D converter VRB input; connect to analog ground

A/D converter VGR input; connect to analog ground

A/D test pin; normally low

77 GR

78 TST0

79 N.C.

80 N.C.

I

Internal pull down

—

Non-connection

Absolute Maximum Ratings

(Ta = 25°C, Vss = 0V)

Item

Symbol

VDD

Ratings

Unit

V

Supply voltage

Vss – 0.5 to +7.0

Vss – 0.5 to VDD + 0.5

–20 to +75

Input voltage

VI

V

Output voltage

VO

V

Operating temperature

Storage temperature

Topr

Tstg

°C

–55 to +150

I/O Pin Capacitance

(V^DD= VI = 0V, f = 1MHz)

Item

Symbol

C^IN

Min.

Typ.

Max.

9

Unit Corresponding pins

1

2

Input pin capacitance

10

11

10

3

pF

4

5

Output pin capacitance

COUT

CI/O

Input/output pin capacitance

1

3

Input pins other than ²and

2

SCLK

3

BITI, DSLB, DSLA, DATB, DATA, TST5

4

5

All output pins

SDA

– 9 –

CXD2027Q/R

Electrical Characteristics

[DC characteristics]

(VDD = 5V ± 0.25V, Vss = 0V, Ta = –20 to +75°C)

Corre-

Measurement

conditions

Item

Symbol

Min.

Typ.

Max.

Unit

sponding

pins

Power consumption

Input/output voltage

PD

VDD = 4.75 to 5.25V

180

Vss

280

350

mW

V

1

2

VI, VO

VIH

VIL

VDD

0.7VDD

CMOS input

0.3VDD

0.8

VIH

VIL

2.2

3

4

TTL input

Input

V

voltage

Vt+

Vt–

0.7VDD

High level

0.3VDD

500

Low level

Vt+

–

Vt–

0.5

Hysteresis voltage

5

6

Input rise/fall time

Output voltage

tr, tf

VOH

VOL

VOH

VOL

VOH

VOL

0

ns

IOH = –2mA

IOL = 4mA

IOH = –4mA

IOL = 4mA

IOH = –4mA

IOL = 8mA

IOL = 3mA

IOL = 6mA

VDD – 0.8

0.4

VDD – 0.8

7

8

9

0.4

V

0.4

0.6

0

1

All pins

2

4

Input pins other than ³and

3

BITI, DSLB, DSLA, DATB, DATA, MUTE

SDA, SCLK

4

5

6

7

8

9

All input pins

7

9

Output pins other than

LNO, LPO, RPO, RNO

,

⁸and

BITO, CK2M, FRAM, DATO, CCI, TX

SDA, SCLK

– 10 –

CXD2027Q/R

Corre-

sponding

pins

Measurement

conditions

Item

Symbol

Min.

–10

–40

Typ.

Max.

10

Unit

µA

1

II

VIN = VSS or VDD

Normal input pin

With pull-up

resistor

2

IIL

VIN = VSS

–100

100

–240

µA

Input

leak

With pull-down

3

4

5

IIH

II

VIN = VDD

40

240

40

µA

current resistor

Bidirectional pin

(during input state)

VIN = VSS or VDD

VIN = VSS

–40

–10

Output leak current

IOZ

–10

(I²C bus)

1

2

4

Input pins other than

,

³and

2

MRST

3

TST0, TST1, TST2, TST3, TST4, SASL, TST6

BITI, DSLB, DSLA, DATB, DATA, TST5

SDA, SCLK

4

5

[Oscillation cell electrical characteristics]

(VDD = 5V ± 0.25V, Ta = –20 to +75°C)

Corre-

Measurement

conditions

Item

Symbol

Min.

Typ.

Max.

Unit

sponding

pins

Logic threshold value

LVth

VIH

VDD/2

V

Ω

6

0.7VDD

Input voltage

VIL

0.3VDD

2.5M

7

8

Feedback resistance

Output voltage

RFB

VOH

VOL

VIN = VSS or VDD

IOH = –12mA

IOL = 12mA

250k

1M

VDD/2

V

VDD/2

6

MCKI, M23I

7

MCKI, MCKO, M23I, M23O

8

MCKO, M23O

– 11 –

CXD2027Q/R

[Internal A/D converter characteristics]

Absolute Maximum Ratings

(Ta = 25°C)

Item

Symbol

Ratings

+7.0

Unit

V

Supply voltage

AVD

Input voltage (analog) AIN

Input voltage (digital)

AVD to AVS

VDD to VSS

AVD to AVS

V

Reference voltage

RB, RT

V

Operating Conditions

Item

Symbol

AVD, AVS

l DVS – AVS l

RB

Ratings

4.75 to 5.25

0 to 100

0 to

Unit

V

Supply voltage

mV

Reference input

voltage

V

RT

to 3.75

100 to 300

(typ. 200)

mV^p-p

V

Amplitude

AIN

Analog input

DC level

typ.1.25

Operating ambient

temperature

°C

Topr

–20 to +75

– 12 –

CXD2027Q/R

[AC characteristics]

(VDD = 5.0V ± 0.25V, Ta = 25°C)

Item

Conditions

Min.

Typ. Max. Unit

ALC characteristics Deviation from standard input level 200mVp-p

±50

%

Carrier

regeneration

PLL pull-in range

Pull-in frequency relative to 5.7272MHz.

Includes temperature characteristics (–20 to +75°C)

and supply voltage fluctuation (±5%) of VCXO.

Upper

Lower

Upper

Lower

+750

–450

+300

–100

Hz

Clock

regeneration

PLL pull-in range

Pull-in frequency relative to 2.048MHz.

Includes temperature characteristics (–20 to +75°C)

and supply voltage fluctuation (±5%) of VCXO.

Hz

Performance guaranteed only when using constants of the recommended oscillation circuit.

22.909088MHz (for carrier regeneration PLL) VCXO circuit

PHAA

M23I

M23O

100K

2.7µ

68

4.7K

12p (UJ)

390p (CH)

22K

HVU359

X'tal : Daishinku AG8865C

VC : Hitachi HVU359

: Matsushita ELJ-FC series

0.01µ

L

24.576MHz (for clock regeneration PLL) VCXO circuit

PHAB

MCKI

MCKO

100K

330

4.7K

10p (UJ)

1800p (CH)

22K

HVU359

X'tal : Daishinku AG8865C

VC : Hitachi HVU359

0.047µ

– 13 –

CXD2027Q/R

(VDD = 5.0V ± 0.25V, Ta = –20 to +75°C, CL = 60pF)

Item

BITI set-up time

Symbol

tsu1

Conditions

Min.

Typ.

Max. Unit

DATA set-up time

DATB set-up time

BITI hold time

Value relative to CK2M fall

32

ns

th1

DATA hold time

DATB hold time

Value relative to CK2M fall

0

ns

(VDD = 5.0V ± 0.25V, Ta = –20 to +75°C, CL = 60pF)

Item

BITO delay time

DATO delay time

NSYN delay time

FRAM delay time

DTUP delay time

CC1 delay time

AUD delay time

LRCK delay time

Symbol

td1

Conditions

Min.

Typ.

Max. Unit

17

24

37

23

38

21

28

26

ns

td2

td3

Value relative to CK2M fall

td4

td5

td6

td7

Value relative to BCLK fall

td8

BITI, DATA, DATB

tsu1

th1

CK2M

td1 to td6

BITO, DATO, NSYN,

FRAM, DTUP, CC1

BCLK

td7 to td8

AUD, LRCK

– 14 –

CXD2027Q/R

Internal 1-bit DAC analog characteristics

(fs = 48kHz, VDD = 5.0V, Ta = 25°C, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, B mode)

Item

Min.

Typ.

90

Max.

Unit

dB

Remarks

1

S/N

(EIAJ)

THD + N

Output level

1

0.011

1.95

%

(EIAJ)

2

V(rms)

"A" characteristic weighting filter used

When master clock is 256fs

2

The following circuit is used for analog characteristics measurement.

820p

CXD2027Q/R

5.4k

4.7k

0.015

4.7k

130k

22

100

LNO (RNO)

4.7k

47p

OUTPUT

12k

1800p

820p

4.7k

820p

LPO (RPO)

Lch

ANALOG

DATA

ANALOG TESTER

(ADVANTEST T7342)

ANALOG

CIRCUIT

TEST DISC

CXD2027Q/R

Rch

– 15 –

CXD2027Q/R

Description of Functions

• ALC

This detects the fluctuation of the input QPSK modulated signal level and absorbs the fluctuation by

controlling A/D VRT. With this function, a signal is output from ALCO after PWM modulation, and should be

fed back to the RT pin after integration.

• Carrier regeneration

A 5.727272MHz carrier is regenerated.

The input QPSK modulated signal is A/D converted at a sample rate of 22.909088MHz (5.727272MHz × 4),

and control voltage is generated using that sampling position as phase error data. The control voltage is

output from the PHAA pin after PWM modulation, and controls VCXO, which consists of an internal

oscillation cell and external crystal.

• Clock regeneration

This is a PLL circuit with 24.576MHz clock. It is 512 × fs, for use with the DAC.

Phase comparison is carried out using the regenerated I and Q signals and VCXO divided output, and

control voltage is generated. After PWM modulation, the control voltage is output from the PHAB pin, and

controls VCXO, which consists of an internal oscillation cell and external crystal.

• Data regeneration

A 2.048MHz bit stream is regenerated from the regenerated I and Q signals.

• Frame sync and master frame sync

Correlated detection and competitive counter format is used for sync protection. The number of rear

protection is set at three times, and that of front protection is set at 3, 5, 7, or 9 times.

Also, synchronizing to the master frame can be done when the master frame signal is being sent to the

control sign 14th bit. In this case, the number of rear protection is set to 2 times, and that of front protection

is set at 7, 9 or 11 times.

• Descramble

A superimposed PN signal is removed for BS.

Also, there is a built-in interface for an external descrambler unit.

• De-interleave

The data interleaved by the built-in 4kbit SRAM is returned to the correct data array.

• (63, 56) BCH sign error correction

This performs (63, 56) BCH sign error correction. Error capability is 1 error correction, 2 errors detection.

• Range bit BCH sign error correction

This performs (7, 3) BCH sign error correction. Error capability is 1 error correction, 2 errors detection.

When there are 2 errors, the previous value is held.

– 16 –

CXD2027Q/R

• Control sign integration detection and 8th range bit integration detection

Integration detection is carried out in units of 15 frames. When a match of 12/15 or more is obtained, a

defined control sign is detected. However, updating is every 18 frames.

When a match of 12/15 or more is not obtained, the previous value is held.

Further, synchronizing to the master frame can be done when the master frame signal is being sent to the

control sign 14th bit.

After integration detection, the control sign and range bit can be read by the I²C bus.

• 10 → 14 bit data expansion

During A mode, the instantaneously compressed 10 bits of audio data are expanded to 14 bits according to

the range expansion rule. The lower bits of data are fixed at a set value during expansion, and the data is

treated as 16 bits.

• Upper bit majority detection

During B mode, this carries out upper bit majority detection and protects the upper bits.

• Mute signal generation

This performs muting by the external MUTE signal and internal logic, and also generates a mute signal

according to the mute setting from the I²C bus.

• Audio data interpolation

This receives the bit error detection signal and interpolation indication signal from majority detection, and

then carries out the average value interpolation or the previous value hold.

• Clock generation for D/A converter

This generates the clock for the DAC.

• Digital filter (DF) and de-emphasis

A 2ch 1-bit DAC with 2nd-order ∆∑ format noise shaper of quadruple oversampling filter is built in.

The output format is differential.

De-emphasis function corresponding to the mode is also built in.

• Audio interface

One of the following three output formats can be selected.

1) SONY: bit clock 32 fs/ MSB first/ 16 bits (for built-in D/A converter)

2) IIS: SONY format 1 BCLK delay

3) Bit clock 64fs / MSB first / 16 bits rearward truncation

• Digital interface

Conforms to the following digital audio interface format: type II form I (for consumer digital audio equipment)

• I²C bus interface

Control by microcomputer is carried out by the I²C bus I/F.

The slave address can be switched by controlling SASL; for low: D4, for high: D6.

– 17 –

CXD2027Q/R

• Output channel selection

The output channels provided are analog output for built-in D/A converter Lch/Rch, one output system for

external D/A audio output and one for digital audio output. Channel selection can be done easily through

the I²C bus.

Unused channels can be suppressed using the I²C bus.

• Audio output selection

Mode selection can be carried out via the I²C bus.

• Zero cross muting

The I²C bus can be used for zero cross muting.

When a mute signal is input, muting is not carried out until zero cross conditions are satisfied for 1 frame.

If these conditions are not met for 1 frame, muting is forced at the next frame.

Zero cross mute cancel is performed in frame units.

The conditions for zero cross are a change in audio data MSB, or when audio data value is between 00ffh

and ff00h.

• Description of mute function

A signal is treated as a mute signal in the following cases:

1) when asynchronous

2) control sign 7th bit (non-broadcast flag) or 16th bit (audio suppression flag) is high

3) 8th range bit (audio chargeable flag) is high (however, only channel for high)

4) number of double error flags goes over a certain TH level (error frequency detection mute)

5) audio carrier (5.7272MHz) can not be detected

6) an I²C bus mute flag is up

7) for other than audio

1. Asynchronous flag mute

Muting is applied when an asynchronous state exists. Also, the number of front sync protection can be

changed among 3, 5, 7 or 9 times by the I²C bus, so the conditions for asynchronous flag muting can be

changed.

2. Muting by control sign 7th and 16th bits

The control sign 7th bit is a flag indicating broadcast or non-broadcast. If this bit is high, muting is

applied. Also, the I²C bus can be used so that this bit does not apply muting.

The control sign 16th bit audio suppression flag is used when broadcast channels are switched and

when transmission modes are switched. Both use the value after integration detection.

3. Chargeable flag detection mute

The 8th range bit indicates if audio data is for a chargeable broadcast or not. For a chargeable

broadcast, a flag ("H") goes up in that bit's position. When this bit is high, the broadcast is detected as

chargeable and muting is applied. Further, the I²C bus can be used for each channel so that this bit

does not apply muting. The value after every 18 frames of integration detection is used.

– 18 –

CXD2027Q/R

4. Error frequency detection mute

Muting is applied after BCH (63, 56) sign error correction is executed for every 64 data, when the

number of double error detection flags goes over a certain TH (threshold value) level during a certain

number of frames. Also, the I²C bus can be used so that muting is not applied. The setting values are

indicated below.

Number of frames: 128, 256, 512, 1024

Up to 32 double errors can be detected in one frame, so 1/16, 1/8, 1/4 and 1/2 of the maximum

detections for each frame number are set as the TH levels.

Therefore, there are 16 possible combinations, and the value is set by the I²C bus.

The TH level for muting cancel is half of the TH value when muting is applied; in other words, 1/32, 1/16,

1/8 and 1/4, respectively.

5. Carrier detection mute

When the BS broadcast audio carrier frequency of 5.7272MHz can not be detected by the PSK

demodulator unit, muting is applied. Also, the I²C bus can be used so that muting is not applied.

6. I²C bus muting

The I²C bus can apply forced muting to analog and AUD outputs. TX output is locked to analog output.

7. Muting other than audio

Muting is done for other than audio mode when the control sign 2nd and 3rd, or 4th and 5th bits are "H, H".

– 19 –

CXD2027Q/R

External descramble I/F circuit example

COATEC and SkyPort units can be connected simultaneously.

DASLC

I²C BUS

register

CXD2027Q/R

BITO

BITI

DSLB

DATO

DATB

DATA

DSLA

BSTMI

BSTMO

RGND

DATI

DSDO

DATI

DATO

SkyPort unit

DASL

Unit connection

COATEC unit

DSLB

Descramble format

COATEC, SkyPort

SkyPort

DSLA

0

1

0

1

0

1

COATEC

1

Internal

The COATEC unit and SkyPort unit can be connected simultaneously.

However, use the I²C bus to set DASLC at high when turning off the COATEC unit power supply.

– 20 –

CXD2027Q/R

Bit stream signal interface

CK2M

BITO is output at falling sync.

2047 2048

2048

1

2

3

4

1

2

BITO

Data interface after BCH error correction

CK2M

FRAM

DATO is output at falling sync.

DATO

2048

1

2

3

4

2047 2048

1

2

1ms

1 frame

Examples of error detection countermeasures for low C/N control sign and chargeable flag integration

detection

When C/N is low, NSYN frequently goes high level (asynchronous state).

In this case, problems such as wrong display or wrong detection of control sign 7th bit "broadcast/non-

broadcast" flag may occur due to incorrect integration detection. This can be improved using the

microcomputer software shown below.

Integration detection result can be updated only when NSYN is low level. Detection results of this IC are read

by the standard trigger of the microcomputer, and if the result values match for 5 to 6 times continuously, the

detection result is taken as an update for the system. It is also possible to update the integration detection

result by the continuous matching of 7 times or more. However, standard trigger cycle of the microcomputer

must be set about 18ms.

NSYN

Control sign,Chargeable flag

(IC)

Control sign,Chargeable flag

(microcomputer)

→ integration detection results

Standard trigger

(microcomputer)

1

2

3

4

5

6

18ms

– 21 –

CXD2027Q/R

Description of I²C bus

The I²C bus is a bidirectional serial bus system developed by Philips. It can transmit and receive data

between multiple devices using two lines, SCLK (Serial Clock) and SDA (Serial Data).

This LSI has a built-in I²C bus interface circuit and is compatible with slave RECEIVER and slave

TRANSMITTER operation modes.

For the transfer configuration, both RECEIVER mode and TRANSMITTER mode have sub-addresses.

RECEIVER mode

The first byte is the slave address, the second byte is the sub-address, and data is read at the third byte

and after. Continuous data reading is also possible. After transmission of the first byte, the sub-address

is made (+1) automatically.

TRANSMITTER mode

The first byte is the slave address, and data is sent at the second byte and after. Continuous data output

is also possible. After transmission of the first byte, the sub-address is made (+1) automatically.

When there is no verification answer from the master, the SDA line is released.

To read data, the sub-address for the data to be read is written in RECEIVER mode, then the data is read

in TRANSMITTER mode.

The SDA line is released for initial reset, so the bus is not occupied. Also, even if the IC supply voltage falls

to 0V, the bus is not occupied. Nonetheless, please keep within the absolute maximum ratings.

This bus is compatible not only with standard mode (maximum 100kbit/s) but with high speed mode

(maximum 400kbit/s) as well.

– 22 –

CXD2027Q/R

• Specifications

Data write (RECEIVER mode)

7654321

SLAm

0

1

76543210

SUBm

1

76543210

DATAm

1

Sm

Wm As

As

to

76543210

DATAm

1

76543210

DATAm

1

As

P

to

Data read (RECEIVER mode & TRANSMITTER mode)

7654321

SLAm

0

1

76543210

SUBm

1

Sm

Wm As

As

to

7654321

SLAm

0

1

76543210

DATAs

1

87654321

DATAs

1

Srm

Rm As

Am

XAm

P

to

Symbol

Description

m

s

from master to slave

from slave to master

Start Condition

S

Sr

Start Condition

P

Stop Condition

SLA

SUB

DATA

W

Slave Address

Sub Address

Data

0 : Write Master → Slave

1 : Read Slave → Master

R

A

Clock pulse for Acknowledgement (SDA: L)

Acknowledgement none (SDA:H)

XA

– 23 –

CXD2027Q/R

I²C bus control table

SASL

L

H

Slave address

D4 D6

MSB

bit7

Data

LSB

bit0

Sub-

R/W

address

bit6

bit5

bit4

SIG

bit3

bit2

A2S2

DOS2

MTOF1

NF2

bit1

A2S3

DOS3

MTOF2

TH1

00'H

01'H

02'H

A1S1

A1S2

A1S3

A2S1

DOS1

BUSMT1 BUSMT2 AMUTE

MTOF0

NF1

MTOF3

TH2

03'H

WR

OTSTP1 OTSTP2 OTSTP3 OTSTP4

04'H

DASLC

C1SL

LRSL

IIS

BLFS

C2

FPCC

C10

FPCB

XPRT

NR

(TEST1)

DOMU

05'H

06'H

07'H

00'H

(TSB0)

RGOF1

CC1

(TSB1)

RGOF2

CC2

XEOFF

RGOF3

CC3

XINH

RGOF4

CC4

PI1

PI2

OTSL

CC5

MFRAM (TEST2) (TEST3)

CC6

CC14

RG82

CC7

CC15

RG83

CC8

CC16

RG84

RD

01'H

02'H

CC9

CC10

(L)

CC11

(L)

CC12

(L)

CC13

RG81

(L)

Blanks

( )

: Data not related to internal logic.

: Data for testing. Fix to the default value.

: Low is output.

(L)

MSB, LSB : Data is transmitted with MSB first.

Default data (default value of internal register after master reset)

MSB

bit7

0

Data

LSB

bit0

—

1

Sub-

address

W

bit6

1

bit5

0

bit4

—

0

bit3

0

bit2

1

bit1

0

00'H

01'H

02'H

03'H

04'H

05'H

06'H

07'H

—

0

—

0

—

1

0

1

0

1

0

1

0

1

WR

0

1

0

1

(0)

0

—

(0)

1

—

(0)

1

—

1

—

0

1

0

—

(0)

1

0

(0)

( ) : Always fix to the default value.

– 24 –

CXD2027Q/R

• BUS setting values for audio output selection

Sub-address

00'H

00000000'B

BIT No.

bit7

Name

A1S1

A1S2

A1S3

A2S1

A2S2

A2S3

Description

bit6

Audio output mode selection when using built-in DF/DAC

Audio output mode selection when using external DF/DAC

bit5

bit3

bit2

bit1

A1S1

A1S2

A1S3

Applications

A2S1

A2S2

A2S3

DOS1

DOS2

DOS3

TV

0

1

X

0

1

X

0

1

X

1

0

1

0

1

0

X

0

A mode

B mode

stereo

independent

main + sub

main

TV

sub

1

A mode

main + sub

main

X

0

independent

2ch mono

sub

1

main + sub

main

X

0

B mode

sub

1

TV

main

X

A mode

independent

1ch mono

main

B mode

Sub-address

01'H

00000001'B

BIT No.

bit3

Name

DOS1

DOS2

DOS3

Description

bit2

Output mode selection when using digital interface

bit1

Same setting method as for A1S1, A1S2 and A1S3

– 25 –

CXD2027Q/R

• Muting-related BUS setting values

Sub-address

BIT No.

bit7

02'H

00000010'B

Name

Description

H

L

BUSMT1 Audio data mute when using built-in DF/DAC

BUSMT2 Audio data mute when using external DF/DAC

ON

OFF

bit6

bit3

MTOF0

MTOF1

MTOF2

MTOF3

Carrier detection mute

bit2

Non-broadcast flag mute

Error occurrence frequency mute

External mute (EXMU)

bit1

bit0

Sub-address

BIT No.

bit7

03'H

Name

00000011'B

Description

H

L

Non-

operation

OTSTP1

Signal suppression for external DF/DAC (AUD, LRCK, BCLK)

Operation

Signal suppression for external descramble

(CK2M, FRAM, DATO)

Non-

operation

bit6

bit5

bit4

OTSTP2

OTSTP3

OTSTP4

Operation

Non-

operation

Control sign output suppression (NSYN, CCUP, CC1)

Built-in DF/DAC operation / non-operation selection

Non-

operation

bit3

bit2

bit1

bit0

NF1

NF2

TH1

TH2

Error occurrence frequency mute setting (number of frames)

Error occurrence frequency mute setting (threshold value)

bit3

NF1

0

bit2

NF2

0

Number of frames

128

256

0

1

0

512

1

1024

Threshold value

bit1

TH1

0

bit0

TH2

0

1

2

MUTE

1/2

Cancel

1/4

1/8

0

1

1/8

1/16

1/32

1

0

1/16

1

MUTE when over this value

2

MUTE cancel when below this value

– 26 –

CXD2027Q/R

• BUS setting values for chargeable flag mute

Sub-address

07'H

00000111'B

BIT No.

bit7

Name

RGOF1

RGOF2

RGOF3

RGOF4

MFRAM

TEST2

TEST3

Description

H

L

Audio 1ch mute

Audio 2ch mute

Audio 3ch mute

Audio 4ch mute

ON

OFF

ON

bit6

bit5

bit4

bit2

Master frame sync processing

For testing (fix to low)

bit1

bit0

For testing (fix to low)

• BUS setting values for external I/F, etc.

Sub-address

02'H

00000010'B

BIT No.

bit4

Name

Description

Signal polarity selection for external descramble I/F

H

L

SIG

Inverted Positive

Corresponding input pins : BITI, DATA, DATB

Corresponding output pins : CK2M, DATO, FRAM

– 27 –

CXD2027Q/R

Sub-address

04'H

00000100'B

BIT No.

bit7

Name

DASLC

C1SL

LRSL

IIS

Description

H

L

Refer to page 20.

Inverted Positive

External descramble I/F control

bit6

CC1 (control sign 1st bit) output polarity inversion

LRCK polarity inversion

bit5

bit4

Audio output format switching

bit3

BLFS

FPCC

FPCB

TEST1

bit2

Selection of the number of front protection for frame sync protection and master

frame syncprotection selection

bit1

For testing (fix to low)

bit0

bit4

IIS

1

bit3

Format

BLFS

1

0

1

0

Prohibited

2) IIS

1

0

3) 64fs

0

1) SONY

bit2

bit1

The number of frame sync

front protection

The number of master

frame sync front protection

FPCC

FPCB

1

0

1

0

1

0

3

5

7

9

7

9

11

Sub-address

07'H

00000111'B

BIT No.

bit3

Name

OTSL

Description

H

L

DTUP pin output signal switching

DED

CCUP

• Digital I/F BUS setting values

Sub-address

05'H

00000101'B

BIT No.

bit3

Name

Description

H

L

C2

Digital copy allowed/prohibited selection

Channel status 10th bit

Allowed

General

Prohibited

BS

bit2

C10

bit1

XPRT

DOMU

Parity inversion selection for digital interface Transmission error

Normal

OFF

bit0

Mute for digital interface (TX is DC low)

– 28 –

ON

CXD2027Q/R

• DF and D/A converter-related BUS setting values

Write register

Sub-address

06'H

00000110'B

BIT No.

bit7

Name

Description

H

L

TSB0

For testing (normally set to low regardless of input data)

bit6

TSB1

XEOFF

XINH

PI1

ON

OFF

bit5

Digital de-emphasis selection

DC dither selection

bit4

Inverted Positive

bit3

DC dither phase control Rch

DC dither phase control Lch

Modulation NR

bit2

PI2

ON

OFF

bit1

NR

• Control sign bit reading after integration correction

Sub-address

00'H

00010000'B

BIT No.

bit7

Name

Description

CC1

Control sign 1st bit

Control sign 2nd bit

Control sign 3rd bit

Control sign 4th bit

Control sign 5th bit

Control sign 6th bit

Control sign 7th bit

Control sign 8th bit

Mode selection

bit6

CC2

CC3

CC4

CC5

CC6

CC7

CC8

TV audio

bit5

bit4

Additional audio

bit3

bit2

Suppression backup

Broadcast identification

Expansion bit

bit1

bit0

Sub-address

01'H

00010001'B

BIT No.

bit7

Name

CC9

Description

Control sign 9th bit

Control sign 10th bit

Control sign 11th bit

Control sign 12th bit

Control sign 13th bit

Control sign 14th bit

Control sign 15th bit

Control sign 16th bit

bit6

CC10

CC11

CC12

CC13

CC14

CC15

CC16

Expansion bits

bit5

bit4

Video scramble existent/non-existent

—

bit3

bit2

Master frame sync flag H: asynchronous, L: synchronous

Data suppression

bit1

bit0

Audio output suppression

– 29 –

CXD2027Q/R

• Range 8th bit read after integration correction

Sub-address

02'H

00010010'B

BIT No.

bit7

Name

—

Description

bit6

—

Low level fixed output

bit5

—

bit4

—

bit3

RG81

Range 8th bit (chargeable flag) 1ch

Range 8th bit (chargeable flag) 2ch

Range 8th bit (chargeable flag) 3ch

Range 8th bit (chargeable flag) 4ch

bit2

RG82

RG83

RG84

bit1

bit0

– 30 –

CXD2027Q/R

N C 8

T S T 6

A U D

L R C K

B C L K

F 2 5 6

D T U P

N S Y N

D D V

S D A

S C L K

S S V

T S T 8

M U T E

^{S S}V

M C K O

M D K I

P H A B

D D V

N C 9

N C 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

9

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

4 9

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

T S T 5

T S T 4

T S T 3

T S T 2

T X

C C 1

D A T O

F R A M

C K 2 M

3

7

8

0

D D V

D A T A

D A T B

D S L A

D S L B

B I T I

8

7

6

5

B I T O

S S V

M R S T

N C 0

4

3

4

2

1

– 31 –

CXD2027Q/R

Package Outline

CXD2027Q

Unit: mm

64PIN QFP(PLASTIC)

23.9 ± 0.4

+ 0.1

0.15 – 0.05

+ 0.4

20.0 – 0.1

0.15

51

33

52

32

20

64

+ 0.2

0.1 – 0.05

1

19

+ 0.35

2.75 – 0.15

+ 0.15

0.4 – 0.1

1.0

M

± 0.12

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

EPOXY RESIN

SOLDER/PALLADIUM

PLATING

SONY CODE

EIAJ CODE

QFP–64P–L01

LEAD MATERIAL

COPPER /42 ALLOY

QFP064–P–1420

1.5g

JEDEC CODE

PACKAGE WEIGHT

CXD2027R

80PIN LQFP (PLASTIC)

14.0 ± 0.2

12.0 ± 0.1

60

41

40

61

A

21

(0.22)

80

1

20

+ 0.05

0.1

+ 0.08

0.18 – 0.03

0.127 – 0.02

0.5 ± 0.08

+ 0.2

1.5 – 0.1

0.1 ± 0.1

0° to 10°

NOTE: Dimension “ ” does not include mold protrusion.

PACKAGE STRUCTURE

DETAIL A

PACKAGE MATERIAL

LEAD TREATMENT

EPOXY / PHENOL RESIN

SOLDER PLATING

SONY CODE

EIAJ CODE

LQFP-80P-L01

LEAD MATERIAL

QFP080-P-1212-A

42 ALLOY

0.5g

JEDEC CODE

PACKAGE WEIGHT

– 32 –


型号：	CXD2027Q
厂家：	SONY CORPORATION
描述：	DBS Audio Signal Processor DBS音频信号处理器商用集成电路
文件：	总32页 (文件大小：464K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD2027Q [SONY]

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