CXD2043 [SONY]
Digital Comb Filter (NTSC); 数码梳状滤波器（ NTSC ）
| 型号： | CXD2043 |
| 厂家： | 
SONY CORPORATION |
| 描述： | Digital Comb Filter (NTSC) |
| 文件： | 总11页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2043Q
Digital Comb Filter (NTSC)
For the availability of this product, please contact the sales office.
Description
80 pin QFP (Plastic)
The CXD2043Q is an adaptive comb filter compatible
with NTSC system, and can provide high-precision Y/C
separation with a single-chip.
Features
• Y/C separation by adaptive processing
• Horizontal aperture compensation circuit
• 8-bit A/D converter (1-channel)
• 8-bit D/A converter (2-channel)
• Two 1H delay lines
Recommended Operating Conditions
• 4-PLL
• Supply voltage DVDD
5.0 ± 0.25
5.0 ± 0.25
5.0 ± 0.25
5.0 ± 0.25
V
V
V
V
YVDD
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
CVDD
• Supply voltage DVDD
VSS – 0.5 to +7.0
VSS – 0.5 to +7.0
V
V
V
V
V
V
PVDD
• Operating temperature
Topr
YVDD
CVDD
PVDD
VSS – 0.5 to +7.0
–20 to +75
°C
VSS – 0.5 to +7.0
• Input voltage
VI
VSS – 0.5 to VDD + 0.5
VSS – 0.5 to VDD + 0.5
Structure
• Output voltage VO
• Operating temperature
Topr
Silicon gate CMOS IC
–20 to +75
°C
°C
Applications
• Storage temperature
Tstg
Y/C separation for color TVs and VCRs
–55 to +150
Block Diagram
DL
A/D
ADIN 27
1HDL
1HDL
DAC
DAC
AYO
31
43
to
BPF
BPF
BPF
48
Y8 to Y1
71
VI8 to VI1 to
78
·
51
·
52
Adaptive
Filter
Operation
ACO
41
54
to
61
C8 to C1
Logic Operation
Phase Comparison
VCO
4FSC
1/4
9
10
12
FIN
CPO VCV
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95812-ST
CXD2043Q
Pin Configuration
64 63 62 61 60
59 58 57 56 55 54 53 52 51 50 49 48
47
46 45 44 43 42 41
65
66
67
68
69
70
71
72
73
74
75
DVSS
DVDD
TEST
TEST
TEST
BPF
VI8
40 CVDD
39 CVG
38 CVRF
37
CIRF
36 VB
35
YIRF
34 YVRF
33
32
31
30
29
28
27
26
25
VI7
YVG
YVDD
AYO
YVSS
RT
VI6
VI5
VI4
VI3 76
77
78
79
80
VI2
VI1
AAVD
ADIN
AAVS
RB
ADCO
INSL
1
2
3
4
5
6
7
8
9
10 11 12
13
14 15 16 17
18 19
20 21 22 23 24
Pin Description
Pin
Symbol
No.
I/O
I
Description
Clock amplifier input.
1
OCLK
Input at 0.8Vp-p or more by eliminating DC components with a capacitor.
2
3
DVSS
DVDD
—
—
Digital ground
Digital power supply
Clock amplifier output.
Left open when the clock amplifier is not used.
4
CLKO
O
5
6
7
8
MCK
ADCK
CK4
I
I
Master clock input
Clock input for A/D converter. Input the same clock signal as for Pin 5.
4FSC clock output. Generated from the built-in 4-PLL.
Test. Fix to Low.
O
I
TEST
FSC clock input. Input FSC which is burst-locked.
Connect to DVss when the PLL is not used.
9
FIN
I
Phase comparison output for the built-in PLL.
Left open when the PLL is not used.
10 CPO
11
O
PVSS
—
PLL analog ground
– 2 –
CXD2043Q
Pin
No.
Symbol
I/O
I
Description
Control voltage input for the built-in VCO oscillation.
Connect to PVss when the PLL is not used.
12 VCV
13 TEST
14 TEST
I
I
Test. Fix to Low.
Test. Fix to Low.
Built-in VCO oscillation enable. Connect to PVDD when using the PLL.
Connect to PVss when the PLL is not used.
15 VCEN
16 TEST
I
O
Test. Left open.
17
PVDD
—
PLL analog power supply
Clamp pulse input for A/D converter (negative polarity).
Connect to DVDD when the clamp is off.
18 CLPI
I
I
High: Clamp function is set to off, and only the normal A/D converter function is enabled.
Low: Clamp function is enabled.
19 CPON
20 ADVD
21 ADVS
22 ICP
—
—
I
Digital power supply for A/D converter
Digital ground for A/D converter
Clamp control voltage
23 CRV
24 GR
I
Clamp reference voltage input
—
O
—
I
Connect to analog ground.
25 RB
A/D converter reference voltage (bottom)
Analog ground for A/D converter
26 AAVS
27 ADIN
28 AAVD
29 RT
Comb filter analog input (A/D converter input)
Analog power supply for A/D converter
A/D converter reference voltage (top)
—
O
—
O
—
O
I
30 YVSS
31 AYO
32 YVDD
33 YVG
34 YVRF
35 YIRF
36 VB
Analog ground for Y-D/A converter
Analog luminance signal output
Analog power supply for Y-D/A converter
Connect to YVDD via a capacitor of approximately 0.1µF.
VRF for Y. Sets the output full-scale value for Y.
Connect a resistor of 16 times (16R) that of the output resistor "R" of AYO pin.
Connect to YVss via a capacitor of approximately 0.1µF.
Connect a resistor of 16 times (16R) that of the output resistor "R" of ACO pin.
VRF for C. Sets the output full-scale value for C.
Connect to CVDD via a capacitor of approximately 0.1µF.
Analog power supply for C-D/A converter
Analog chroma signal output
I
O
O
I
37 CIRF
38 CVRF
39 CVG
40 CVDD
41 ACO
42 CVSS
43 Y8
O
—
O
—
O
O
O
Analog ground for C-D/A converter
Digital luminance signal output (MSB)
Digital luminance signal output
44 Y7
45 Y6
Digital luminance signal output
– 3 –
CXD2043Q
Pin
No.
Symbol
I/O
Description
46 Y5
47 Y4
48 Y3
O
O
Digital luminance signal output
Digital luminance signal output
Digital luminance signal output
Digital ground
O
49
50
DVSS
DVDD
—
—
O
Digital power supply
51 Y2
52 Y1
Digital luminance signal output
O
Digital luminance signal output (LSB)
Digital luminance signal output control
High: High impedance
53 XYOE
I
Low: Standard output
54 C8
55 C7
56 C6
57 C5
58 C4
59 C3
60 C2
61 C1
O
O
O
O
O
O
O
O
Digital chroma signal output (MSB)
Digital chroma signal output
Digital chroma signal output
Digital chroma signal output
Digital chroma signal output
Digital chroma signal output
Digital chroma signal output
Digital chroma signal output (LSB)
Digital chroma signal output control.
High: High impedance
Low: Standard output
62 XCOE
63 APCN
I
I
Aperture compensation switching.
High: Aperture compensation ON
Low: Aperture compensation OFF
Y output through mode.
High: Outputs the input composite video signal from the Y output. At this time,
there is 1H + 18 clock delay from the input.
64 TST
I
Low: Y/C separation mode
65
66
DVSS
DVDD
—
—
I
Digital ground
Digital power supply
Test. Fix to Low.
Test. Fix to Low.
Test. Fix to Low.
67 TEST
68 TEST
69 TEST
I
I
High: Fixed to BPF separation
Low: Standard mode
70 BPF
I
71 VI8
72 VI7
73 VI6
74 VI5
75 VI4
76 VI3
I
I
I
I
I
I
Digital composite video input (MSB)
Digital composite video input
Digital composite video input
Digital composite video input
Digital composite video input
Digital composite video input
– 4 –
CXD2043Q
Pin
No.
Symbol
I/O
Description
77 VI2
78 VI1
I
I
Digital composite video input
Digital composite video input (LSB)
High: Video signals taken in form A/D converter are output from the Y output pins
(Y8 to Y1) as 8-bit digital data with a 3.5 clock delay.
Low: Normal mode
79 ADCO
80 INSL
I
I
Input switching.
High: Digital input
Low: Analog input.
– 5 –
CXD2043Q
Electrical Characteristics
DC Characteristics
(VDD = 5 ± 0.25V, VSS = 0V, Ta = –20 to +75°C)
Item
Symbol
DVDD
AAVD
ADVD
YVDD
CVDD
Topr
Conditions
Min.
Typ.
Max.
Unit
4.75
5.0
5.25
V
Supply voltage
—
—
–20
—
—
—
—
—
+75
80
°C
mA
V
Operating temperature
Supply current
IDD
Clock 14MHz
VDD × 0.7
VSS
VDD
VIH
High level input voltage
Low level input voltage
CMOS level
VDD × 0.3
V
VIL
CMOS level
IOH = –2mA
VDD – 0.8
VSS
—
—
VDD
VOH
VOL
High level output voltage
Low level output voltage
IOH = –4mA (Pins 4, 7)
IOL = 4mA
V
0.4
IOL = 8mA (Pins 4, 7)
—
0.8
VDD/2
—
—
V
Vp-p
Ω
LVth
VIN
Logical Vth
VDD
2.5M
Input voltage
Feedback resistor
OCLK (Pin 1)
250k
1M
RFB
AC Characteristics
(VDD = 5 ± 0.25V, VSS = 0V, Ta = –20 to +75°C, CL = 20pF)
Item
Data setup time
Data hold time
Symbol
tdsu
Conditions
MCK → VI [8 : 1]
Min.
15.0
10.0
Typ.
—
Max.
—
Unit
ns
MCK → VI [8 : 1]
—
—
ns
tdh
MCK → Y [A : 1]
MCK → C [A : 1]
Propagation delay time
Clock frequency
—
—
40
15
ns
tpd
f
—
14
4fsc
MHz
Pin Capacitance
(Ta = 25°C, f = 1MHz, VIN = VOUT = 0V)
Item
Symbol
CIN
Conditions
Min.
—
Typ.
—
Max.
9
Unit
pF
Input capacitance
Output capacitance
—
—
—
—
11
pF
COUT
– 6 –
CXD2043Q
ADC Characteristics
(VDD = 5V, Ta = 25°C, f = 10MHz)
Item
Resolution
Symbol
Conditions
Min.
—
Typ.
8
Max.
—
Unit
bit
n
Max. conversion speed
Analog input band width
fmax
BW
14.3
—
—
—
MSPS
MHz
V
–3dB
18
—
VRB
VRT – VRB
tpd
0.48
1.96
—
0.52
2.08
—
0.56
2.22
45
Self bias
V
Propagation delay time
Differential linearity error
Integral linearity error
ns
ED
–1.0
–3.0
–20
–30
—
+1.0
+3.0
+20
+10
LSB
LSB
mV
mV
EL
—
VREF = VRB
VREF = VRT
0
Clamp offset voltage
EOC
–10
DAC Characteristics
(VDD = 5V, VRF = 2V, IRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz)
Item
Resolution
Symbol
Conditions
Min.
—
Typ.
8
Max.
—
Unit
bit
n
—
—
—
—
—
—
—
Max. conversion speed
Differential linearity error
Integral linearity error
Output full-scale voltage
Output full-scale current
Output offset voltage
fmax
ED
14.3
–0.5
–1.5
1.805
—
—
—
MSPS
LSB
LSB
V
—
+0.5
+1.5
1.995
15
EL
—
VFS
IFS
1.90
9.5
—
mA
VOS
—
1.0
mV
Precision guaranteed output voltage
range
VOC
GE
—
1.8
—
—
2.1
—
V
1
Glitch energy
30
pV-s
1
R = 75Ω, 1Vp-p output
– 7 –
CXD2043Q
Application Circuit for A/D Converter
(1) In the case of input clamp pulse directly.
RT
Clamp Pulse
ADC Clock
0.01µ
29
27
25
CLPI 18
ADC Input
75
CPON
ADCK
ADIN
RB
19
6
10p
47µ
20k
0.01µ
23 CRV
ICP
GR
22
24
0.01µ
28 AAVD
0.1µ
26
ADVD 20
ADVS 21
0.1µ
AAVS
(2) In the case of not using the internal clamp circuit
RT
0.01µ
29
27
CLPI
CPON
ADCK
18
19
6
ADC Input
75
ADIN
10p
25 RB
ADC Clock
0.01µ
CRV
23
22
ICP
GR
24
28
AAVD
ADVD
ADVS
20
21
0.1µ
0.1µ
26
AAVS
– 8 –
CXD2043Q
Application Circuit for D/A Converter
Y OUTPUT
AYO
31
200 (R)
0.1µ
YVDD
YVSS
32
30
0.1µ
YVG 33
1k
YVRF
34
CLOCK
5
MCK
DVDD
DVSS
YIRF 35
VB 36
3.3k (R')
0.1µ
C OUTPUT
ACO
41
200 (R)
0.1µ
0.1µ
CVDD
CVSS
40
42
CVG
39
1k
CVRF 38
CIRF 37
3.3k (R')
• Method of Selecting Output Resistance
The CXD2043Q has a built-in current output-type D/A converter. To obtain the output voltages, connect
resistances to AYO and ACO pins.
The voltage and current specifications are:
Output full-scale voltage: VFS = 0.5 to 2.0V
Output full-scale current: IFS = 0 to 15mA
Calculate the output resistance using the relationship VFS = IFS × R. In addition, connect a resistance of 16
times the output resistance to the reference current pin (YIRF, CIRF). In the case where the value comes to
be impractical, use a value of resistance as close to the value calculated as possible.
Note that, at this time, VFS = VRF × 16R/R' (VRF: Pin voltage of YVRF and CVRF).
R is the resistance connected to AYO/ACO, and R' is the resistance connected to YIRF/CIRF. Power
consumption can be reduced by using higher resistance values, but then glitch energy and data settling time
increase contrastingly. Select optimum resistance values according to the system applications.
• VDD, VSS
Separate the analog and digital systems around the device to reduce noise effect. YVDD and CVDD are
respectively by-passed to YVSS and CVSS as close to each other as possible through ceramic capacitor of
approximately 0.1µF.
– 9 –
CXD2043Q
O C A
S S V C
8 Y
R G
V R C
P C I
7 Y
S V D A
D V D A
N O P C
I P L C
D D V P
T S E T
N E C V
T S E T
T S E T
V C V
6 Y
5 Y
4 Y
3 Y
S S V D
D D V D
2 Y
1 Y
E O Y X
8 C
S S V P
O P C
7 C
6 C
N I F
5 C
T S E T
4 K C
4 C
3 C
K C D A
K C M
O K L C
D D V D
S S V D
K L C O
2 C
1 C
E O C X
N C P A
T S T
– 10 –
CXD2043Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
0.15
64
41
65
40
A
+ 0.2
0.1 – 0.05
80
25
1
24
+ 0.15
+ 0.35
2.75 – 0.15
0.8
0.35 – 0.1
M
0.2
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
EIAJ CODE
QFP-80P-L01
QFP080-P-1420
42/COPPER ALLOY
1.6g
JEDEC CODE
PACKAGE MASS
– 11 –
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