CXD1961Q_技术文档

CXD1961Q

DVB-S Front-end IC (QPSK demodulator + FEC)

Preliminary

For the availability of this product, please contact the sales office.

Description

100 pin QFP (Plastic)

The CXD1961Q is a single chip DVB Satellite

Broadcasting Front-end IC, including dual ADC for

analog I/O inputs, QPSK demodulator, Viterbi

decoder, de-interleaver, Reed-Solomon decoder

and Energy Dispersal descrambler.

It is suitable for use in a DVB Integrated Receiver

Decoder.

Features

Absolute Maximum Ratings (Ta=25°C, GND=0V)

• Dual 6 bit A/D converters

• Supply voltage

• Input voltage

• Output voltage

• I/O voltage

VDD

VIN

–0.5 to 4.6

V

• QPSKdemodulator

–0.5 to VDD+0.5

Multi-symbol rate operation

Nyquist roll off filter (α = 0.35)

Clock recovery circuit

VOUT –0.5 to VDD+0.5

V

VI/O

–0.5 to VDD+0.5

–0.5 to 5.5

0 to +75

V

• CPU I/F pin

V^CPUIF

V

Carrier recovery circuit

• Operating temperature Topr

• Storage temperature Tstg

°C

AGC control circuit

–55 to +150 °C

• Viterbi decoder

Constraint length K =7

DC Recommended Operating Conditions

Punctured rate R = 1/2 –7/8

Truncation length 144

(Ta=0°C to 75°C, GND=0 V)

• Supply voltage

• Input Hi-level

• Input Lo-level

VDD

3.15 to 3.45

VIH VDD–0.7 to VDD+0.5V

0.3 to VDD +0.2

V

Punctured rate search function

BER monitor

VIL

V

• De-interleaver

Packet synchronization

Convolutional de-interleaver

• Reed-Solomon decoder (204, 188)

• Energy dispersal descrambler

• CPU interface

l²C bus interface/8 bit CPU bus

TTL interface level (5V input capability)

• JTAG(IEEE std 1149.1–1990) test mode

• Package : QFP-100pin

• Single +3.3V Power Supply

• Symbol rate max:32MSPS min:TBD

• Power consumption TBD

• 0.4um CMOS Technology

Applications

• DVB-S Set Top Box (Satellite)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

—1—

PE96417-TE

CXD1961Q

Block Diagram

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

Analog I/Q

Sampling

Clock

VCO

2ch ADC

PLL

QPSK

Demodulator

Digital

Filter

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

NCO

Viterbi Decoder

De-interleaver

Reed-Solomon

Decoder

CPU I/F

l²C

bus

Energy Dispersal

8bit CPU bus

Decoded

data & clock

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Typical Application Block Diagram

QPSK+FEC

I/Q

Detector

Amp

Data

LNB

SAW

LPF

SONY

CXD1961Q

Clock

PLL

VCO

Crystal

90°

LPF

Reference

OSC

Micro Controller

—2—

CXD1961Q

Pin Configuration

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

80

79

78

77

76

75

74

72

73

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

AVS0 1

RB0 2

VDD10

CR7

CR6

CR5

CR4

VSS9

VDD9

CR3

CR2

CR1

CR0

CKV

3

4

VDD0

VSS0

CPUSEL 5

PLLSEL 6

TEST1 7

8

TEST2

TEST3

VDD1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VSS1

SDATA

SCLK

SEN

AGCPWM

VSS8

VDD8

TEST5

TEST4

XI

VDD2

VSS2

TCK

TMS

TDO

XO

TDI

VSS7

VDD7

SDA

CK8OUT

RESET

TE

SCL

VDD3

ADD3

ADD2

ADD1

VSS6

VDD6

ADD0

CS

VSS3

PKTCLK

BYTCLK

PKTERR

DATA0

DATA1

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

—3—

CXD1961Q

Pin Description

No.

1

Symbol

AVS0

RB0

I/O

—

I

Description

Analog Ground

2

ADC0 bottom reference voltage

Digital Power Supply (+3.3 V)

Digital Ground

CPU interface select (L : I²C bus)

Connect Digital Ground

Test input (connect Digital Ground)

Digital Power Supply (+3.3 V)

Digital Ground

3

VDD0

4

VSS0

5

CPUSEL

PLLSEL

TEST1–3

VDD1

6

I

7–9

10

I

—

O

—

I

11

VSS1

12

SDATA

SCLK

SEN

SONY internal use

13

SONY internal use

14

SONY internal use

15

VDD2

Digital Power Supply (+3.3 V)

Digital Ground

16

VSS2

17

TCK

JTAG test clock

18

TMS

I

JTAG test mode select

JTAG test data output

JTAG test data input

19

TDO

O

I

20

TDI

21

CK8OUT

RESET

TE

O

I

Divide by 8 clock of Crystal clock

Reset input (L : reset)

Test Enable (H : test enable)

Digital Power Supply (+3.3 V)

Digital Ground

22

23

I

24

V^DD3

—

O

—

O

25

VSS3

26

PKTCLK

BYTCLK

PKTERR

DATA0–4

VDD4

R/S Packet clock

27

R/S Byte clock

28

R/S uncorrectable Packet flag

R/S data output (DATA0 : LSB)

Digital Power Supply (+3.3 V)

Digital Ground

29–33

34

35

VSS4

36–38

39–43

44

DATA5–7

D0–D4

VDD5

R/S data output (DATA7 : MSB)

I/O 8 bit CPU bus data I/O (D0 : LSB)

—

Digital Power Supply (+3.3 V)

Digital Ground

45

VSS5

46–48

49

D5–D7

RW

I/O 8 bit CPU bus data I/O (D7 : MSB)

I

8 bit CPU bus Read/Write (H : Read)

8 bit CPU bus Data strobe

8 bit CPU bus Chip Select

8 bit CPU bus Address0 (LSB)

Digital Power Supply (+3.3 V)

Digital Ground

50

DS

51

CS

I

52

ADD0

I

53

VDD6

—

54

VSS6

—4—

CXD1961Q

No.

55–57

58

Symbol

ADD1–3

SCL

I/O

Description

8 bit CPU bus Address1–3 (ADD3 : MSB)

I²C bus serial clock

I

59

SDA

I/O I²C bus serial data

60

VDD7

—

O

I

Digital Power Supply (+3.3 V)

Digital Ground

61

VSS7

62

XO

Oscillator output (for Crystal)

Oscillator input (for Crystal)

Test output (VSS level)

63

XI

64, 65

66

TEST4, 5

VDD8

O

—

O

—

O

—

O

—

O

—

I

Digital Power Supply (+3.3 V)

Digital Ground

67

VSS8

68

AGCPWM

CKV

PWM output for AGC

69

Sampling Clock monitor output

Clock Recovery data 0–3 (CR0 : LSB)

Digital Power Supply (+3.3 V)

Digital Ground

70–73

74

CR0–3

VDD9

75

VSS9

76–79

80

CR4–7

V^DD10

VSS10

TEST6, 7

VDD11

VSS11

CPOUT

AVD2

VCOC

OPXIN

OPOUT

AVS2

VCOEN

RT1

Clock Recovery data 4–7 (CR7 : MSB)

Digital Power Supply (+3.3 V)

Digital Ground

81

82, 83

84

Test output (VSS level)

Digital Power Supply (+3.3 V)

Digital Ground

85

86

PLL Charge pump output

Analog Power Supply (+3.3 V)

VCO control voltage input

Embedded OP-Amp Negative input

Embedded OP-Amp output

Analog Ground

87

88

89

I

90

O

—

I

91

92

VCO enable (H : enable)

ADC1 top reference voltage

Analog Power Supply (+3.3 V)

Analog Q input (ADC1 input)

Analog Ground

93

—

I

94

AVD1

QIN

95

96

AVS1

RB1

—

I

97

ADC1 bottom reference voltage

ADC0 top reference voltage

Analog Power Supply (+3.3 V)

Analog input (ADC0 input)

98

RT0

99

AVD0

IIN

100

Note)

Apply 0.1 µF capacitor to every power supply terminal.

Apply 0.1µF capacitor to RB0, RT0, RB1, RT1 for stable A to D conversion.

—5—

CXD1961Q

CPU Interface Register

Sub

R/W

R

MSB 7

6

5

4

3

2

1

LSB 0

address

0

ADC_IN7 ADC_IN6 ADC_IN5 ADC_IN4 ADC_IN3 ADC_IN2 ADC_IN1 ADC_IN0

BECNT15 BECNT14 BECNT13 BECNT12 BECNT11 BECNT10 BECNT9 BECNT8

BECNT7 BECNT6 BECNT5 BECNT4 BECNT3 BECNT2 BECNT1 BECNT0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

R

QSYNC

AGC7

VS_N4

QS_N3

AK2

AFC3

AGC6

VS_N3

QS_N2

AK1

AFC2

AGC5

AFC1

AGC4

AFC0

AGC3

VS_N0

AC2

VSYNC

AGC2

RATE2

AC1

RSYNC BEM_END

W

AGC1

RATE1

BC2

AGC0

RATE0

BC1

VS_N2

QS_N1

VS_N1

QS_N0

S_INV AGC_INV AGC_MOD TIMER2 TIMER1 TIMER0

PLL_CTL MON_SW VS_T3

DF_SKIP DOUT_INV RS_SKIP

VS_T2

VS_T1

VS_T0 CE_LEV1 CE_LEV0

SSEL AFC_MOD BER_T2 BER_T1 BER_T0

SFD18

SFD10

SFD2

SFD17

SFD9

SFD16

SFD8

SFD15

SFD7

SFD14

SFD6

SFD13

SFD5

SFD12

SFD4

SFD11

SFD3

SFD1

SFD0

PCD2

NC020

NC012

NC04

PCD1

NC019

NC011

NC03

PCD0

NC018

NC010

NC02

REF_SEL REF_LSB

NC023

NC015

NC07

NC022

NC014

NC06

NC021

NC013

NC05

NC017

NC09

NC01

NC016

NC08

NC00

F

Note)

1. Above Registers are shared by I²C bus interface and 8 bit CPU bus interface.

2. To select CPU interface, use CPUSEL (Pin 5) ; H : 8 bit CPU bus / L : I²C bus.

3. I²C bus interface slave address;

MSB 6

1

5

1

4

0

3

1

2

1

LSB 0

0

R/W

Write mode : DC (Hex)

Read mode : DD (Hex)

—6—

CXD1961Q

CPU Interface Register Brief Explanation

ADD 0

ADC_IN (7 : 0)

BECNT (15 : 0)

QSYNC

ADC input level (I²+Q²at QPSK demodulator)

Bit Error Count at QPSK demodulator output

QPSK Synchronization Flag (H : in sync.)

Auto Frequency Control data

ADD 1, 2

ADD 3

AFC (3 : 0)

VSYNC

Viterbi dec. Synchronization Flag (H : in sync)

Reed-Solomon dec. Synchronization Flag (H : in sync)

Bit Error Monitor enable Flag (H : enable)

(when AGC mode is H) AGC Gain control data

(when AGC mode is L) Reference data for self AGC

V sync threshold Bit Error Count (see Fig. 1)

Punctured rate (see Fig. 2)

RSYNC

BEM_END

AGC (7 : 0)

ADD 4

ADD 5

ADD 6

ADD 7

VS_N (4 : 0)

RATE (2 : 0)

QS_N (3 : 0)

Threshold data for QPSK sync. judgement (see Fig. 3)

AC (2 : 1), BC (2 : 1) Parameter for Carrier recovery loop filter (see Fig. 4)

AK (2 : 1)

S_INV

Parameter for Clock recovery loop filter (see Fig. 4)

I/Q exchange (H : enable)

AGC_INV

AGC_MOD

TIMER (2 : 0)

PLL_CTL

MON_SW

VS_T (3 : 0)

CE_LEV (1 : 0)

DF_SKIP

AGC control voltage polarity (H : positive)

H : controlled by CPU (slave) L : self AGC mode (master)

Timer for AGC master mode (see Fig. 5)

For SONY internal use (input 0 for norma use)

Monitor period for Viterbi sync. (see Fig. 6)

Clock recovery Error feed back level (see Fig. 7)

Digital Filter skip mode (H : enable)

ADD 8

ADD 9

DOUT_INV

RS_SKIP

SSEL

Data output timing invert (H : falling edge)

R/S decode skip mode (H : enable)

For SONY internal use (input 0 for normal use)

Monitor period for Bit error Count (see Fig. 8)

For SONY internal use (input 0 for normal use)

Sampling Frequency 2*Fs=NC0 (0 : 23)*8*Fxtal/2²⁴

(Fxtal=Crystal Frequency)

AFC_MOD

BER_T (2 : 0)

HS_PLL

ADD A

ADD A, B, C SFD (17 : 11)

ADD C

PCD (2 : 0)

REF_SEL

REF_LSB

ADD D, E, F NC0 (23 : 0)

Fig. 1 V sync threshold (Error Counter Preset data)

max. : 992

min. : 32

Register

Limit

VS_N4

×2⁹

VS_N3

×2⁸

VS_N2

×2⁷

VS_N1

×2⁶

VS_N0

×2⁵

(ex. VS_N (4 : 0)=(1, 1, 0, 0, 1) Limit=0×2⁹+0×2⁸+1×2⁷+1×2⁶+0×2⁵=192)

Fig. 2 Punctured Rate

Punc. rate

RATE2

1/2

0

2/3

0

3/4

0

4/5

1

5/6

1

6/7

1

7/8

1

Auto

0

RATE1

0

1

0

1

RATE0

1

0

1

0

1

0

1

—7—

CXD1961Q

Fig. 3 QPSK Synchronization monitor

QSYNC Threshold

(QS_N3)×2⁷+(QS_N2)×2⁶+(QS_N1)×2⁵+(QS_N0)×2⁴

256 (fix)

QSYNC Monitor Period

Fig. 4 Costas Loop Filter co-efficiency

Parameter

(AC2, AC1)

(0, 0)

×1

(0, 1)

1/2

(1, 0)

1/4

(1, 1) Item

1/8 Carrier recovery IIR filter

×8 Carrier recovery tracking range

1/8 Clock recovery IIR filter

(BC2, BC1)

(AK2, AK1)

×1

×2

×4

×1

1/2

1/4

Fig. 5 Timer period (Sampling Frequency = 60 MHz)

TIMER2

1

0

1

0

1

0

1

0

1

0

1

0

TIMER1

TIMER0

Period (ms)

140 70

35 17.5 8.75 4.38 2.19 1.09

Frequency (kHz) 7.14 14.3 28.6 57.1 114 229 457 914

Fig. 6 V sync monitor period (measurement period counter preset data)

Register

VS_T3 VS_T2 VS_T1 VS_T0

×2¹²×2¹¹×2¹⁰×2⁹

max. :6656

min. : 512

Period (viterbi clock)

(ex. VS_T (3:0)=(0, 1, 1, 1) → Limit=1×2¹²+0×2¹¹+0×2¹⁰+0×2⁹=4096)

(viterbi clock)

Fig. 7 Clock recovery error data (8 bit) feed back level

NCO

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CE_LEV

(1, 1)

(1, 0)

(0, 1)

(0, 0)

Fig. 8 Bit Error Monitor period (Viterbi clock)

BER_T2

BER_T1

BER_T0

Period

1

0

1

0

1

0

1

0

1

2¹⁹

0

2¹⁸

1

2¹⁷

0

2¹⁶

1

2¹⁵

0

2¹⁴

1

2¹³

0

2⁶

—8—

CXD1961Q

Functional Description

(1) CPU Interface

CXD1961Q has two CPU interface, an 8 bit CPU bus and an I²C bus interface. Fix CPUSEL (Pin 5) to DC L or

H level depending on the choice of bus.

CPUSEL=L : I²C bus / H : 8 bit bus

I²C bus Interface

The CXD1961Q's slave address is "1101110", and the read/write operation is based on Philips standard.

In write operation, the second byte is input as the sub-address of the start position. The 3rd byte then forms

the data to be written to the start register.

Successive data bytes are written to successive sub-address register.

S Slave

T Address 0 C Address

A 1101110 K Nhex

A Sub-

A

C

K

A

C

K

A

C

K

A S

C T

K P

Input data

for "N"

Input data

for "N+1"

• • •

STA : Start condition

ACK : Acknowledgment by CXD1961Q

STP : Stop Condition

Note)

Registers of Sub-Address 0hex to 3hex are read only

Before read operation, the sub-address of the start register to be read is input by using write operation, and

terminated by a stop condition.

Read operation then begins with the second byte which is the data of the start register. Data of successive

sub-address registers are read successively following by the second byte.

S Slave

A Sub-

A S

C T

K P

T Address 0 C Address

A 1101110

S Slave

K Nhex

A

C

K

A S

C T

K P

Output data

from "N"

Output data

T Address 1 C

C

K

• • •

from "N+1"

A 1101110

K

Note)

Registers of Sub-Address 4hex to Fhex are write only

—9—

CXD1961Q

8 bit CPU bus Interface

(Write cycle)

DS

RW

D [7:0]

Valid input

ADD [3:0 ]

CS

Valid Address

T1

T2

T3

T4

T5

T6

Timing

Description

Min (nsec) Max (nsec)

T2–T1

T3–T1

T3–T2

T4–T3

T5–T4

T6–T4

Note)

Address, CS to Data valid

R/W to DS

25

24

10

70

21

24

Data valid to DS

DS pulse width

Data hold time

Address, CS, R/W hold time

Registers of Address 0hex to 3 hex are read only

(Read cycle)

DS

RW

D [7:0]

Valid output

Valid Address

ADD [3:0]

CS

T1

T2

T3

T4

T5

T6

Timing

T2–T1

Description

Min (nsec) Max (nsec)

Address, CS, R/W to DS

DS to Data valid

24

T3–T2

T4–T2

T5–T4

T6–T4

Note)

75

24

DS pulse width

105

Data hold time

Address, CS, R/W hold time

24

Registers of Address 4hex to Fhex are write only

—10—

CXD1961Q

(2) Analog to Digital Converters

The Dual 6 bit A to D converters quantize the analog I/Q input data. The input range of the ADC's is

determined by external resistors. RT0 (RT1) is the top reference voltage, and RB0 (RB1) is the bottom

reference voltage. RT0 (RT1) and RB0 (RB1) are connected internally with a 320 Ω (Typical value) resistor.

In the example shown in the following figure, input range is approximately 1.1 V, and center voltage 1.65 V.

AVD (+3.3V)

CXD1961Q

330Ω

RT

RB

Top reference level

Input range

Bottom reference level

320Ω

330Ω

AVS (0V)

(3) AGC

Input signal level of the A to D Converter is estimated by calculating I²+Q²in 16 bit precision, and the upper

8 bits of the estimated data are sent via the CPU I/F as ADC_IN [7:0]. CXD1961Q has two AGC modes that

can be selected by AGC_MOD. In AGC slave mode, ADC_IN[7:0] is checked and an appropriate gain level

AGC[7:0] is returned by the micro controller. This value is converted into 8 bit PWM format and output from

AGCPWM (Pin 68).

In AGC master mode, reference level AGC[7:0] is set via the CPU I/F and compared to ADC_IN[7:0]

internally. The updated gain level is then output at the AGCPWM pin. In normal operation, ADC_IN[7:0]

becomes almost equal to reference level. In AGC master mode, AGC control interval is set by TIMER[2:0].

In both modes, AGCPWM output should be low pass filtered, and if needed, the level should be converted

to satisfy the AGC gain control range. Depending on AGC_INV, the polarity can be inverted. (H:positive /

L:negative)

CPU Register

ADC_IN [7 : 0]

→

A^DD0h

ADD 7h

AGC [7 : 0]

TIMER [2 : 0]

→

ADD 4h

ADD 7h

AGC_INV

→

ADD 7h

AGC_MOD

Reference level

Input signal level

ADC_IN [7 : 0]

to ADC input range ratio

0F

3F

7F

FF

0.25

0.5

0.7

1.0 or over range

Note)

ADC input range is subject to temperature and VDD level.

—11—

CXD1961Q

(4)Clock Recovery

Initial sampling clock frequency is set by a 24 bit word via the CPU I/F. This 24 bit word is written to the

NCO(Numerically Controlled Oscillator).

The sampling frequency is:

Fsample= 8*NCO [23:0]*Fxtal/2²⁴

where: NCO [23:0] is the parameter for sampling frequency, "8" is the divider gain of the PLL, Fxtal is the

reference crystal frequency, whose value should be more than 30MHz (32MHz is recommended).

The internal digital clock recovery loop feeds clock error data to the above NCO to provide sampling timing

correction .

AK [2:1] is the Loop Filter coefficient and CE_LEV [1:0] is the Loop Gain.

This value limits clock recovery range and resolution. (see the CPU Interface Register

Brief Explanation Fig.7)

Sampling clock is output from CKV (pin 69).

CPU I/F Register

AK [2:1] → A^DD7h

CE_LEV [1:0] → ADD 8h

NCO [23:0] → ADD D, E, Fh

(Example)

CE_LEV [1:0]=(0,1), NCO [23:0]=(001110000000000000000000), Fxtal=32 MHz

Sampling Frequency

= 8*(2²¹+2²⁰+2¹⁹)*32*10⁶/2²⁴

= 2³*7*10⁶= 56*10⁶

→

56 MHz

Clock recovery range

= 2⁹/(2²¹+2²⁰+2¹⁹)

= 1/2¹⁰/7 = 139.5..*10^–6

= 8*2¹*32*10⁶/2²⁴= 30.5. . .

→

±140 ppm

31 Hz

Clock recovery

resolution

(5)Carrier Recovery

The Analog I/Q inputs have a carrier offset frequency, which is not corrected by the tuner's PLL

Synthesizer. The offset is compensated by a Costas Loop, using a frequency multiplier, loop filter and the

NCO. AC [2:1] is the coefficient of the loop filter and BC [2:1] is the loop gain parameter. QPSK

synchronization(QSYNC) is determined by monitoring the output of loop filter. The internal sync detector

monitors 256 cycles, and checks the value with the threshold set by QS_N [3:0]. In QPSK synchronization,

AFC [3:0] indicates the offset proportional value which remains at that point. This value is the average data

of the loop filter output. If AFC3(=MSB) is high, tuner PLL has a negative offset to the carrier frequency ,

and vice versa if AFC3 is low. By feeding the AFC [3:0] to the tuner's PLL Synthesizer, carrier offset can be

corrected with the PLL step size.

CPU I/F Register

QSYNC,AFC [3:0] → ADD 3h

QS_N [3:0], AC [2:1], BC [2:1] → ADD 6h

—12—

CXD1961Q

(6)Viterbi decoder

By using QPSK demodulated data and Viterbi decoded data, the existence of errors is detected. Bit error

measured over a certain period is used to determine the correct punctured rate and phase synchronization

as well as bit error rate (BER). VS_N[4:0] is used to set the error count threshold, and VS_T[3:0] is used to

set the error count duration. (see Fig.1 and Fig. 6 of CPU Interface Register Brief Explanation)

For example)

VS_N[4:0]=(1, 1, 0, 0, 1)

VS_T[3:0] =(1, 0, 1, 1)

→ Error Count threshold =192

→ Error Count duration = 2048

In this case, bit error is checked for 2048 cycles. If the error count is less than 192, CXD1961Q judges that

punctured decoding is in sync and VSYNC goes high.

Punctured rate is set by RATE[2:0]. When a certain rate is set by RATE[2:0], only punctured phase search

is performed. Punctured rate and phase search is performed if RATE[2:0] is set to (0, 0, 0).

CXD1961Q has 2¹⁶(= 65536) bit counter for BER estimation. BER monitor period is set by BER_T[2:0]

(see Fig. 8), and the error count is read by CPU I/F as BECNT[15:0]. If BEM_END is low, punctured rate or

phase search is not finished and the error count is not reliable at that moment.

CPU I/F Register

BERCNT[15:0] → A^DD1, 2h

VS_N[4:0]

VSYNC

→ ADD 3h BEM_END

→

ADD 3h

ADD 9h

→ ADD 5h

VS_T[3:0] → ADD 8h BER_T[2:0]

(7) Packet synchronization and De-inter leaver

2 dimensional sync protection starts once sync word 47 hex or inverted sync word B 8 hex is detected. In

this algorithm, sync status changes with hysteresis depending on sync or non-sync detection every 204

byte, so that the probability of false-LOCK or Sync-loss is minimized.

When the packet synchronization is achieved,the convolutional de-inter leaver

(Forney, depth=12) starts operating.

(8) Reed - Solomon decoder

The Galois Field is generated by F(x) = x⁸+x⁴+x³+x²+¹

Code is generated by G(x) = (x-α⁰)(x-α¹)(x-α²) • • (x-α¹⁵)

If RS_SKIP is high, no correction is performed.

CPU I/F Register

RS_SKIP → ADD 9h

(9) Energy Dispersal

Energy dispersal descrambling is represented by the polynomial x¹⁵+ x¹⁴+1. Initial sequence is loaded

when inverted sync word B8hex is detected. 1 dimensional sync protection circuit checks the inverted sync

word every 8 packets. When it is in sync, RSYNC goes high. Even if the sync is lost, the initial sequence

continues to be loaded at previous time step.

CPU I/F Register

RSYNC → ADD 3h

—13—

CXD1961Q

(10) Output Data Format

The following figure shows the output format of BYTCLK, PKTCLK, PKTERR. BYTCLK is generated by

dividing the internal viterbi clock by 8. Data output DATA[7:0] is output in sync with BYTCLK. DOUT_INV

determines whether DATA[7:0] is output on the rising edge or the falling edge of BYTCLK. PKTCLK High-

Time is equal to 188 data bytes period and PKTCLK Low-Time is equal to 16 parity bytes period. PKTERR

goes H if an uncorrectable error packet is encountered.

CPU I/F Register

DOUT_INV → ADD 9h

no error

data

correctable error

data

uncorrectable error

data

parity

pa

BYTCLK

PKTCLK

PKTERR

BYTCLK and PKTCLK have varying forms, depending on the punctured rate. The following figure shows

Minimum and Maximum values for each rate.

One unit represents 1 sampling clock (=2 Symbol rate) cycles.

BYTCLK

PKTCLK

Period

High-Time

Low-Time

Period

High-Time

Low-Time

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

R=1/2

R=2/3

R=3/4

R=4/5

R=5/6

R=6/7

R=7/8

16

12

10

9

16

12

11

10

8

6

5

4

8

6

5

8

6

5

4

8

6

5

3264 3264 3008 3008 256

2448 2448 2256 2256 192

2176 1276 2005 2006 170

2040 2040 1880 1880 160

1948 1949 1804 1805 153

1904 1904 1754 1755 149

1865 1866 1718 1719 146

256

192

171

160

154

150

147

9

(For example)

SACLK

R=1/2

R=7/8

Viterbi

clock

Byteclock

Viterbi

clock

Byte clock

—14—

CXD1961Q

Package Outline Unit : mm

100PIN LQFP (PLASTIC)

16.0 ± 0.2

14.0 ± 0.1

75

51

76

50

A

26

100

(0.22)

1

25

+ 0.08

0.18 – 0.03

+ 0.05

0.127 – 0.02

0.5 ± 0.08

+ 0.2

1.5 – 0.1

0.1

0.1 ± 0.1

NOTE: Dimension “ ” does not include mold protrusion.

0° to 10°

DETAIL A

PACKAGE STRUCTURE

PACKAGE MATERIAL

EPOXY/PHENOL RESIN

SOLDER PLATING

LQFP-100P-L01

LEAD TREATMENT

LEAD MATERIAL

SONY CODE

EIAJ CODE

QFP100-P-1414-A

42 ALLOY

JEDEC CODE

PACKAGE WEIGHT

—15—


型号：	CXD1961Q
厂家：	SONY CORPORATION
描述：	DVB-S Front-end IC (QPSK demodulator + FEC) DVB-S的前端集成电路（ QPSK解调器+ FEC）的
文件：	总15页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD1961Q [SONY]

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