CXD1969 [SONY]

CableCARDTM INTERFACE CONTROLLER; CableCARDTM接口控制器
CXD1969
型号: CXD1969
厂家: SONY CORPORATION    SONY CORPORATION
描述:

CableCARDTM INTERFACE CONTROLLER
CableCARDTM接口控制器

控制器
文件: 总2页 (文件大小:160K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CableCARDTM INTERFACE CONTROLLER  
CXD1969  
Customer Requirements Specification  
DESCRIPTION  
&
Play’ and OpenCableTM  
100 pin Plastic LQFP  
The CXD1969 is an ‘Plug  
CableCARDTM interface controller IC designed for use with  
OpenCableTM compliant CableCARDTM modules. It performs  
the communication interface between a host microcontroller  
and the CableCARDTM. The IC communicates to the Host  
either by a 68k-type or I2C connection. Communication  
between the CXD1969 and the CableCARDTM is highly efficient  
due to the inclusion of a fully integrated hardware Physical  
layer.  
MPEG2 Transport Stream interfaces are fully programmable  
ensuring compatibility to commonly used Front End  
demodulators and MPEG2 decoders.  
A SCTE 28 compliant software stack is also available for this  
device.  
FEATURES  
PC Card Interface  
Transport Stream Interfaces  
Fully integrated CableCARDTM interface.  
Support for generic PC Cards.  
Accepts MPEG2 compliant TS.  
SCTE28 compliant parallel TS interfaces  
to/from POD Card.  
Supports 3V3 modules (VPP either 3V3 or 5V)  
Integrated Physical layer with 1Kbyte buffers.  
TS interface from tuner (up to 72Mbits/s).  
Serial TS interface to downstream device (up  
to 72Mbits/s).  
Host Interface  
Four serial input and output modes.  
68k-type host bus interface  
27MHz or 33MHz operating frequency.  
I2C host bus interface.  
Miscellaneous  
Integrated PLL for serial TS.  
5V compatible I/Os.  
100kHz or 400kHz operation.  
Maskable/programmable interrupt capability.  
3V3 logic levels.  
LQFP 100-pin package.  
OOB Interface  
Supports SCTE 28 Bidirectional OOB I/F.  
APPLICATIONS  
iDTV  
Set Top Box  
Personal Video Recorder (PVR)  
Document No. DC_D1969_CM_2108  
Version: 3.0  
- 1 -  
Released: Jul 2004  
CXD1969  
2 Key differences between CXD2099AR and CXD1969  
Clock frequency can be 27MHz or 33MHz  
No change to 68k host interface  
Polarity/function of HIRQ is now programmable  
Removed ability to extend data and address lines by the use of external buffers  
TS Input I/F is now serial only, (parallel TS input removed)  
No change to TS Output I/F  
Hot-swap state machine removed  
Support for dual-slot removed  
VCCSW and OVERLOAD functionality removed  
VCCSEL changed to VPPSEL to support 3V3 or 5V PODs  
Bidirectional OOB I/F added  
Technology process change, some changes to DC spec  
Pinout optimized for POD  
Document No. DC_D1969_CM_2108  
Version: 3.0  
- 5 -  
Released: Jul 2004  

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