LV8121V [SANYO]
For Fan Motor 3-phase Brushless Motor Driver; 对于风扇电机的3相无刷电机驱动器
| 型号： | LV8121V |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | For Fan Motor 3-phase Brushless Motor Driver |
| 文件： | 总14页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA2135
Bi-CMOS IC
For Fan Motor
LV8121V
3-phase Brushless Motor Driver
Overview
The LV8121V is a three-phase brushless motor driver that uses a PWM drive technique. The motor speed is controlled
by changing the PWM duty that based on an analog voltage input. This motor driver includes an automatic return
constraint protection circuit and is optimal for driving fan motors.
Features
• PWM control based on an analog voltage input (the CTL voltage), synchronous rectification
• One Hall-effect sensor FG output
• Automatic return constraint protection circuit (ON/OFF=1/15)
• Start/Stop switching circuit, Forward/Reverse switching circuit
• Current limiter circuit, Low-voltage shutdown protection circuit, Thermal shutdown protection circuit
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage
V
max
V
pin
36
42
CC
CC
VG max
max
VG pin
V
Output current
I
t ≤ 500ms
3.5
A
O
Allowable power dissipation
Operation temperature
Storage temperature
Junction temperature
Pd max
Topr
Mounted on a specified board *
1.7
W
°C
°C
°C
-30 to +100
-55 to +150
150
Tstg
Tj max
* Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board
Caution 1) Absolute maximum ratings represent the values which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
O2412NKPC 20120919-S00001 No.A2135-1/14
LV8121V
Recommendation Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage range
V
I
8.0 to 35
0 to -6
0 to -7
0 to 6
CC
5V constant voltage output current
HB output current
mA
mA
V
REG
HB
I
FG applied voltage
V
FG
FG output current
I
0 to 5
mA
FG
Electrical Characteristics at Ta = 25°C, V
= 24V
CC
Ratings
typ
Parameter
Symbol
1
Conditions
Unit
min
max
4.7
Supply current 1
I
I
3.5
mA
mA
CC
Supply current 2
2
At stop
1.1
1.5
CC
Output block
Lower side output ON resistance
R
R
R
R
(L1)
(L2)
(H1)
(H2)
I
I
I
I
= 1.2A
= 2.0A
= -1.2A
= -2.0A
0.26
0.26
0.27
0.27
120
0.9
0.43
0.43
0.45
0.45
170
Ω
Ω
Ω
Ω
μA
V
ON
ON
ON
ON
O
O
O
O
Upper side output ON resistance
Mid output current
I
(M)
V
= 12V
O
O
Lower side diode forward voltage
V
V
V
V
(L1)
I
= -1.2A
= -2.0A
= 1.2A
= 2.0A
1.20
1.35
1.20
1.35
D
D
(L2)
(H1)
(H2)
I
I
I
1.0
V
D
D
D
D
D
D
Upper side diode forward voltage
0.9
V
1.0
V
5V Constant voltage Output
Output voltage
VREG
4.6
5.0
20
5
5.4
100
100
V
Line regulation
ΔV(REG1)
ΔV(REG2)
V
= 8.0 to 35V
mV
mV
CC
I = -1 to -6mA
O
Load regulation
Hall Amplifier
Input bias current
I (HA)
-2
0.3
0
-0.1
μA
V
B
Common mode input voltage range 1
Common mode input voltage range 2
V
1
When Hall-effect sensors are used
VREG-1.7
VREG
ICM
ICM
V
2
When one-side inputs are biased
(Hall IC application)
SIN wave
V
Hall input sensitivity
Hysteresis width
V
80
9
mVp-p
mV
HIN
ΔV (HA)
20
8
35
16
-5
IN
Input voltage L → H
Input voltage H → L
HB pin
V
3
mV
SLH
V
-20
-12
mV
SHL
Output voltage
V
I
= -0.5mA
= 0V
O
VREG-0.27
-10
VREG-0.18
VREG-0.10
V
HBO
HB
Output leakage current
Reference Oscillator (CT pin)
High level voltage
Low level voltage
I (HB)
V
μA
L
V
(CT)
VREG×0.54 VREG×0.56 VREG×0.58
VREG×0.43 VREG×0.45 VREG×0.47
VREG×0.10 VREG×0.11 VREG×0.12
V
V
H
V (CT)
L
Amplitude
V(CT)
V
Oscillation frequency
RT pin
f(REF)
C = 56pF, R = 11kΩ
1.71
2.11
2.51
MHz
High level output voltage
Low level output voltage
Charge Pump Output (VG pin)
Output voltage
V
(RT)
OH
I
I
= -0.3mA
= 0.3mA
VREG-0.15
0.05
VREG-0.1
0.1
VREG-0.05
0.15
V
V
RT
RT
V
(RT)
OL
VG
V
+4.1
V
+4.7
V
+5.4
V
OUT
CC
CC
CC
CP1 pin
High level output voltage
Low level output voltage
Charge pump frequency
V
(CP1)
I
I
= -2mA
V
-1.4
V
-1.1
V
CC
-0.7
V
V
OH
CP1
CP1
CC
CC
V
(CP1)
= 2mA
0.55
0.75
f(REF)/32
0.90
OL
f(CP1)
MHz
Continued on next page.
No.A2135-2/14
LV8121V
Continued from preceding page.
Ratings
typ
Parameter
Symbol
(PWM)
Conditions
Unit
min
max
PWM Oscillator
High level voltage
Low level voltage
Amplitude
V
2.75
3.05
3.35
V
V
H
V (PWM)
L
1.20
1.40
-80
1.35
1.70
-63
1.50
2.00
-45
V(PWM)
V
Charge current
Oscillation frequency
LIM pin
I
V
= 2.1V
μA
kHz
CHG
f(PWM)
PWM
C = 1800pF
15.1
19.2
24.8
Input bias current
CTL pin
I (LIM)
-2
-0.1
μA
B
Input voltage
V
V
1
2
Output duty: 100%
Output duty: 0%
2.74
1.15
-2
3.07
1.33
-0.2
3.40
1.51
V
V
CTL
CTL
Input bias current
Current limiter operation
Limiter voltage
I (CTL)
B
μA
V
0.23
0.25
0.275
V
RF
CSD Oscillator
High level voltage
Low level voltage
Amplitude
V
(CSD)
2.75
1.43
1.12
-13.5
8.0
3.05
1.68
1.37
-10.5
11.5
83
3.35
1.93
1.62
-7.0
14.5
104
V
V
H
V (CSD)
L
V(CSD)
V
Charge current
I
I
1
μA
μA
Hz
CSD
CSD
Discharge current
Oscillation frequency
Thermal shutdown operation
2
f(CSD)
C = 0.047μ F
62
Thermal shutdown operation
temperature
TSD
Design target value *
(Junction temperature)
Design target value *
(Junction temperature)
150
180
40
°C
°C
Hysteresis width
ΔTSD
FG pin
Low level output voltage
Output leakage current
V
(FG)
I
= 2mA
0.1
0.3
10
V
OL
FG
I (FG)
V
= 6V
μA
L
FG
Low-voltage shutdown protection circuit
Operating voltage
V
V
6.52
6.98
0.36
7.03
7.49
0.46
7.54
8.00
0.56
V
V
V
SDL
SDH
Release voltage
Hysteresis width
ΔVSD
F/R pin
High level input voltage range
Low level input voltage range
Input open voltage
Hysteresis width
V
V
V
V
(FR)
2.0
0
VREG
1.0
V
V
IH
(FR)
IL
(FR)
VREG-0.5
0.15
VREG
0.5
V
IO
(FR)
IS
0.35
0
V
High level input current
Low level input current
S/S pin
I
I
(FR)
IH
VF/R = VREG
VF/R = 0V
-10
10
μA
μA
(FR)
IL
-80
-50
-35
High level input voltage range
Low level input voltage range
Input open voltage
Hysteresis width
V
V
V
V
(SS)
2.0
0
VREG
1.0
V
V
IH
(SS)
(SS)
IL
VREG-0.5
0.15
VREG
0.5
V
IO
(SS)
IS
0.35
0
V
High level input current
Low level input current
I
I
(SS)
IH
VS/S = VREG
VS/S = 0V
-10
10
μA
μA
(SS)
IL
-80
-50
-35
* : These items are design target value and are not tested.
No.A2135-3/14
LV8121V
Package Dimensions
unit : mm (typ)
3333A
TOP VIEW
SIDE VIEW
BOTTOM VIEW
15.0
44
23
22
(4.7)
1
0.65
0.22
0.2
(0.68)
SIDE VIEW
SANYO : SSOP44K(275mil)
Pd max -- Ta
Mounted on the specified board: 114.3×76.1×1.6mm3
glass epoxy
2.0
1.7
1.5
1.0
0.68
0.5
0
--30
0
30
60
90
120
Ambient temperature, Ta -- °C
Pin Assignment
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
LV8121V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
Top view
No.A2135-4/14
LV8121V
Block Diagram
No.A2135-5/14
LV8121V
Pin Function
Pin No. Pin name
Function
Equivalent circuit
1
2
3
4
PWM
Pin to set the PWM oscillation frequency.
VREG
Connect a capacitor between this pin and GND1.
A frequency of about 19kHz can be set by using
a 1800pF capacitor.
200Ω
950Ω
1
LIM
Pin to set the minimum output duty.
VREG
A minimum output duty can be set by inputting a fixed
voltage to the LIM pin through resistor division of VREG.
Connect the LIM pin to GND1 if this pin is not used, then the
minimum output duty becomes 0 %.
500Ω
2
CTL
Pin to control the output duty.
VREG
The output duty is determined by the result of comparing
the CTL pin voltage with the PWM oscillation waveform.
When the CTL pin is open, the output duty becomes 100%.
Therefore, connect a pull-down resistor to prevent open.
500Ω
3
S/S
Start / Stop control pin.
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
Goes high when left open.
Low for start.
100kΩ
10kΩ
The hysteresis width is about 0.35V.
4
-
5
6
IN3
Hall input pins.
VREG
+
+
-
IN3
The input is seen as the high level input when IN > IN , and
as the low level input for the opposite state.
-
7
IN2
+
8
IN2
If noise on the Hall signals is a problem, connect a capacitor
-
+ -
between the corresponding IN and IN inputs.
9
IN1
+
10
IN1
5
7
9
6
8
10
Continued on next page.
No.A2135-6/14
LV8121V
Continued from preceding page.
Pin No. Pin name
Function
Forward / Reverse control pin.
Equivalent circuit
14
F/R
VREG
Low : 0V to 1.0V
High : 2.0V to VREG
Goes high when left open.
Low for forward.
100kΩ
10kΩ
The hysteresis width is about 0.35V.
14
34
V
1
2
Power supply pin.
CC
(For systems other than the motor drive output.)
Connect a capacitor between this pin and GND1 for
stabilization.
12, 33
V
Motor drive output power supply pins.
CC
V
CC
2
12 33
20, 21
22, 23
24, 25
OUT3
OUT2
OUT1
Motor drive output pins.
20 21
22 23
24 25
15, 30
18, 27
31
RF
Source pins of the lower side output FET.
Connect a resistor (Rf) between these pins and
GND.
18 27
15 30
GND2
RFS
Motor drive output circuit GND pins.
Output current detection pin.
VREG
Connect the RFS pin to the RF pin.
5kΩ
31
35
37
VG
Charge pump output pin.
V
CC
2
Connect a capacitor between this pin and V 2.
CC
300Ω
CP2
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP1.
35
37
Continued on next page.
No.A2135-7/14
LV8121V
Continued from preceding page.
Pin No. Pin name
Function
Equivalent circuit
36
CP1
Pin to connect the capacitor for charge pump.
Connect a capacitor between this pin and CP2.
V
CC
2
300Ω
36
38
VREG
5V constant voltage output pin.
V
1
CC
(Power supply pin for the control circuits.)
Connect a capacitor between this pin and GND1 for
stabilization.
50Ω
38
39
40
GND1
RT
GND pin for the control circuits.
Pin to set the reference oscillation frequency.
Connect a resistor to charge / discharge the capacitor of CT
between this pin and CT.
VREG
40
200Ω
41
41
42
CT
HB
Pin to set the reference oscillation frequency.
Connect a capacitor between this pin and GND1.
Hall bias switch pin.
VREG
Goes off when the S/S input is the stop mode.
250Ω
42
100kΩ
43
FG
One hall-effect sensor FG output pin.
(This is an open-drain output.)
VREG
43
Continued on next page.
No.A2135-8/14
LV8121V
Continued from preceding page.
Pin No. Pin name
Function
Equivalent circuit
44
CSD
Pin to set the operating time of the constraint protection.
Connect a capacitor between this pin and GND1.
VREG
500Ω
44
11, 13
16, 17
19, 26
28, 29
32
NC
No connection pins.
Backside Die-Pad
metal
Exposed Die-Pad.
The metal of the IC’s backside is the Exposed Die-pad and
is internally connected to GND1, GND2. For stabilization,
connect the Exposed Die-pad to GND1 externally.
+
−
Three-phase logic truth table (A high level input is the state where IN > IN )
F/R = L
F/R = H
Output
IN1
H
H
H
L
IN2
L
IN3
H
L
IN1
L
IN2
H
H
L
IN3
L
OUT1
OUT2
OUT3
1
2
3
4
5
6
L
L
H
M
L
M
H
H
M
L
L
L
H
H
H
L
H
H
H
L
L
L
M
H
H
M
L
H
H
H
L
L
L
H
H
L
M
H
L
H
L
L
No.A2135-9/14
LV8121V
Description of LV8121V
1. Motor Drive Output Circuit
The LV8121V provides a charge pump circuit and implements both upper side and lower side N-channel power FET
drive circuit. This IC employs the direct PWM drive technique. The motor speed is controlled by changing the output
duty according to an analog voltage input (CTL). The upper side N-channel power FET is switched so that the output
duty tracks the CTL voltage.
The PWM frequency is determined by the capacitor connected between the PWM pin and GND1.
When the PWM switching of the upper side N-channel power FET is off, the lower side N-channel power FET is
turned on (synchronous rectification). Therefore, it is possible to reduce the temperature increase of the lower side
N-channel power FET.
2. PWM Oscillator
The PWM frequency is set by the oscillation frequency of the PWM pin. When a capacitor C [F] is connected between
the PWM pin and GND1, the PWM frequency (fPWM) is calculated as follows.
fPWM = 1/(28900 × C)
When a 1800pF capacitor is connected, this frequency becomes about 19kHz.
By the variance of the IC, “28900” of the above formula has varied from 22400 to 36800.
If the PWM frequency is too high, since the switching power loss will be large, the IC temperature increase will be
excessive. The PWM frequency therefore should be normally kept below 50kHz, which is achieved with a capacitor C
of 1000pF or higher. The GND lead of the connected capacitor to the PWM pin should be connected as close as
possible to the GND1 pin.
3. Output Duty
The CTL voltage and the PWM oscillation waveform are compared to determine the output duty of the upper side
N-channel power FET.
If the LIM pin is not used (LIM=GND), the output duty becomes 0% when the CTL voltage is lower than about 1.3V
and 100% when it exceeds about 3.1V.
For the application that inputs a fixed voltage to the LIM pin, the LIM voltage and the PWM oscillation waveform are
compared to determine the minimum output duty. Accordingly, even if the CTL voltage is lower than the LIM voltage,
the output duty does not decrease below the minimum output duty.
PWM oscillation waveform
LIM voltage
compared result
CTL voltage
ON
Upper side FET
(PWM)
OFF
ON
Lower side FET
(synchronous rectification)
OFF
If a minus voltage is applied to the CTL pin, this pin current must be limited within 2mA by inserting the resistor of
about 200Ω.
When the CTL pin is open, the output duty becomes 100%. Therefore, connect a pull-down resistor to prevent open.
If the output duty is fast reduced by dropping the CTL voltage quickly when the motor speed is changed from high to
low, since this IC employs the synchronous rectification, the lower side N-channel power FET can be the short brake
condition that turns on two phases. If the lower side N-channel power FET (synchronous rectification) is switched
from on to off while this condition, the motor current may flow on the power supply side, and the power supply
voltage may bounce. The bounce of the power supply voltage is different on the motor speed, the varied range of the
CTL voltage and the capacitance of the power supply line. Therefore, check sufficiently that the bounce of the power
supply voltage does not exceed the maximum rating when the CTL voltage is changed.
Continued on next page.
No.A2135-10/14
LV8121V
Continued from preceding page.
In case of limiting the bounce of the power supply voltage, the maximum voltage of
the V can be limited according to the following method. The maximum voltage of
To VG
CC
the VG is limited by using Zener diode, NPN transistor and some resistors. Normally,
the relation between VG and V becomes “VG = V + 4.7V”. If V rises above
160kΩ
33kΩ
5.1kΩ
CC
CC
CC
5.6V
Zener
“VG max - 4.7V” when VG is limited to VG max, this relation does not keep.
Because the sufficient gate voltage cannot be applied to the upper side N-channel
power FET when this relation does not keep, this IC includes the protective function
that turns off the upper side N-channel power FET.
Accordingly, if V
FET is turned off, and the V
CC
rises above “VG max - 4.7V” when VG is limited to VG max, the upper side N-channel power
bounce caused by dropping the CTL voltage can be limited to
CC
“V
= VG max - 4.7V”. When the above reference circuit is used, VG is limited to about 36.7V, and V
is limited
is steeply bounced
CC
CC
CC
to about 32.0V. But this function does not guarantee that any V
by dropping the CTL voltage, this function may not limit the V
bounce can be limited. If V
bounce.
CC
CC
4. Current Limiter Circuit
The current limiter circuit limits the output current peak to the value determined by “I = V /Rf” (V = 0.25V typ.,
RF RF
Rf: current detection resistor). When the current limiter is operating, the upper side N-channel power FET is switched,
and the output current is suppressed by reducing the output duty.
5. Reference Oscillator
Connect a 56pF capacitor between CT and GND1, and a 11kΩ resistor between RT and CT. Then, the reference
oscillation frequency becomes about 2.1MHz. The reference oscillation frequency functions as a reference clock for
the internal logic circuit. The charge pump circuit boosts the voltage using a frequency that is 1/32 of the reference
oscillation frequency.
6. Start/Stop Switching Circuit
When the S/S pin is set to the low level, start/stop switching circuit is the start mode. Inversely, when the S/S pin is set
to the high level or open, start/stop switching circuit is the stop mode. This IC goes into a power saving state that
reduces the supply current at the stop mode. In the power saving state, the bias current is removed from most of the
circuits in the IC.
The operating circuits in the power saving state are limited to the start/stop switching circuit and the 5V constant
voltage output. The other circuits do not operate. Both upper side and lower side N-channel power FET are turned off
in the power saving state.
If a minus voltage is applied to the S/S pin, this pin current must be limited within 2mA by inserting the resistor of
about 200Ω.
7. Forward / Reverse Switching Circuit
The motor rotation direction can be switched by using the F/R pin. However, the following notes must be observed if
the F/R pin is switched while the motor is rotating.
• This IC is designed to avoid the through current when the direction is switched. However, the bounce of the V
CC
voltage (due to the motor current that flows instantly on the power supply side) may be caused during the direction
switching. If this bounce is a problem, the capacitance inserted between V and GND must be increased.
CC
• If the motor current after the direction switching exceeds the current limiter value, the upper side N-channel power
FET will be turned off, but the lower side N-channel power FET will be the short brake condition. On the short
brake condition, the current determined by the motor back EMF voltage and the coil resistance will flow. Because
the current limiter circuit of this IC cannot limit this current, applications must be designed so that this current does
not exceed the maximum rating (3.5A). When the motor speed is higher, the direction switching is dangerous.
If a minus voltage is applied to the F/R pin, this pin current must be limited within 2mA by inserting the resistor of
about 200Ω.
No.A2135-11/14
LV8121V
8. Hall Input Signal
The input amplitude of 100mVp-p or more (differential) is desirable in the Hall inputs. The closer the input
wave-form is to a square wave, the required input amplitude is lower. Inversely, the closer the input wave-form is to a
triangular wave, the higher input amplitude is required. Also, note that the input DC voltage must be set within the
common mode input voltage range.
For the Hall IC application, one side (either the + or – side) of the Hall inputs must be fixed at a voltage within the
common mode input voltage range that applies when the Hall-effect sensors are used, and the input voltage range for
the other side becomes 0V to VREG.
If noise on the Hall signals is a problem, that noise must be excluded by inserting capacitor between the Hall inputs as
close as possible to these pins.
When the Hall inputs for all three phases are in the same state, all the outputs (the both upper side and lower side
N-channel power FET) are turned off.
9. FG Output
The FG pin is the pulse output that has the same frequency as Hall input IN1 (one Hall-effect sensor FG output).
10. HB Pin
The HB pin is the 5V constant voltage output that combines the switch function. This pin is connected to the base of
external NPN transistor that supplies the bias of the Hall-effect sensors. If the HB output is turned off, this external
NPN transistor is too turned off, and the bias of the Hall-effect sensors is cut (Hall bias switch).
The HB output is turned off and is made pull-down by a 100kΩ internal resistor when the S/S pin is the stop mode.
Therefore, the bias of the Hall-effect sensors can be cut when the S/S pin is the stop mode.
In case the LIM pin is not used (LIM = GND), if the CTL voltage falls below 0.7V, the HB output is turned off, and
the bias of the Hall-effect sensors is cut.
In case the minimum output duty is determined by the LIM pin, even if the CTL voltage falls below 0.7V, the HB
output is not turned off.
If the HB pin is not used, keep open.
11. Constraint Protection Circuit
The constraint protection circuit operates to turn the motor drive (the upper side N-channel power FET) on or off
repeatedly in the motor constrained state. Therefore, the IC and the motor are protected. The drive on/off time can be
set by adjusting the oscillation frequency of the CSD pin with external capacitor. When a capacitor C [μF] is
connected between the CSD pin and GND1, the drive on/off time is calculated as follows.
TCSD1 (drive on time) = 8.21 × C
TCSD2 (drive off time) = TCSD1 × 15
When a 0.047μF capacitor is connected, this protection function will iterate an on/off period in which drive is on for
about 0.39sec and off for about 5.8sec.
By the variance of the IC, “8.21” of the above formula has varied from 5.41 to 11.01.
If the switching from L to H of the Hall input IN1 (the rising edge on the FG output) is not caused during the drive on
time, this protection function turns the motor drive off, and returns the motor drive on after the drive off time.
If the drive on time to be set is too short, this protection function operates at a normal motor start-up, and the motor
may not speed up since this protection function iterates an on/off period. Also, if the motor speed is too low, this
protection function operates when one cycle of the Hall input IN1 is longer than the drive on time. The drive on time
must be set to a sufficient time so that this protection function does not operate except the motor constrained state.
The oscillation waveform of the CSD pin is used for some circuits in addition to the constraint protection circuit.
Therefore, it is desirable to oscillate the CSD pin even if the constraint protection function is unnecessary.
The CSD pin combines the function as the initial reset pin. The time that the CSD voltage is charged to about 1.25V is
determined as the initial reset. At the initial reset, all the outputs (the both upper side and lower side N-channel power
FET) are turned off.
If the constraint protection function is not used, the oscillation of the CSD pin must be stopped by connecting a 220kΩ
resistor and a 0.01μF capacitor in parallel between the CSD pin and GND1. However, when the oscillation of the CSD
pin is stopped, note that some functions do not operate in the following cases.
• If the motor does not rotate at the motor start-up because the motor is constrained, the upper side N-channel power
FET may be switched by the current limiter. But, the synchronous rectification does not operate when the oscillation
of the CSD pin is stopped.Continued on next page.
• In case the LIM pin is not used (LIM = GND), even if the CTL voltage falls below 0.7V, the HB output is not turned
off when the oscillation of the CSD pin is stopped.
No.A2135-12/14
LV8121V
12. Low-voltage Shutdown Protection Circuit
The IC includes a low-voltage shutdown protection circuit to protect against incorrect operation when the V
power
CC
voltage falls
supply is switched on or if the V
voltage falls below the allowable operating range. When the V
CC
CC
below the specified voltage (VSDL), this protection function operates, and all the outputs (the both upper side and
lower side N-channel power FET) are turned off. When the V
protection function is released.
voltage rises above the release voltage (VSDH), this
CC
13. Thermal Shutdown Protection Circuit
If the junction temperature rises to the specified temperature (TSD), this protection function operates, and the upper
side N-channel power FET is turned off. If the temperature decrease falls to more than the hysteresis width (ΔTSD),
this protection function is released.
14. Power Supply Stabilization
Because a large switching current flows in the V
line, the line inductance and other factors can lead to V
CC
CC
voltage fluctuations. Sufficient capacitance should be provided between V
wiring routes are used, choose a capacitor with even larger capacitance.
and GND for stabilization. When long
CC
Ceramic capacitors of about 0.2μF must be connected between the V 1 pin and the GND1 pin as close as possible to
CC
these pins for excluding noise.
15. VREG Pin
The VREG pin is the power supply for the control circuits. Therefore, a capacitor of about 0.1μF must be connected
between the VREG pin and the GND1 pin as close as possible to these pins for stabilization.
16. VG Pin
When the S/S pin is the stop mode, the VG pin is the high-impedance condition in the IC. If the ambient temperature
of the capacitor inserted between VG and V 2 becomes high when the VG pin is the high-impedance condition,
CC
since the voltage charged in this capacitor may rise due to the temperature characteristic of the capacitor, the VG
voltage may rise. Therefore, prevent the VG voltage from rising by inserting the resistor of about 200kΩ between VG
and V 2 or VG and GND1 so that the VG pin is not the high-impedance condition.
CC
17. Notes on wiring of a Printed Circuit Board
Two pins are provided for each of pins (V 2, RF, OUT1, OUT2, OUT3, GND2) where large current flows. Both of
CC
these pins should be externally connected.
18. The Metal of the IC’s Backside
The metal of the IC’s backside is the Exposed Die-pad and is internally connected to GND1, GND2. For stabilization,
connect the Exposed Die-pad to GND1 externally. The IC’s generation of heat can be efficiently diffused to a printed
circuit board by soldering the Exposed Die-pad to the copper of the printed circuit board.
19. NC Pins
The NC pins are electrically open. These pins may be used for wiring routes.
No.A2135-13/14
LV8121V
Application (Reference value)
100Ω 2SC5964 510Ω/0.5W
5.1kΩ
Exposed
24V
47μF
100Ω
Die-Pad
160kΩ
27kΩ
15kΩ
2SC
5964
5.6V
Zener
+
0.1μF
0.1μF
0.17Ω/1W
0.2μF
10kΩ
FG
56pF
0.1μF
11kΩ
0.033μF
1500pF
0.047μF
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
LV8121
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
1800pF
4700pF
100kΩ
51Ω
200Ω
CTL S/S
F/R
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature,
high current, high voltage, or drastic temperature change, even if it is used within the range of absolute
maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a
confirmation.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
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No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of October, 2012. Specifications and information herein are subject
to change without notice.
PS No.A2135-14/14
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