LV8139JA [ONSEMI]
Sine wave PWM Drive, Pre drive IC,;
| 型号： | LV8139JA |
| 厂家： | 
ONSEMI |
| 描述： | Sine wave PWM Drive, Pre drive IC, |
| 文件： | 总19页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LV8139JA
Sine wave PWM Drive, Pre drive IC,
for Brushless Motor Drive
Overview
The LV8139JA is a PWM system pre driver IC designed for three-phase
brushless motors.
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This IC reduces motor driving noise by using a high-efficiency, sine wave
PWM drive type.
It incorporates a full complement of protection circuits and, by combining it
with a hybrid IC in the STK611 or STK5C4 series, the number of components
used can be reduced and a high level of reliability can be achieved.
Furthermore, its power-saving mode enables the power consumption in the
standby mode to be reduced to zero. This IC is optimally suited for driving
various large-size motors such as those used in air conditioners and hot-water
heaters.
SSOP30 (275mil)
Features
• Three-phase bipolar drive
• Sine wave PWM drive
GENERIC
MARKING DIAGRAM*
• Drive phase setting function (Set 0-58 degrees 32 steps: There is an adjustment
function corresponding to the CTL pin input)
• Supports power saving mode(power saving mode at CTL pin voltage of 0.95V
XXXXXXXXXX
YMDDD
(typ) or less; I
• Supports bootstrap
= 0mA, HB pin turned off)
CC
• Automatic recovery type constraint protection circuit
• Forward/reverse switching circuit, Hall bias pin
• Current limiter circuit, low-voltage protection circuit, and thermal shutdown
protection circuit
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
• FG1 and FG3 output (360-degree electrical angle/1 pulse and 3 pulses)
Typical Applications
• Air Purifier
• Clothes Dryer
• Air conditioners
• Consumer
ORDERING INFORMATION
Ordering Code:
LV8139JA-AH
Package
SSOP30 (275mil)
(Pb-Free / Halogen Free)
Shipping (Qty / packing)
1000 / Tape & Reel
† For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
April 2016- Rev. 1
LV8139JA/D
LV8139JA
Specifications
Absolute Maximum Ratings at Ta = 25C (Note 1)
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage
V
I
max
V
pin
CC
18
15
CC
Output current
max
mA
W
W
V
O
Allowable power dissipation
Pd max1
Pd max2
Independent IC
Mounted on a specified circuit board. (Note 2)
0.45
1.05
18
CTL pin applied voltage
V
max
CTL
FG1,FG3 pin applied voltage
V
V
1 max
18
V
FG
FG
3 max
Junction temperature
Operating temperature
Storage temperature
Tj max
Topr
150
-40 to +105
-55 to +150
C
C
C
Tstg
1. Stresses exceeding those listed in the Absolute Maximum Rating table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Specified circuit board : 114.3mm 76.1mm 1.6mm, glass epoxy
Recommendation Operating Range at Ta = 25C (Note 3)
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage range
V
I
9.5 to 16.5
CC
VREG5 pin output current
HB pin output current
-10
-30
10
mA
mA
mA
REG
HB
I
I
FG1,FG3 pin output current
1, I 3
FG FG
3. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta 25C, V
= 15V (Note 4)
CC
Ratings
typ
Parameter
Symbol
1
Conditions
Unit
min
max
Supply current 1
Supply current 2
I
I
4
0
6
mA
CC
2
At stop (CTL VIL1)
10
A
CC
Output Block (Pin HIN1, HIN2, HIN3, LIN1, LIN2 and LIN3)
High level output voltage
Upper output ON resistance
Low level output voltage
Lower output ON resistance
Output leakage current
V
I
I
I
I
= -10mA
= -10mA
= 10mA
= 10mA
VREG-0.40 VREG-0.25
V
HO
O
O
O
O
R
H
L
25
0.15
15
40
ON
V
0.25
25
V
LO
R
ON
I
leak
10
A
s
s
O
Bootstrap charge pulse width
Output minimum dead time
Tboot
Tdt
1.6
1.6
2.5
2.5
3.4
3.4
5V Constant Voltage Output (VREG5 pin)
Output voltage
VREG
I
= -5mA
4.7
4.9
5.1
100
100
V
O
Voltage fluctuation
Load fluctuation
V (REG1)
V (REG2)
V
= 9.5 to 16.5V, I = -5mA
mV
mV
CC
= -5 to -10mA
O
I
O
+
-
+
-
+
-
Hall Amplifier (Pin IN1 , IN1 , IN2 , IN2 , IN3 and IN3 )
Input bias current
IB (HA)
VICM1
VICM2
-1
0.3
0
0
VREG-1.8
VREG
A
V
Common-mode input voltage range 1
Common-mode input voltage range 2
When a Hall element is used
Single-sided input bias mode
(when a Hall IC is used)
Sine wave,
V
Hall input sensitivity
VHIN
80
mVp-p
Hall element offset = 0V
Hysteresis width
V (HA)
15
5
30
15
45
25
-5
mV
mV
mV
IN
Input voltage Low High
Input voltage High Low
VSLH
VSHL
-25
-15
Continued on next page.
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2
LV8139JA
Continued from preceding page.
Ratings
typ
Parameter
Symbol
(CSD)
Conditions
Unit
min
max
CSD Oscillator Circuit (CSD pin)
High level output voltage
Low level output voltage
Amplitude
V
V
2.75
2.95
3.15
V
V
OH
(CSD)
0.85
1.7
-14
6
1.05
1.9
-10
10
1.25
2.1
-6
OL
V (CSD)
Vp-p
A
A
External capacitor charging current
ICHG1 (CSD)
ICHG2 (CSD)
VCHG1 = 2.0V
External capacitor discharging
current
VCHG2 = 2.0V
14
Lock detection ON/OFF time ratio
LRTO
Drive OFF/drive ON
11
PWM Oscillator (PWM pin)
High level output voltage
Low level output voltage
Amplitude
V
V
(PWM)
(PWM)
3.3
1.3
1.8
3.5
1.5
3.7
1.7
2.2
V
V
OH
OL
V (PWM)
f (PWM)
2.0
Vp-p
kHz
Oscillation frequency
C = 2200pF, R = 15k
17.3
(design target value)
Current Limiter Operation (RF pin)
Limiter voltage
VRF
0.225
150
0.25
0.275
V
Thermal Shutdown Protection Operation
Thermal shutdown protection
operating temperature
Hysteresis width
TSD
Design target value (Note 5)
(junction temperature)
175
35
C
C
TSD
Design target value (Note 5)
(junction temperature)
TH pin
Protection start voltage
Hysteresis width
HB pin
VTH
0.50
0.32
0.65
0.42
0.80
0.52
V
V
VTH
Output ON resistance
Output leakage current
R
(HB)
IHB = -10mA
10
20
10
ON
(HB)
I
Power saving mode V
= 15V
A
L
CC
Low Voltage Protection Circuit (detecting V
voltage)
CC
VSD
VSD
Operation voltage
7.4
7.9
0.5
8.4
V
V
Hysteresis width
0.35
0.65
FG1 FG3 Pin
Output ON resistance
Output leakage current
CTL Amplifier (drive mode)
Input voltage range
High level input voltage
R
(FG)
IFG = 5mA
VFG = 18V
40
60
10
ON
(FG)
I
A
L
V
V
V
(CTL)
(CTL)
0
4.4
V
V
V
V
IN
IH
IM
CC
HIN pin PWM ON duty 100%
HIN pin PWM ON duty 0%
4.6
4.8
Middle level input voltage 1
(At drive start)
1 (CTLI)
2.15
2.35
2.55
Middle level input voltage 2
(During drive)
V
2 (CTLI)
HIN pin PWM ON duty 0%
VCTL = 3.5V
1.9
13
2.1
25
2.3
37
V
IM
Input current
I
I
1 (CTLI)
A
IH
IH
(During drive in 120-degree
current-carrying mode)
Input current
2 (CTLI)
VCTL = 3.5V
10
20
30
A
(During drive in sine wave
current-carrying mode)
CTL Amplifier (power saving mode)
Low level input voltage
Hysteresis width
V
1 (CTL)
Power saving mode
0.75
0.15
0.95
0.35
1.15
0.55
V
V
IL
CTL
Continued on next page.
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3
LV8139JA
Continued from preceding page.
Ratings
typ
Parameter
Symbol
(FR)
Conditions
Unit
min
max
F/R Pin
High level input voltage range
Low level input voltage range
Input open voltage
V
V
V
V
3.0
0
VREG
V
V
IH
(FR)
(FR)
(FR)
0.7
0.3
0.45
65
IL
0
V
IO
IS
Hysteresis width
0.15
25
0.3
45
0
V
High level input current
Low level input current
FAULT Pin
I
I
(FR)
(FR)
VF/R = VREG
A
A
IH
IL
VF/R = 0V
-2
+2
Drive stop voltage
VFOF
VFON
0
3.0
4.6
0.5
V
V
Drive start voltage
VREG
Input open voltage
V
(FLT)
VREG
0
V
IO
High level input current
Low level input current
ADP1 Pin (drive phase adjustment)
Minimum lead angle
Maximum lead angle
I
I
(FLT)
VFAULT=VREG
VFAULT=0V
10
A
A
IH
IL
(FLT)
-200
-160
-120
Vadp01
Vadp16
ADP
VADP1 = 0V
0
58
2
2
Deg
Deg
A/A
VADP1 = VREG
56
Current ratio with the ADP2 pin
current
VCTL = 5.5V, IADP1/IADP2
1.8
2.2
ADP2 Pin (drive phase adjustment)
High level output voltage
Low level output voltage
VADP2H
VADP2L
VCTL = 5.5V
VCTL = 1.5V
2.25
0
2.45
2.65
0.3
V
V
DPL Pin (drive-phase-adjustment limit setting pin)
Lead angle limit high level voltage
Lead angle limit low level voltage
VDPLH
VDPLL
3.3
1.3
3.5
1.5
3.7
1.7
V
V
4. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance
may not be indicated by the Electrical Characteristics if operated under different conditions.
5. These are design target values and no measurements are made.
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4
LV8139JA
Package Dimensions
unit : mm (typ)
SSOP30 (275mil)
CASE 565AT
ISSUE A
SOLDERING FOOTPRINT*
(Unit: mm)
0.65
0.32
NOTE: The measurements are not to guarantee but for reference only.
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5
LV8139JA
Pdmax-Ta diagram
Pd max - Ta
1.5
Specified circuit board : 114.3 76.1 1.6mm3
×
×
glass epoxy
Mounted on a specified circuit board.
1.05
1.0
Independent IC
0.5
0.45
0.38
0.16
0
--40
--20
0
20
40
60
80
100
120
Ambient temperature, Ta --
C
Pin Assignment
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LV8139JA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Top view
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6
LV8139JA
Sample Application Circuit 1 (Hall IC, HIC)
The Hall IC to be used must be of open-collector or
open-drain output type, and it must be pulled up by
VREG5.
The type of Hall IC incorporating a pull-up resistor
cannot be used.
Furthermore, when using an element that cannot turn
off the control power while VM is being applied, the
control power must be supplied from the V
rather than from the HB pin.
pin
CC
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LV8139JA
Sample Application Circuit 2 (Hall IC, FET)
The Hall IC to be used must be of open-collector or
open-drain output type, and it must be pulled up by
VREG5.
Furthermore, when using a gate driver that cannot
turn off the control power while VM is being applied,
the control power must be supplied from the V
pin
CC
The type of Hall IC incorporating a pull-up resistor
cannot be used.
rather than from the HB pin. An element with a short
reverse recovery time must be selected as the output
FET.
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8
LV8139JA
Pin Functions
Pin No.
Pin Name
Pin function
Hall signal input pins.
Equivalent Circuit
+
-
1
2
3
4
5
6
IN1
IN1
IN2
IN2
IN3
IN3
+
The high state is when IN is greater
VREG
+
-
-
than IN , and the low state is the
reverse.
+
-
An amplitude of at least 100mVp-p
(differential) is desirable for the Hall
signal inputs. If noise on the Hall signals
is a problem, insert capacitors between
1
3
5
2
4
6
+
-
IN and IN pins.
500
500
If input is provided from a Hall IC, fix one
side of the inputs (either the “+” or “-”
side) at a voltage within the
common-mode input range (0.3V to
VREG-1.8V), and use the other input
side as an input over the 0V to VREG
range.
7
8
GND
Ground pin of the control circuit block.
V
Power supply pin for control.
Insert a capacitor between this pin and
ground to prevent the influence of noise,
etc.
CC
9
CTL
Control input pin. When CTL pin voltage
rises, the IC changes the output signal
PWM duty to increase the torque output.
In sine wave mode, Nch FET
(in equivalent circuit diagram) OFF
In 120-degree current-carrying mode,
Nch FET ON
VREG
VREG
VREG
V
CC
45k
9
86.6k
38.4k
10
DPL
Setting pin for drive phase adjustment
limit.
This pin is used to limit the lead angle of
the drive phase. The lead angle is
limited to zero degrees when the voltage
is 1.5V or lower and the limit is released
when the voltage is 3.5V or higher.
500
10
11
12
FG3
FG1
FG3 : 3-Hall FG signal output pin.
8-pole motor outputs 12 FG pulses per
one rotation. In power saving mode,
high-level is output.
11 12
25
FG1 :1-Hall FG signal output pin.
8-pole motor outputs 4 pulses per one
rotation. In power saving mode,
high-level is output.
Continued on next page.
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9
LV8139JA
Continued from preceding page.
Pin No.
13
Pin Name
ADP2
Pin function
Equivalent Circuit
Setting pin for phase drive correction.
This pin sets the amount of correction
made to the lead angle according to the
CTL input. Insert a resistor between this
pin and ground to adjust the amount of
correction.
V
CC
VREG
VREG
500
500
13
14
CSD
Pin to set the operating time of the motor
constraint protection circuit.
Insert a capacitor between this pin and
ground.
VREG
Connect this pin to ground when the
constraint protection circuit is not going
to be used.
500
500
14
15
ADP1
Drive phase adjustment pin.
VREG
V
CC
The drive phase can be advanced from
0 to 58 degrees during 180-degree
current carrying drive. The lead angle
becomes 0 degrees when 0V is input
and 58 degrees when VREG is input.
500
AD
15
500
16
CPWM
Triangle wave oscillation pin for PWM
generation.
VREG
Insert a capacitor between this pin and
ground and a resistor between this pin
and RPWM for triangle wave oscillation.
200
16
17
RPWM
Oscillation pin for PWM generation.
Insert a resistor between this pin and
CPWM.
VREG
17
Continued on next page.
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LV8139JA
Continued from preceding page.
Pin No.
18
Pin Name
FR
Pin function
Equivalent Circuit
FR
VREG
Forward/reverse rotation setting pin.
A low-level specifies forward rotation
and a high-level specifies reverse
rotation. This pin is held low when open.
2k
18 20
20
TGND
TGND
Test pin. Connect this pin to ground.
100k
19
VREG5
5V regulator output pin
V
CC
(control circuit power supply).
Insert a capacitor between this pin and
ground for power stabilization.
0.1F or so is desirable.
50
19
21
RF
Output current detection pin.
This pin is used to detect the voltage
across the current detection resistor
(Rf).
VREG
The maximum output current is
determined by the equation I
0.25V/Rf.
=
OUT
5k
21
22
TH
Thermistor connection pin.
VREG
The thermistor detects heat generated
from HIC and turns off the drive output
when an overheat condition occurs.
All the HIN/LIN output pins are set to low
at a pin voltage of 0.6V or less.
500
22
* For further details, refer to “Description
of LV8139JA.”
Continued on next page.
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LV8139JA
Continued from preceding page.
Pin No.
23
Pin Name
FAULT
Pin function
Equivalent Circuit
HIC protection signal input pin.
This pin accepts an error mode
VREG
detection signal generated by the HIC
side.
30k
500
With a low-level input, the error mode
detection condition is established, and
all the HIN/LIN output pins are set to low.
23
* For further details, refer to “Description
of LV8139JA.”
24
25
26
LIN3
LIN2
LIN1
LIN1, LIN2, and LIN3 :
VREG
L side drive signal output pin.
Generate 0 to VREG push-pull outputs.
27
28
29
HIN3
HIN2
HIN1
HIN1, HIN2, and HIN3 :
24 27
25 28
26 29
H side drive signal output pin.
Generate 0 to VREG push-pull outputs.
500
30
HB
Hall bias HIC power supply pin.
Insert a capacitor between this pin and
ground.
V
CC
This pin is set to high-impedance state
in power saving mode. By supplying Hall
bias and HIC power using this pin, the
power consumption by Hall bias and
HIC in power saving mode can be
reduced to zero.
30
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12
LV8139JA
+
-
Timing Chart (IN = “H”indicates the state in which IN is greater than IN .)
(1) F/R pin = L
Normal Hall input Lead Angle=0
IN1+
IN1-
IN2+
IN1-
IN3+
IN1-
IN1
IN2
IN3
H
L
H
L
L
H
H
L
L
H
L
L
H
H
L
L
H
L
H
L
L
H
H
L
L
H
L
L
H
H
L
L
H
H
H
H
F/R="L" 120 energization
ON
HIN1
PWM
PWM
OFF
U
V
OFF
LIN1
ON
ON
HIN2
PWM
PWM
PWM
OFF
OFF
LIN2
ON
ON
HIN3
PWM
PWM
OFF
OFF
W
LIN3
ON
F/R="L" sin wave drive method
Max Duty
UOUT
H Duty
0%
Max Duty
VOUT
H Duty
0%
Max Duty
WOUT
H Duty
0%
F/R="H" 120 energization in reverse rotate
ON
HIN1
PWM
PWM
OFF
U
V
OFF
LIN1
ON
ON
HIN2
PWM
PWM
OFF
OFF
LIN2
ON
ON
HIN3
PWM
PWM
OFF
W
OFF
ON
LIN3
3 Hall FG
1 Hall FG
The energization is switched to 120 wher 3 Hall FG
If the motor rotates in reverse against F/R pin input 120
frequency is 5.15Hz (typ) or lower
A direction of rotation is detected from Hall signal
according to F/R pin input
energization is maintained forcibly
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LV8139JA
(2) F/R pin = H
Reverse Hall input Lead Angle=0
IN1+
IN1-
IN2+
IN1-
IN3+
IN1-
IN1
IN2
IN3
L
L
L
H
H
L
H
L
H
H
L
H
L
L
H
L
L
L
L
H
H
L
H
L
H
H
L
H
L
L
H
L
H
H
H
H
F/R="H" 120 energization
ON
HIN1
PWM
PWM
OFF
U
V
OFF
LIN1
ON
ON
HIN2
OFF
PWM
PWM
OFF
LIN2
ON
ON
HIN3
PWM
PWM
OFF
OFF
W
LIN3
ON
F/R="H" sin wave drive method
Max Duty
UOUT
H Duty
0%
Max Duty
VOUT
H Duty
0%
Max Duty
WOUT
H Duty
0%
F/R="L" 120 energization in reverse rotate
ON
HIN1
PWM
PWM
OFF
U
V
OFF
LIN1
ON
ON
HIN2
PWM
PWM
OFF
OFF
LIN2
ON
ON
HIN3
LIN3
PWM
PWM
OFF
OFF
W
ON
3 Hall FG
1 Hall FG
The energization is switched to 120 wher 3 Hall FG
frequency is 5.15Hz (typ) or lower
If the motor rotates in reverse against F/R pin input 120
energization is maintained forcibly
A direction of rotation is detected from Hall signal
according to F/R pin input
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LV8139JA
Functional Description
Basic operation of 120-degree Sine wave
current-carrying switching
Concerning the Hall signal input sequence
This IC controls the motor rotation direction
At startup, this IC starts at 120-degree
current-carrying. The current-carrying is switched to
sine wave when the 3-Hall FG frequency is 5.15Hz
(typ) or above and the rising edge of the IN2 signal has
been detected twice in succession.
commands and Hall signal input sequence in order to
set the lead angle. If the motor rotation direction
commands and Hall signal input sequence do not
conform to what is shown on the timing chart, the
motor is driven by 120-degree current-carrying.
Shown below are two Hall signal input sequences.
Sequence 1 : When the Hall signal has been input with the following logic
IN1
IN2
IN3
H
L
H
H
L
L
H
H
L
L
H
L
L
H
H
L
L
H
When F/R pin input is high 120-degree current-carrying
When F/R pin input is low 180-degree current-carrying
Sequence 2 : When the Hall signal has been input with the following logic
IN1
IN2
IN3
H
L
H
L
L
H
L
H
H
L
H
L
H
H
L
H
L
L
When F/R pin input is high 180-degree current-carrying
When F/R pin input is low 120-degree current-carrying
CTL pin input
a) Power-saving mode V
* When the PWM oscillation frequency setting is
17kHz, the maximum duty ratio in the 120-degree
current carrying mode is 88% (typ).
V (0.95V : typ)
IL
CTL
L 1 to L 3 and H 1 to H 3 outputs all set to
IN IN IN IN
low
I
= 0, HB pin = OFF
The CTL pin is pulled down by 170k (120-degree
mode) : Typ, 131.6k (sine wave mode) : typ inside
the IC. Caution is required when the control input
voltage input is subjected to resistance division, for
example.
CC
The power consumption of the IC can now be set to
0, and the power consumption of the Hall element
connected to the HB pin and the output block can
also be set to 0.
b) Standby mode While stopped: V V
IL
Bootstrap capacitor initial charging mode
CTL
V
1 (2.33V: typ); while running: V V
2 (2.1V: typ)
When the mode is switched from the power-saving
mode to the standby mode and then to the drive mode,
the IC enters the bootstrap capacitor charging mode
IM
IM
IL CTL
V
The U 1 to 3 outputs are set to low, and the
IN
bootstrap charge pulse (pulse width: 2.5s: design
(H 1, H 2, H 3 pins = L L 1, L 2, L 3 pins
IN IN IN IN IN IN
target) is output to the L 1 to 3 outputs in
= H 4.55ms typ) in order to charge the bootstrap
capacitor.
IN
preparation for drive start.
c) Drive mode At drive start: V 1 V
IM
7V;
CTL
during drive: V 2 V
7V (V 4.7V: typ)
IM
CTL
IH
The motor is driven at the PWM duty ratio that
corresponds to V . When V is increased,
CTL
the PWM duty ratio increases, and the maximum
duty ratio is established at “V .”
CTL
IH
d) Test mode 8.5V V
V
CTL
CC
When the CTL pin voltage is 8V or higher, the IC
enters the test mode, and the motor is driven at the
120-degree current-carrying and maximum duty*
ratio.
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LV8139JA
Drive phase adjustment
the resistance levels of resistors connected to the
During 180-degree current-carrying drive, any lead
angle from 0 to 58 degrees can be set using the ADP1
pin voltage (lead angle control). This setting can be
adjusted in 32 steps (in 1.875-degree increments) from
0 to 58 degrees using the ADP1 pin voltage, and it is
updated every Hall signal cycle (it is sampled at the
rising edge of the IN3 input and updated at its falling
edge).
ADP1 pin, ADP2 pin and DPL pin. When these pins
are not going to be used, reference must be made to
section 4.5, and the pins must not be used in the open
status. Furthermore, a resistance of 47k or more
must be used for the resistor (RADP2) that is
connected to the ADP2 pin.
1. The slopes of V
and VADP1 can be adjusted by
CTL
A number of lead angle adjustments proportionate to
the CTL pin voltage can be undertaken by adjusting
setting the resistance level of the resistor (RADP1)
connected to ADP1 (pin 15).
VADP1, VADP2[V]
58° VREG
ADP1(RADP1=47k)
VREG5
RDPL1 33k
IADP2
IADP1
ADP2
ADP1(RADP1=22k)
VADP2H
2.34V
47k RADP2
RADP1
VADP2=(VCTL-VIM2)×(2.5/(VIH-VIM2))
=(VCTL-2.1V)×(2.5/(4.6V-2.1V))
IADP2=VADP2/RADP2
IADP1=IADPR×IADP2
VADP1=IADP1×RADP1
0°
0V
VCTL[V]
VIM2(typ:2.1V)
VIH(typ:4.6V)
2. The ADP2 pin rise can be halted (a limit on the lead
angle adjustment can be set by means of the CTL
voltage) by setting DPL (pin 10).
VADP1, VADP2[V]
58° VREG
VREG5
RDPL1 33k
DPLLIM
IADP2
IADP1
2.46V
ADP1(RADP1=47k)
RDPL2 33k 47k RADP2
RADP1
VADP2=(VCTL-VIM2)×(2.5/(VIH-VIM2))
IADP2=VADP2/RADP2
1.23V
1.17V
ADP2
ADP1(RADP1=22k)
IADP1=IADPR×IADP2
VADP1=IADP1×RADP1
DPLLIM=VDPL×1.36
0°
0V
VCTL[V]
VIM2(typ:2.1V)
3.33V
VIH(typ:4.6V)
3. The offset and slope can be adjusted as desired by
setting RADP1 and RADP12 of ADP1 (pin 15). (It
is also possible to set a limit on the lead angle
adjustment by means of the CTL voltage by setting
DPL.)
VADP1, VADP2[V]
ADP1
58° VREG
(RADP1=47k,RADP12=220k)
VREG5
VREG5
ADP1
4.17V
(RADP1=33k,RADP1=33k)
RDPL1 33k
RADP12
IADP2
IADP1
VADP2H
0.86V
ADP2
47k RADP2
RADP1
VADP2=(VCTL-VIM2)×(2.5/(VIH-VIM2))
IADP2=VADP2/RADP2
IADP1=IADPR×IADP2
VADP1=((RADP1×RADP12)/(RADP1+RADP12))×IADP1
+(RADP1/(RADP1+RADP12))×VREG
0°
0V
VCTL[V]
VIM2(typ:2.1V)
VIH(typ:4.6V)
4. When the lead angle is not adjusted
ADP1 pin: shorted to ground; ADP2 pin and DPL
pin: pulled down to ground using the resistors
5. When the lead angle is not adjusted by means of the
CTL pin voltage (for use with a fixed lead angle)
ADP1 pin: lead angle setting by resistance division
from VREG5; ADP2 pin and DPL pin: pulled down
to ground by the resistors
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LV8139JA
Description of LV8139
1. Current Limiter Circuit
The current limiter circuit limits the output current
4. Constraint Protection Circuit
peak value to a level determined by the equation I =
A constraint protection circuit is incorporated in
order to protect the output elements and motor when
the motor is constrained. The circuit is activated
when the Hall signal is not switched for a specific
period of time when the motor is in operation. The
counter is reset each time the motor rotates 360
degrees in terms of the electrical angle.
V
/Rf (where V = 0.25V typ, Rf is the value of
RF
RF
the current detection resistor). The current limiter
operates by reducing the H output on duty to
IN
suppress the current.
The current limiter circuit detects the reverse
recovery current of the diode due to PWM operation.
To assure that the current limiting function does not
malfunction, its operation has a delay of approx. 1s.
If the motor coils resistance or a low inductance,
current fluctuation at startup (when there is no back
electromotive force in the motor) will be rapid. The
delay in this circuit means that at such times the
current limiter circuit may operate at a point well
above the set current. Application must take this
increase in the current due to the delay into account
when the current limiter value is set.
All the H and L outputs are set to the low level
IN IN
when the constraint protection circuit is in operation.
This time is determined by the capacitance of the
capacitor connected to the CSD pin.
Oscillation time of CSD pin (1 pulse) T =
(V -V )/ICHG1 C (F) +
OH OL
(V -V )/ICHG2 C (F)
OH OL
Constraint protection detection time T1 (s) = T 256
(count)
Constraint protection time T2 (s) = T 2816 (count)
2. Power Saving Circuit (CTL pin)
This IC goes into the power saving mode that stops
operation of all the circuits to reduce the power
consumption. If the HB pin is used for the Hall
element bias and the output block, the current
consumption in the power-saving mode is zero.
When a 0.022F capacitor is attached, T = 8.36ms,
T1 = 2.14s and T2 = 23.54s are established as the
typical ratings. After the motor has been constrained,
the constraint protection state is established at 2.14
(s), and then after 23.54 (s) has elapsed, the constraint
protection circuit is reset automatically. A time that
provides some leeway in the motor start time that
factors in any fluctuations must be selected as the
setting.
3. Hall Input Signal
Signals with an amplitude in excess of the hysteresis
is required for the Hall inputs. However, considering
the influence of noise and phase displacement, an
amplitude of over 100mV is desirable.
If noise disrupts the output waveform, this must be
prevented by inserting capacitors or other devices
across the Hall inputs. The Hall inputs are used by the
circuit inside the IC as decision signals so if noise
enters, a malfunction occurs in the operation.
Although the circuit is designed to tolerate a certain
amount of noise, care is required.
Conditions for releasing the constraint protection
state other than by automatic resetting:
When CTL pin voltage V 2 input
IM
protection release and CSD count reset
When the low level is detected on the TH pin
protection release and CSD count reset
When FR has been switched protection release
and CSD count reset
Furthermore, when the Hall signal amplitude has
changed as a result of a change in temperature, the
drive phase may possibly shift due to the Hall
amplifier hysteresis. It is the user who is responsible
for giving due consideration to this aspect. Use of a
Hall IC is recommended unless there is a reason not
to use one.
When TSD protection is detected CSD count
stop
5. Power Supply Stabilization
Since this IC adopts a switching drive technique, the
power-supply line level can be disrupted easily. Thus
capacitors large enough to stabilize the power supply
If all three phases of the Hall input signal go to the
same input state (HHH or LLL), all the HIN/LIN
outputs are set to low.
If the outputs from a Hall IC are used, fix one side of
the inputs (either the “+” or “−” side) at a voltage
within the common-mode input voltage range (0.3V
to VREG–1.8V), and use the other input side as an
input over the 0V to VREG range.
voltage must be inserted between the V
pins and
CC
ground. If the electrolytic capacitors cannot be
connected close to their corresponding pins, ceramic
capacitors of about 0.1F must be connected near
these pins.
If diodes are inserted in the power-supply line to
prevent destruction of the device when the power
supply is connected with reverse polarity, the power
supply line levels will be even more easily disrupted,
and even larger capacitors must be used.
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LV8139JA
6. VREG Stabilization
The drive phase is shifted.
Connect a capacitor with a capacitance of 0.1F or
more between VREG5 and ground in order to
stabilize the VREG voltage that is the power supply
of the control circuit.
The ground lead of that capacitor must be located as
close as possible to the control system ground
(SGND) of the IC.
The motor has been suddenly accelerated.
The output duty ratio has been decreased sharply
while the motor is running.
If the output duty ratio has been decreased sharply, it
is highly likely that current will return to the motor
power supply.
The extent to which the motor supply voltage
increases differs depending on the size of the
capacitors used in the product that incorporates the
motor, the size of the capacitor inserted between the
motor power supply and ground on the motor circuit
board and the motor used; as such, it is the user who
is responsible for giving due consideration to this
aspect.
7. Forward/Reverse Switching (F/R pin)
Switching between forward rotation and reverse
rotation must not be undertaken while the motor is
running.
8. TH Pin
The TH pin must normally be pulled up to VREG5
for use. When this pin has been set to low, all the
It is necessary to take remedial action such as
increasing the capacitance of the capacitors or
reducing the speed at which the duty ratio will be
reduced when the motor supply voltage rises to
ensure that the maximum withstand voltage of the
element used for output is not exceeded.
H
/L outputs are set to low. When reset is
IN IN
initiated, the bootstrap initial charging mode is
established.
9. FAULT Pin
The FAULT pin must normally be pulled up to
VREG5 for use. When this pin has been set to low, all
the H /L outputs are set to low. When reset is
IN IN
initiated, the bootstrap initial charging mode is
established.
All the outputs are set to low. In addition, the
FG1/FG3 output goes off, too. When reset is initiated,
the bootstrap initial charging mode is established.
10. PWM Frequency Setting
fCPWM 1/ (1.7CR)
Components with good temperature characteristics
must be used.
An oscillation frequency of about 17kHz is obtained
when a 2200pF capacitor and 15k resistor are used.
If the PWM frequency is too low, switching noise
will be heard from the motor; conversely, if it is too
high, the output power loss will increase. For this
reason, a frequency between 15kHz and 30kHz or so
is desirable. The capacitor ground must be connected
as close as possible to the control system ground
(SGND pin) of the IC to minimize the effects of the
outputs.
If there are no fluctuations in the capacitance or
resistance of the external capacitors or resistors and
only the IC fluctuations are to be considered, an
actual capability of 3% can be expected.
11.Concerning the power-raising operation
This IC provides sine wave PWM drive so it
performs operations similar to synchronous
rectification. These operations are such that current is
sometimes returned to the motor power supply side
depending on the conditions of use. For instance, this
may happen when:
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LV8139JA
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