LV8112V_1002 [SANYO]
For Polygon Mirror Motor 3-phase Brushless Motor Driver; 对于多面体反射镜电机的3相无刷电机驱动器
| 型号： | LV8112V_1002 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | For Polygon Mirror Motor 3-phase Brushless Motor Driver |
| 文件： | 总13页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1645A
Bi-CMOS IC
For Polygon Mirror Motor
LV8112V
3-phase Brushless Motor Driver
Overview
The LV8112V is a 3-phase brushless motor driver for polygon mirror motor driving of LBP.
A circuit needed to drive of polygon mirror motor can be composed of a single-chip. Also, the output transistor is made
DMOS by using BiDC process, and by adopting the synchronous rectification method, the lower power consumption
(Heat generation) is achieved.
Features
• 3-phase bipolar drive
• Full complement of on-chip protection circuits, including lock
protection, current limiter, under-voltage protection, and thermal
shutdown protection circuits
• Circuit to switch slowing down method while stopped
(Free run or Short-circuit brake)
• Direct PWM drive + synchronous rectification
• I max1 = 2.5A
O
• I max1 = 3.0A (t ≤ 0.1ms)
O
• Output current control circuit
• PLL speed control circuit
• Constraint protection detection signal switching circuit (FG or LD)
• Phase lock detection output (with mask function) • Forward / Reverse switching circuit
• Compatible with Hall FG
• Hall bias pin (Bias current cut in a stopped state)
• SDCC (Speed Detection Current Control) function
• Provides a 5V regulator output
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage
V
max
V
pin
CC
37
42
CC
VG max
VG pin
*1
V
Output current
I
I
max1
max2
2.5
A
O
O
t ≤ 0.1ms *1
3.0
A
Allowable Power dissipation
Operation temperature
Storage temperature
Pd max
Topr
Mounted on a specified board *2
1.7
W
°C
°C
°C
-25 to +80
-55 to +150
150
Tstg
Junction temperature
Tj max
*1. Tj max = 150°C must not be exceeded.
*2. Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
30310 SY / 11310 SY 20091224-S00004 No.A1645-1/13
LV8112V
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage range
V
I
10 to 35
0 to -30
0 to 5
CC
5V constant voltage output current
LD pin applied voltage
LD pin output current
mA
V
REG
V
LD
FG
HB
I
0 to 15
0 to 5
mA
V
LD
FG pin applied voltage
FG pin output current
V
I
0 to 15
0 to 5
mA
V
FG
HB pin applied voltage
HB pin output current
V
I
0 to -30
mA
HB
Electrical Characteristics at Ta = 25°C, V
= 24V
CC
Ratings
typ
Parameter
Symbol
1
Conditions
Unit
min
max
6.5
Current drain
I
I
5.5
mA
mA
CC
2
In a stop state
1.0
1.5
CC
5V Constant Voltage Output
Output voltage
VREG
4.65
5.0
20
25
0
5.35
100
60
V
mV
Line regulation
ΔVREG1
ΔVREG2
ΔVREG3
V
= 10 to 35V
CC
= -5 to -20mA
Load regulation
I
mV
O
Temperature coefficient
Output Block
Design target value *
mV/°C
Output ON resistance
R
I
= 1A , Sum of the lower and upper side
O
1.5
1.9
Ω
ON
outputs
Output leakage current
Lower side Diode forward voltage
Upper side Diode forward voltage
Charge Pump Output (VG pin)
Output voltage
I
leak
1
Design target value *
10
1.35
1.35
μA
V
O
V
I
I
= -1A
= 1A
1.0
1.0
D
D
D
V
2
V
D
VG
OUT
V
+4.9
V
CC
CP1 pin
Output ON resistance (High level)
Output ON resistance (Low level)
Hall Amplifier Block
V
(CP1)
OH
I
I
= -2mA
= 2mA
500
300
700
400
Ω
Ω
CP1
CP1
V (CP1)
OL
Input bias current
I
(HA)
-2
0.5
80
-0.5
μA
V
HB
Common mode input voltage range
Hall input sensitivity
V
VREG-2.0
42
ICM
mVp-p
mV
Hysteresis
ΔV (HA)
IN
15
24
12
Input voltage L → H
V
mV
SLH
SHL
Input voltage H → L
V
-12
mV
Hall Bias (HB pin) P-channel Output
Output voltage ON resistance
Output leakage current
FG Amplifier Schmitt Block (IN1)
Input amplifier gain
V
(HB)
I
= -20mA
= 0V
20
30
10
Ω
OL
HB
I (HB)
L
V
μA
O
G
Design target value *
5
0
times
mV
FG
Input hysteresis (H → L)
Input hysteresis (L → H)
hysteresis
V
V
V
(FGS) Input referred, Design target value *
(FGS) Input referred, Design target value *
Input referred, Design target value *
SHL
SLH
FGL
10
10
mV
mV
FGFIL pin
High level output voltage
Low level output voltage
External capacitor charge current
External capacitor discharge current
Amplitude
V
(FGFIL)
OH
2.7
0.75
-5
3.0
0.85
-4
3.3
0.95
-3
V
V
V
(FGFIL)
OL
I
I
1
2
V
V
1 = 1.5V
2 = 1.5V
μA
μA
Vp-p
CHG
CHG
CHG
CHG
3
4
5
V(FGFIL)
1.95
2.15
2.35
* Design target value, Do not measurement.
Continued on next page.
No.A1645-2/13
LV8112V
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
FG Output
Output ON resistance
Output leakage current
PWM Oscillator
V
(FG)
I
= 7mA
= 5V
O
20
30
10
Ω
OL
FG
I (FG)
V
μA
L
High level output voltage
Low level output voltage
External capacitor charge current
Oscillation frequency
Amplitude
V
(PWM)
OH
2.95
3.2
1.5
-70
225
1.7
3.45
1.7
V
V
V
(PWM)
1.3
-90
180
1.5
15
OL
I
(PWM)
V
= 2V
PWM
-50
270
1.9
μA
CHG
f(PWM)
C = 150pF
kHz
Vp-p
kHz
V(PWM)
Recommended operation frequency
range
f
300
OPR
CSD Oscillation Circuit
High level output voltage
Low level output voltage
Amplitude
V
(CSD)
OH
2.7
0.8
1.75
-14
8
3.0
1.0
2.0
-10
11
3.3
1.2
2.25
-6
V
V
V
(CSD)
OL
V(CSD)
Vp-p
μA
μA
Hz
External capacitor charge current
External Capacitor Discharge Current
Oscillation frequency
I
I
1(CSD)
2(CSD)
V
V
1 = 2.0V
CHG
CHG
CHG
CHG
2 = 2.0V
14
f(CSD)
C = 0.068μF,Design target value *
30
40
50
Phase comparing output
Output ON resistance (high level)
Output ON resistance (low level)
Phase Lock Detection Output
Output ON resistance
Output leakage current
Error Amplifier Block
Input offset voltage
V
V
I
I
= -100μA
= 100μA
500
500
700
700
Ω
Ω
PDH
OH
OL
PDL
V
(LD)
I
= 10mA
= 5V
O
20
30
10
Ω
OL
LD
I (LD)
V
μA
L
V
(ER)
IO
Design target value *
-10
-1
+10
+1
mV
μA
V
Input bias current
I (ER)
B
High level output voltage
Low level output voltage
DC bias level
V
(ER)
OH
I
I
= -100μA
= 100μA
EI+0.7
EI-1.75
-5%
EI+0.85
EI-1.6
EI+1.0
EI-1.45
5%
OH
OL
V (ER)
OL
V
V (ER)
B
VREG/2
V
Current Control Circuit
Drive gain
GDF
While phase locked
0.5
0.55
0.6
times
V
Current Limiter Circuit (pins RF and RFS)
Limiter voltage
V
0.465
0.515
0.565
RF
Under-voltage Protection
Operation voltage
VSD
8.3
0.2
8.7
9.1
0.5
V
V
Hyteresis
ΔVSD
0.35
CLD Circuit
External capacitor charge current
Operation voltage
I
V
= 0V
-4.5
-3.0
3.5
-1.5
μA
CLD
(CLD)
CLD
V
3.25
3.75
V
H
Thermal Shutdown Operation
Thermal shutdown operation
temperature
TSD
Design target value (Junction temperature)
Design target value (Junction temperature)
150
175
30
°C.
°C
Hysteresis
ΔTSD
CLK pin
External input frequency
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
f (CLK)
I
0.1
10
VREG
1.0
kHz
V
V
V
V
V
(CLK)
2.0
IH
(CLK)
0
VREG-0.5
0.2
V
IL
(CLK)
VREG
0.4
V
IO
(CLK)
IS
0.3
0
V
High level input current
Low level input current
I
I
(CLK)
IH
V
V
= VREG
= 0V
-10
+10
μA
μA
CLK
(CLK)
IL
-110
-85
-60
CLK
* Design target value, Do not measurement.
Continued on next page.
No.A1645-3/13
LV8112V
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
CSDSEL pin
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
S/S pin
V
V
V
(CSD)
2.0
0
VREG
1.0
V
V
IH
(CSD)
IL
(CSD)
IO
VREG-0.5
-10
VREG
+10
V
I
I
(CSD)
IH
V
V
= VREG
0
μA
μA
CSD
(CSD)
= 0V
-110
-85
-60
IL
CSD
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
V
V
V
V
(SS)
2.0
VREG
1.0
V
V
IH
(SS)
(SS)
0
VREG-0.5
0.2
IL
VREG
0.4
V
IO
(SS)
IS
0.3
0
V
High level input current
Low level input current
BRSEL pin
I
I
(SS)
IH
V
V
= VREG
=0V
-10
+10
μA
μA
S/S
(SS)
IL
-110
-85
-60
S/S
High level input voltage
Low level input voltge
Input open voltage
High level input current
Low level input current
F/R pin
V
V
V
(BRSEL)
2.0
0
VREG
1.0
V
V
IH
(BRSEL)
(BRSEL)
IL
VREG-0.5
-10
VREG
+10
V
IO
I
I
(BRSEL)
IH
V
V
= VREG
= 0V
0
μA
μA
BRSEL
(BRSEL)
-110
-85
-60
IL
BRSEL
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
V
V
V
(FR)
2.0
0
VREG
1.0
V
V
IH
(FR)
IL
(FR)
VREG-0.5
-10
VREG
+10
V
IO
I
I
(FR)
IH
V
V
= VREG
0
μA
μA
F/R
F/R
(FR)
IL
= 0V
-110
-85
-60
No.A1645-4/13
LV8112V
Package Dimensions
unit : mm (typ)
3333
TOP VIEW
SIDE VIEW
BOTTOM VIEW
15.0
44
23
(4.7)
1
22
0.65
0.22
0.2
(0.68)
SIDE VIEW
SANYO : SSOP44K(275mil)
Pd max -- Ta
2.0
1.7
1.5
1.0
0.5
0
0.95
-25
0
25
50
75 80
100
Ambient temperature, Ta -- C
Pin Assignment
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
LV8112V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
Top view
No.A1645-5/13
LV8112V
Block Diagram and Application Circuit Example
PWM
CSDSEL
CSD
PD
EI
CSDSEL
CSD
OSC
PWM
OSC
COUNT
LOGIC
LOGIC
VREG
BRSEL
S/S
BRSEL
S/S
EO
TOC
CONT
AMP
COMP
FC
PH
F/R
F/R
PEAK
HOLD
TSD
LD output
LD
LD
CLD
LD
MASK
VREG
VREG
V
CC
PLL
LVDS
V
V
1
2
CC
CLK input
FG output
CLK
FG
CC
CLK
CNTROL
CIRCUIT
VG
FG
CHARGE
PUMP
CP1
CP2
FGFIL
FILTER
OUT1
OUT2
DRIVER
CURR
LIM
HALL HYS AMP
HB
OUT3
SUB
+
−
+
−
+
−
IN3
IN1
IN1
IN2
IN2
IN3
HB
RFS
RF
GND GND2
No.A1645-6/13
LV8112V
Pin Function
Pin No. Pin name
Function
Equivalent circuit
1
CLK
Clock input pin (10kHz maximum)
VREG
55kΩ
10kΩ
5kΩ
1
2
LD
Phase lock detection output pin.
Goes ON during PLL-phase lock.
Open drain output.
VREG
2
3
S/S
Start/Stop input pin.
VREG
START with a low-level input.
STOP with a high-level input or open input
55kΩ
10kΩ
5kΩ
3
4
5
6
VREG
5V regulator output pin.
V
CC
(the control circuit power supply)
50Ω
Connect a capacitor between this pin and GND for
stabilization.
4
BRSEL
Brake selection pin.
VREG
By low level, short-circuit braking when the S/S pin is in a
stopped state.
(Brake for the inspection process)
55kΩ
5kΩ
5
CSDSEL
Motor constraint protection detection signal selection pin.
Select FG with low,
VREG
and LD with high or in an open state.
55kΩ
5kΩ
6
Continued on next page.
No.A1645-7/13
LV8112V
Continued from preceding page.
Pin No. Pin name
Function
Equivalent circuit
7
8
9
F/R
Pin to select Forward / Reverse.
(Pin to select SDCC function)
VREG
55kΩ
5kΩ
7
CLD
Pin to set phase lock signal mask time.
VREG
Connect a capacitor between this pin and GND.
If there is no need for masking, this pin must be left open.
500Ω
8
2kΩ
CSD
Pin for both the constraint protection circuit operation time
and the initial reset pulse setting.
VREG
Connect a capacitor between this pin and GND.
If the motor constraint protection circuit is not used,
a capacitor and a resistor must be connected in parallel
between the CSD pin and GND.
500Ω
9
10
FG
FG Schmitt output pin.
Open drain output.
VREG
10
12
PWM
Pin to set the oscillation frequency of PWM.
Connect a capacitor between this pin and GND.
VREG
200Ω
12
2kΩ
14
FC
Frequency characteristics correction pin of the current
limiter circuit.
VREG
Connect a capacitor between this pin and GND.
500Ω
14
110kΩ
Continued on next page.
No.A1645-8/13
LV8112V
Continued from preceding page.
Pin No. Pin name
Function
Equivalent circuit
15
FGFIL
FG filter pin.
VREG
When the noise of the FG signal is a problem, connect a
capacitor between this pin and GND for stabilization.
15
16
PH
Pin to stabilize the RF waveform.
VREG
Connect a capacitor between this pin and GND.
500Ω
16
10kΩ
17
PD
Phase comparison output pin.
VREG
The phase error is output by the duty changing of the pulse.
500Ω
17
18
EI
Error amplifier input pin.
VREG
500Ω
18
19
EO
Error amplifier output pin.
VREG
19
100kΩ
20
TOC
Torque command voltage input pin.
VREG
Normally, this pin must be connected with the EO pin.
20
21
GND
Ground pin of the control circuit block.
Continued on next page.
No.A1645-9/13
LV8112V
Continued from preceding page.
Pin No. Pin name
Function
Hall element bias current pin.
Goes ON when the S/S pin is in a start state.
Goes OFF when the S/S pin is in an stopped state.
Equivalent circuit
22
HB
VREG
22
+
−
+
−
+
−
23
24
25
26
27
28
IN1
IN1
IN2
IN2
IN3
IN3
Hall amplifier input pin.
VREG
+
−
A high level state of logic is recognized when IN > IN .
In reverse case is a low-level state.
The input amplitude of 100mVp-p or more (differential) is
desirable in the Hall sensor inputs.
500Ω
500Ω
If noise on the Hall inputs is a problem, that noise must be
excluded by inserting capacitors across the inputs.
24 26 28
23 25 27
29
30
SUB
Frame ground pin. This pin is connected with the GND2 pin.
Ground pin of the output circuit block.
GND2
32
34
36
OUT3
OUT2
OUT1
Output pin.
V
CC
As for PWM, Duty control is executed on the upper- side
FET.
32 34 36
38
39
RF
Source pin of output MOSFET (lower-side).
38
Connect a low resistance (Rf) between this pin and GND.
RFS
Output current detection pin.
Connect to RF pin.
VREG
5kΩ
39
40
V
V
2
1
Power supply pin.
CC
Connect a capacitor between this pin and GND for
stabilization.
41
42
Power supply pin for control.
CC
VG
Charge pump output pin (Power supply for the upper side
FET gate).
V
CC
Connect a capacitor between this pin and V
.
CC
500Ω
44
100Ω
43
44
CP1
CP2
Pin to connect a capacitor for charge pump.
Connect a capacitor between CP1 and CP2.
42
43
No.A1645-10/13
LV8112V
+
−
3-phase Logic Truth Table (IN = “H” indicates the state where in IN > IN )
F/R = H
F/R = L
Output
IN1
H
H
H
L
IN2
L
IN3
H
L
IN1
L
IN2
H
H
L
IN3
L
OUT1
OUT2
OUT3
L
L
H
M
L
M
H
H
M
L
L
L
H
H
H
L
H
H
H
L
L
L
M
H
H
M
L
H
H
H
L
L
L
H
H
L
M
H
L
H
L
L
S/S Pin
BRSEL Pin
Input state
High or Open
Low
Input state
Mode
Stop
Start
While stopped
High or Open
Low
Free run
Short-circuit brake
CSDSEL Pin
Input state
SDCC Select
Input state
Mode
Mode
High or Open
Low
LD standard
FG standard
F/R = High or Open
F/R = Low
Function ON
Function OFF
LV8112V Description
1. Speed Control Circuit
This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method.
This the PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls
by using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency.
f
(Servo) = f
CLK
FG
2. Output Drive Circuit
This IC adopts the direct PWM drive method to reduce power loss in the output. The output transistor is always
saturated while the transistor is on and adjusts the driving force of the motor by changing the duty that the output
transistor is on.
The PWM switching of the output is performed by the upper-side output transistor.
Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off.
But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification.
3. Current Limiter Circuit
This IC limits the (peak) current at the value
I = V / Rf (V = 0.515V (typical), Rf : current detection resister)).
RF RF
The current limitation operation consists of reducing the PWM output on duty to suppress the current.
To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the
operation has a delay (approximately 300ns). In case of a coil resistance of motor is small or small inductance, since
the current change at start-up is fast, there is a possibility that the current more than specified current is flowed by this
delay.
It is necessary to set the current increases by the delay.
4. Power Saving Circuit
This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the
majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state.
5. Reference Clock
Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis.
But, if noise is a problem, that noise must be excluded by inserting capacitors across the inputs.
If clock input goes to the no input state when the IC is in the start state, the drive is turned off after a few rotation of
motor if the motor constrained protection circuit does operate. (Clock disconnection protection)
No.A1645-11/13
LV8112V
6. PWM Frequency
The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin.
…
…
f
f
≈ 1 / (29500 × C ) 150pF or more
PWM
PWM
≈ 1 / (32000 × C ) 100pF or more, less than 150pF
The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected.
The GND of a capacitor must be placed as close to the control block GND (GND pin ) of the IC as possible to reduce
influence of the output.
7. Hall Effect Sensor Input Signals
The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs.
Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise.
If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting
capacitors across the inputs.
8. FG Signals
The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be
excluded by inserting a capacitor between the FGFIL pin and GND.
Note that normal operation becomes impossible if the value of the capacitor is overlarge. Also, note that the trouble of
noise occurs easily when the position of GND of a capacitor is incorrect.
9. Constraint Protection Circuit
This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. when the
CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed
period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed
period in the start state, this circuit is operates. Also, the upper-side output transistor is turned off while the constraint
protection circuit is operating. This time is set by the capacitance of the capacitor attached to the CSD pin.
The set time (in seconds) is 102 × C (μF)
When a capacitor of 0.068μF is attached, the protection time becomes about 7.0 seconds.
The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the
clock frequency, this protection circuit is not operated. To clear the motor constrained state, the S/S pin is switched
into a stop state or the power must be turned off and reapplied. Since the CSD pin also functions as the power-on reset
pin, if the CSD pin were connected directly to ground, the logic circuit goes to the reset state and the speed cannot be
controlled.
Therefore, if the motor constraint protection circuit is not used, a resistor of about 220kΩ and a capacitor of about
4700pF must be connected in parallel between the CSD pin and GND.
10. Phase Lock Signals
(1) Phase lock range
This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the
characteristics of the IC. ( because the accelerations of the change in FG frequency influences.)
When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating
must be measured. Since the speed error occurs easily when the accelerations of FG is large, the speed error will be
the largest when the IC goes into the lock state during start-up or the unlocked state by switching the clock.
(2) Phase lock signal mask functions
When the IC goes into the lock state during start-up or the unlocked state by switching the clock, the low signal for a
short-time by using the hunting when the IC goes into the locked state is masked. Therefore, the lock signal is output
in stable state. But, the mask time duration causes the delay of the lock signal output. The mask time is set by the
capacitance of the capacitor attached between the CLD pin and GND.
The mask time (seconds) is 1.8 × C (μF)
When a capacitor of 0.1μF is attached, the mask time becomes about 180ms.
If the signals should be masked completely, the mask time must be set well in advance.
When there is no need for masking, the CLD pin must be left open.
No.A1645-12/13
LV8112V
11. Power Supply Stabilization
Since this IC is used in applications that draw large output currents and adopts the drive method by switching, the
power-Supply line is subject to fluctuations. Therefore, capacitors with capacitances adequate to stabilize the
power-supply voltage must be connected between the V
pin and GND. The ground-side a capacitor must be
CC
connected as close to the GND2 pin of power GND as possible. If it is impossible to connect a capacitor (electrolytic
capacitor) near the pin, the ceramic capacitor of about 0.1μF must be connected as close to the pin as possible.
If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power supply connection,
Since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors will be required.
12. VREG Stabilization
To stabilize the VREG voltage that is the power supply of the control circuit, connect a capacitor of 0.1μF or more.
GND of the capacitor must be attached as close to the control block GND (GND1 pin) of the IC as possible.
13. Error Amplifier
External components of the error amplifier block must be placed as close to the IC as possible to reduce influence of
noise.
Also, these components must be placed as separate from the motor as possible.
14. IC Reverse Metal
To improve heat radiation, the metal part on the reverse of IC is stuck fast to the substrate by using highly-conduction
solder.
15. SDCC (Speed Detection Current Control) function
The SDCC circuit controls the speed detection current. It limits the current to 87.5% of the specified current to reduce
acceleration of the motor when the rotation of the motor exceeds 95% of its target speed. This enables stabilized phase
lock pull-in and minimizes the variation in startup time.
The SDCC function is disabled by setting F/R low. It is enabled by setting F/R high or open.
Notes: If the selected state of SDCC does not match the rotational direction of the motor, it is necessary to solve the
problem by changing the HALL bias.
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This catalog provides informationasofMarch,2010.Specificationsandinformationhereinare subject
to change without notice.
PS No.A1645-13/13
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