BU9910KV [ROHM]
Status display LCD driver for PCs with I2C Bus interface; 个人电脑与I2C总线接口的状态显示LCD驱动器
| 型号： | BU9910KV |
| 厂家： | 
ROHM |
| 描述： | Status display LCD driver for PCs with I2C Bus interface |
| 文件： | 总15页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multimedia ICs
Status display LCD driver for PCs
with I2C Bus interface
BU9910KV
The BU9910KV is a status LCD driver with I2C Bus intetface. Various lighting mode can be controlled through I2C
Bus. In addition, 20 direct drive inputs allow the application to drive 20 elements directly without I2C Bus, so that the
system configuration can be kept simple.
Applications
•
PCs
Features
1) I2C Bus interface.
•
5) 20 direct drive inputs, which allow the application to
drive LCD directly without I2C control.
2) Drive up to 44 LCD cells.
4 common × 11 segment, 1 / 3 bias, 1 / 4 duty
3) Blink operation for eaeh cell.
6) Minimum LCD drive time is guaranteed for direct in.
7) LCD device test ferminals.(LCDT0, LCDT1)
8)Power aupply voltages: 3.3V to 5.0V
4) Support four frame frequencies
256Hz, 128Hz, 64Hz, 32Hz (at fOSC = 32.768kHz)
1
Multimedia ICs
BU9910KV
Block diagram
•
36
35
34
33
32
31
30
29
28
27
26
25
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
HT1
Date Latch Logic
Control Logic
I2CBus
Interface
Segment
Driver
Timing Generator
Common
Driver
HT0
LCDT1
LCDT0
1
2
3
4
5
6
7
8
9
10
11
12
2
Multimedia ICs
BU9910KV
Pin descriptions
•
Pin No.
1
Pin name
VL3
Function
Input for LCD driver
Input for LCD driver (2 / 3) VL3
Input for LCD driver (1 / 3) VL3
Ground
2
VL2
3
VL1
4
GND
5
COM3
COM2
COM1
COM0
CLK
LCD common driver output 3
LCD common driver output 2
LCD common driver output 1
LCD common driver output 0
Clock input (ex.32.768kHz)
Reset
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
#RES
SDA
I2CBus Serial Data Line
I2CBus Serial Clock Input
LCD Device test mode set 0
LCD Device test mode set 1
Direct IN Hold time set 0
Direct IN Hold time set 1
Direct IN 0
SCL
LCDT0
LCDT1
HT0
HT1
DIN0
DIN1
Direct IN 1
DIN2
Direct IN 2
DIN3
Direct IN 3
DIN4
Direct IN 4
DIN5
Direct IN 5
DIN6
Direct IN 6
DIN7
Direct IN 7
DIN8
Direct IN 8
DIN9
Direct IN 9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
DIN17
DIN18
DIN19
Direct IN 10
Direct IN 11
Direct IN 12
Direct IN 13
Direct IN 14
Direct IN 15
Direct IN 16
Direct IN 17
Direct IN 18
Direct IN 19
3
Multimedia ICs
BU9910KV
Pin No.
37
Pin name
Function
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
LCD segment driver output 10
LCD segment driver output 9
LCD segment driver output 8
LCD segment driver output 7
LCD segment driver output 6
LCD segment driver output 5
LCD segment driver output 4
LCD segment driver output 3
LCD segment driver output 2
LCD segment driver output 1
LCD segment driver output 0
Supply Voltage 3.0V to 5.5V
38
39
40
41
42
43
44
45
46
47
48
VDD
Absolute maximum ratings (Ta = 25°C)
•
Parameter
Symbol
Limits
7.0
Unit
Applied voltage
V
DD
V
mW
°C
°C
V
Power dissipation
Operating temperature
Storage temperature
Input voltage
Pd
400
Topr
Tstg
– 15 ~ + 75
– 55 ~ + 125
GND – 0.5 ~ VDD + 0.5
V
IN
Reduced by 4mW for each increase in Ta of 1°C over 25°C.
᭺ ROHM holds a license from Philips semicondoctors for the “I2C Bus.”
Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD = 5.0V)
•
Parameter
Circuit current
Symbol
Min.
20
Typ.
35
Max.
50
Unit
µA
V
Conditions
Bias 51kΩ × 3
I
DD
IH
IL
IH
IL
Input high level voltage
Input low level voltage
Input high level current
Input low level current
SDA pin
V
VDD 0.7
V
DD
V
DD + 0.5
—
—
—
—
V
–
–
0.5
—
0.0
0.0
0.0
V
DD 0.3
1.0
V
I
µA
µA
I
1.0
—
VOLsda
tfsda
0.0
—
0.2
—
0.6
V
Output low level voltage
I
OL = 6.0mA
CL = 400pF
I
ns
Output fall time
250
OL = 6.0mA
COM, SEG pins
V
V
V
OM3
OM2
OM1
Output intermediate level voltage VL3
Output intermediate level voltage VL2
Output intermediate level voltage VL1
Output low level voltage
VL3 – 0.1
VL2 – 0.1
VL1 – 0.1
0.0
V
V
V
V
IOM3 = 100µA
IOM2 = 100µA
IOM1 = 100µA
IOL = 100µA
VL3
VL2
VL1
0.2
VL3 + 0.1
VL2 + 0.1
VL1 + 0.1
0.6
V
OL
LCDT pin
Pull-up resistance
RPU
24k
30k
36k
Ω
—
᭺ Not designed for radiation resistance.
4
Multimedia ICs
BU9910KV
Input / output circuits
•
Pin No.
Pin name
Equivalent circuit
Pin description
I2C Bus serial data input / output.
11
SDA
I2C Bus serial clock Input.
12
SCL
Clock Input for LCD display.
Clock frequency is 32.768kHz.
9
CLK
Reset input.(Low Active)
Low: Reset all internal registers.
10
#RES
Note: Require external power on reset.
4
GND
Ground terminal.
Power supply.
3.0V to 5.5V supply voltage range.
48
VDD
5
Multimedia ICs
BU9910KV
Pin No.
Pin name
Equivalent circuit
Pin description
COM0 ~
COM3
5 ~ 8
LCD common drive output.
SEG0 ~
SEG10
LCD segment drive output.
37 ~ 47
Input of LCD drive voltage setting.
Supply the 1 / 3 VL3 voltage to VL1.
1
2
3
VL3
VL2
VL1
Supply the 2 / 3 VL3 voltage to VL2.
Supply the VDD or the zero to VDD
voltage to VL3 .
Direct drive Input.(High Active)
The drive time is set from the HT0
and HT1 terminals, and the drive
starts from a rising edge of the
direct drive Inputs.
DIN0 ~
DIN19
17 ~ 36
LCD cells will be driven while the
direct drive Input remains high.
6
Multimedia ICs
BU9910KV
Pin No.
15 ~ 16
Pin name
Equivalent circuit
Pin description
Hold time setting terminal of the direct
drive input.
There are four hold times to drive the cell.
HT0 ~
HT1
30kΩ: VDD = 5.0V
LCD device test terminal.
LCDT0 ~
LCDT1
13 ~ 14
7
Multimedia ICs
BU9910KV
Application example
•
VDD
COM0
COM1
COM2
COM3
VDD
VR
R
VL3
VL2
VL1
GND
SEG0
SEG1
R
44
Segment
LCD
C
C
C
R
#RES
CLK
Power on Reset
fosc = 32.768kHz
SEG9
SEG10
SCL
SDA
I2C Bus
Controller
DIN0
DIN1
Set direct in
hold time
HT0
HT1
Direct In
(HDD.FDD.etc)
LCD panel test
DIN18
DIN19
LCDT0
LCDT1
Note: Choose appropriate values of Road C and R for the LCD panel and application.
Fig.1
8
Multimedia ICs
BU9910KV
Circuit operation
(1) Description of the I2C Bus interface
•
1) Slave address
0
1
1
1
0
0
1
R / W
MSB
LSB
2) Conformance to I2C Bus standards
Parameter
Symbol
f SCL
Min.
0
Max.
400
–
Unit
kHz
µs
SCL clock frequency
Start condition hold time
t HD: STA
0.6
0.6
100
0
Start condition setup time t SU: STA
–
µs
Data setup time
Data hold time
t SU: DAT
t HD: DAT
–
ns
0.9
–
µs
Stop condition setup time t SU: STO
0.6
µs
(Start condition)
SCL
SDA
t SU: STA
t HD: STA
(Data condition)
SCL
SDA
t SU: DAT
t HD: DAT
(Stop condition)
SCL
SDA
t SU: STO
9
Multimedia ICs
BU9910KV
(2) Data structure
1) Wrote Mode
–
S
Address
A
A
Command Reg. Byte
Command Reg. Byte
A
Write Data Byte
Auto Increment
A
P
W
2) Read Mode
1. Command register set
–
S
Address
A
A
W
–
Sr
R
Address
R
Read Data Byte
Auto Increment
P
A
2. Preset command register
–
S
Address
A
Read Data Byte
Auto Increment
P
A
In multi-master application, the preset command register mode is prohibited.
S: Start condition
P: Stop condition
Sr: Restart condition
A: Acknowledge
A: Acknowledge bar
(3) Mode settings table
1) Command Register (commands and pointers)
D7
D6
D5
D4
D3
D2
D1
D0
Disp
Frame freq.
Blink freq.
Pointer register
The all bit may be "0"during the reset procedure.
D7: Display control
0: Light (depend on the LCD segment data memory status )
1: All off
D6, D5: Frame frequency select
D6
0
D5
0
f0
32Hz (default)
64Hz
0
1
1
0
128Hz
1
1
256Hz
At fosc = 32.768kHz
D4: Blink frequency select
0: Blink frequency = 0.5Hz (default)
1: Blink frequency = 1Hz
10
Multimedia ICs
BU9910KV
D3 to D0: Pointer register
The Pointer register appoints a base address, which acceses the LCD display memory in read or write mode.
In the write mode, a byte data that follows command byte is written to the LCD display memory which is
appointed by the pointer register.
Write address is incremented automatically and more than 2 bytes data are written to continuous place that
starts from the base address.
A master controller can continue to access the LCD display memory untill it generates the stop condition.
In the read mode, the master reads the LCD display memory data that is appointed by the pointer register.
Read adress is incremented automatically and the master read the LCD display memory data of continuous
address that starts from the base address.
The master can continue to access the LCD display memory data until it generates the NO ACK & Stop
Condition.
The pointer register value should be 0000b(0h) to 1011b(Bh) and becomes 0h after Bh.
Do not set Ch, Dh, Eh, Fh to the pointer register.
2) LCD display memory
LCD driving condition
Segment data memory Blink control memory
Driving condition
0
0
1
1
0
1
0
1
Off
Off
Light
Blink
Segment data memory: SEG vs. COM(COM No. / SEG No.)
Base address
0000b
bit7
3 / 1
3 / 3
3 / 5
3 / 7
3 / 9
0
bit6
2 / 1
2 / 3
2 / 5
2 / 7
2 / 9
0
bit5
1 / 1
1 / 3
1 / 5
1 / 7
1 / 9
0
bit4
0 / 1
0 / 3
0 / 5
0 / 7
0 / 9
0
bit3
3 / 0
3 / 2
3 / 4
3 / 6
3 / 8
3 / 10
bit2
2 / 0
2 / 2
2 / 4
2 / 6
2 / 8
2 / 10
bit1
1 / 0
1 / 2
1 / 4
1 / 6
1 / 8
1 / 10
bit0
0 / 0
0 / 2
0 / 4
0 / 6
0 / 8
0 / 10
0001b
0010b
0011b
0100b
0101b
11
Multimedia ICs
BU9910KV
Blink control memory: SEG vs. COM(COM No. / SEG No.)
Base Address
0110b
bit7
3 / 1
3 / 3
3 / 5
3 / 7
3 / 9
0
bit6
2 / 1
2 / 3
2 / 5
2 / 7
2 / 9
0
bit5
1 / 1
1 / 3
1 / 5
1 / 7
1 / 9
0
bit4
0 / 1
0 / 3
0 / 5
0 / 7
0 / 9
0
bit3
3 / 0
3 / 2
3 / 4
3 / 6
3 / 8
3 / 10
bit2
2 / 0
2 / 2
2 / 4
2 / 6
2 / 8
2 / 10
bit1
1 / 0
1 / 2
1 / 4
1 / 6
1 / 8
1 / 10
bit0
0 / 0
0 / 2
0 / 4
0 / 6
0 / 8
0 / 10
0111b
1000b
1001b
1010b
1011b
3) Direct drive input description
Direct input pin vs.SEG / COM
SEG6
DIN0
DIN1
DIN2
DIN3
SEG7
SEG8
DIN8
SEG9
DIN12
DIN13
DIN14
DIN15
SEG10
DIN16
DIN17
DIN18
DIN19
COM0
COM1
COM2
COM3
DIN4
DIN5
DIN6
DIN7
DIN9
DIN10
DIN11
In the test mode, the specified lighting is carried out regardless of the state of the segment data register. Setting pins
to the open state returns to the normal state without carrying out a reset.
Holding time setting(when activate the direct input pins)
HT1
L
HT0
L
Holding time
0.125s Ϲ HT < 0.156s
0.250s Ϲ HT < 0.313s
0.500s Ϲ HT < 0.625s
1.000s Ϲ HT < 1.250s
L
H
H
L
H
H
At fosc = 32.768kHz
4) LCD device test terminal description
LCD device test pins setting table
LCDT1 LCDT0
Lighting conditions
Test mode : All cells are turned on
L
L
L
H
L
Test mode : 10100101b (set all Segment Data Memory)
Test mode : 01011010b (set all Segment Data Memory)
Normal: Controlled by the LCD display memory
H
H
H
When these pins are low, the Segment data memory are ignored.
Each of LCDT1 and LCDT2 has a pull-up resister.
When these pins are open, return to nomal operation without reset.
12
Multimedia ICs
BU9910KV
(4) Output waveforms (1 / 2)
To = 1 / fo
VL3
VL2
VL1
VSS
• COM 0 Drive Output
• COM 1 Drive Output
• COM 2 Drive Output
• COM 3 Drive Output
VL3
VL2
VL1
VSS
VL3
VL2
VL1
VSS
VL3
VL2
VL1
VSS
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-off, COM 1-off, COM 2-off, COM 3-off
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-ON, COM 1-off, COM 2-off, COM 3-off
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-off, COM 1-ON, COM 2-off, COM 3-off
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-off, COM 1-off, COM 2-ON, COM 3-off
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-off, COM 1-off, COM 2-off, COM 3-ON
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-ON, COM 1-ON, COM 2-ON, COM 3-ON
1 / 3 bias, 1 / 4 duty waveforms
13
Multimedia ICs
BU9910KV
(5) Output waveforms (2 / 2)
To = 1 / fo
VL3
VL2
VL1
VSS
• COM 0 Drive Output
• COM 1 Drive Output
• COM 2 Drive Output
• COM 3 Drive Output
VL3
VL2
VL1
VSS
VL3
VL2
VL1
VSS
VL3
VL2
VL1
VSS
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-ON, COM 1-off, COM 2-ON, COM 3-off
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-ON, COM 1-off, COM 2-ON, COM 3-off
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-ON, COM 1-off, COM 2-off, COM 3-ON
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-off, COM 1-ON, COM 2-ON, COM 3-off
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-off, COM 1-ON, COM 2-off, COM 3-ON
VL3
VL2
VL1
VSS
• SEG Drive Output
COM 0-off, COM 1-off, COM 2-ON, COM 3-ON
1 / 3 bias, 1 / 4 duty waveforms
14
Multimedia ICs
BU9910KV
External dimensions (Units: mm)
•
9.0 ± 0.3
7.0
±
0.2
36
25
37
48
24
13
1
12
0.125 ± 0.1
0.5
0.2 ± 0.1
0.10
VQFP48
15
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