NTD60N02RT4 [ROCHESTER]
32A, 25V, 0.0105ohm, N-CHANNEL, Si, POWER, MOSFET, CASE 369AA-01, DPAK-3;
| 型号： | NTD60N02RT4 |
| 厂家： | 
Rochester Electronics |
| 描述： | 32A, 25V, 0.0105ohm, N-CHANNEL, Si, POWER, MOSFET, CASE 369AA-01, DPAK-3 开关 晶体管 |
| 文件： | 总9页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTD60N02R
Power MOSFET
62 A, 25 V, N−Channel, DPAK
Features
• Planar HD3e Process for Fast Switching Performance
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• Low R
to Minimize Conduction Loss
DS(on)
• Low C to Minimize Driver Loss
iss
V
R
DS(on)
TYP
I MAX
D
(BR)DSS
• Low Gate Charge
25 V
8.4 mW @ 10 V
62 A
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• Pb−Free Packages are Available
N−Channel
D
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Drain−to−Source Voltage
Symbol Value Unit
G
V
25
20
Vdc
Vdc
DSS
Gate−to−Source Voltage − Continuous
V
GS
S
4
Thermal Resistance
Junction−to−Case
Total Power Dissipation @ T = 25°C
Drain Current
R
P
2.6
58
°C/W
q
JC
4
W
C
D
4
Continuous @ T = 25°C, Chip
I
I
I
62
50
32
A
A
A
C
D
D
D
Continuous @ T = 25°C, Limited by Package
C
Continuous @ T = 25°C, Limited by Wires
A
2
3
1
1
1
2
3
Thermal Resistance
2
3
Junction−to−Ambient (Note 1)
Total Power Dissipation @ T = 25°C
Drain Current − Continuous @ T = 25°C
R
P
I
80
1.87
10.5
C/W
W
A
q
JA
A
D
D
CASE 369AA
DPAK
CASE 369AC
3 IPAK
CASE 369D
DPAK
A
(Surface Mount) (Straight Lead) (Straight Lead)
Thermal Resistance
Junction−to−Ambient (Note 2)
R
P
I
120
1.25
8.5
°C/W
W
A
STYLE 2
STYLE 2
q
JA
Total Power Dissipation @ T = 25°C
A
D
D
Drain Current − Continuous @ T = 25°C
A
MARKING DIAGRAM
& PIN ASSIGNMENTS
Operating and Storage Temperature
T , and −55 to
°C
J
T
175
stg
4
Single Pulse Drain−to−Source Avalanche Energy
E
60
mJ
AS
Drain
− Starting T = 25°C
J
4
(V = 50 Vdc, V = 10.0 Vdc,
DD
GS
Drain
I = 11 Apk, L = 1.0 mH, R = 25 W)
L
G
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
260
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 in sq drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
2
1
Gate
3
1
2
3
Drain
Source
Gate Drain Source
Y
WW
= Year
= Work Week
T60N02R = Device Code
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 12
NTD60N02R/D
NTD60N02R
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage (Note 3)
V
Vdc
mV/°C
mAdc
(BR)DSS
25
−
27.5
25.5
−
−
(V = 0 Vdc, I = 250 mAdc)
GS
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
I
DSS
GSS
−
−
−
−
1.5
10
(V = 20 Vdc, V = 0 Vdc)
DS
GS
(V = 20 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V
=
20 Vdc, V = 0 Vdc)
−
−
100
nAdc
GS
DS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
Vdc
mV/°C
mW
GS(th)
1.0
−
1.5
4.1
2.0
−
(V = V , I = 250 mAdc)
DS
GS
D
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
R
DS(on)
−
−
−
11.2
8.4
8.2
12.5
10.5
−
(V = 4.5 Vdc, I = 15 Adc)
GS
D
(V = 10 Vdc, I = 20 Adc)
GS
D
(V = 10 Vdc, I = 31 Adc)
GS
D
Forward Transconductance (V = 10 Vdc, I = 15 Adc) (Note 3)
g
FS
−
27
−
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
−
−
−
1000
480
1330
640
(V = 20 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
C
rss
180
225
t
−
−
−
−
−
−
−
7.0
33
−
−
ns
d(on)
t
r
(V = 10 Vdc, V = 10 Vdc,
GS
DD
I
= 31 Adc, R = 3.0 W)
D
G
Turn−Off Delay Time
Fall Time
t
19
−
d(off)
t
9.0
9.5
2.2
5.0
−
f
Gate Charge
Q
14
−
nC
T
(V = 4.5 Vdc, I = 31 Adc,
GS
D
Q
GS
GD
V
= 10 Vdc) (Note 3)
DS
Q
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
−
−
−
0.88
1.15
0.80
1.2
−
−
Vdc
ns
(I = 20 Adc, V = 0 Vdc) (Note 3)
SD
S
GS
(I = 31 Adc, V = 0 Vdc)
S
GS
(I = 15 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
29.1
13.6
15.5
0.02
−
−
−
−
rr
(I = 31 Adc, V = 0 Vdc,
S
GS
t
a
b
dI /dt = 100 A/ms) (Note 3)
S
t
Reverse Recovery Stored Charge
Q
mC
rr
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD60N02R
TYPICAL CHARACTERISTICS
140
120
V
= 10 V
T = 25°C
J
V
w 10 V
GS
DS
5.0 V
4.5 V
8.0 V
6.0 V
120
100
80
60
40
20
0
100
80
60
40
20
0
4.2 V
4.0 V
3.8 V
3.6 V
3.4 V
T = 175°C
J
3.2 V
3.0 V
2.8 V
T = 25°C
J
2.6 V
2.4 V
T = −55°C
J
0
2
4
6
8
10
0
2
4
6
8
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
V
, GATE−TO−SOURCE VOLTAGE (V)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.05
0.04
0.03
0.02
0.01
0
0.05
0.04
0.03
0.02
0.01
0
T = 25°C
I
= 62 A
J
D
T = 25°C
J
V
= 4.5 V
GS
V
= 10 V
120
GS
4
6
2
8
10
20
40
60
80
100
140
V
, GATE−TO−SOURCE VOLTAGE (V)
GS
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100000
10000
1000
100
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I
V
= 31 A
D
V
= 0 V
GS
= 10 V
GS
T = 175°C
J
T = 100°C
J
10
0
−50 −25
0
25
50
75
100 125 150 175
6
12
18
24
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTD60N02R
5
20
16
12
8
2000
1500
1000
500
0
T = 25°C
J
Q
T
C
iss
4
3
2
1
0
V
GS
V
= 0 V
Q
Q
DS
GS
GS
V
= 0 V
DS
C
iss
V
DS
C
rss
C
oss
4
C
rss
I
= 31 A
D
T = 25°C
J
0
10
10
5
0
5
10
15
20
0
2
4
6
8
V
V
DS
GS
Q , TOTAL GATE CHARGE (nC)
g
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
1000
100
10
80
V
I
V
= 10 V
= 31 A
= 10 V
DD
GS
V
= 0 V
GS
70
60
50
40
30
20
10
0
D
T = 25°C
J
t
r
t
f
t
d(off)
t
d(on)
1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1
10
100
R , GATE RESISTANCE (W)
G
V , SOURCE−TO−DRAIN VOLTAGE (V)
SD
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
100
10 ms
V
= 20 V
GS
SINGLE PULSE
T
= 25°C
C
100 ms
10
1 ms
10 ms
dc
R
LIMIT
DS(ON)
THERMAL LIMIT
PACKAGE LIMIT
1
0.1
1
10
100
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 11. Maximum Rated Forward Biased Safe Operating Area
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4
NTD60N02R
1.0
D = 0.5
0.2
0.1
0.05
0.02
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
SINGLE PULSE
t
1
1
t
2
T
− T = P
R (t)
q
JC
J(pk)
C
(pk)
DUTY CYCLE, D = t /t
1
2
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t, TIME (s)
Figure 12. Thermal Response
ORDERING INFORMATION
Order Number
†
Package
Shipping
NTD60N02R
DPAK−3
75 Units / Rail
75 Units / Rail
NTD60N02RG
DPAK−3
(Pb−Free)
NTD60N02RT4
DPAK−3
2500 / Tape & Reel
2500 / Tape & Reel
NTD60N02RT4G
DPAK−3
(Pb−Free)
NTD60N02R−1
DPAK−3 Straight Lead
75 Units / Rail
75 Units / Rail
NTD60N02R−1G
DPAK−3 Straight Lead
(Pb−Free)
NTD60N02R−35
DPAK−3 Straight Lead
(3.5 0.15 mm)
75 Units / Rail
75 Units / Rail
NTD60N02R−35G
DPAK−3 Straight Lead
(3.5 0.15 mm)
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTD60N02R
PACKAGE DIMENSIONS
DPAK
CASE 369AA−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.63
0.46
0.77
MAX
6.22
6.73
2.38
0.89
0.61
1.14
A
B
C
D
E
F
0.235 0.245
0.250 0.265
0.086 0.094
0.025 0.035
0.018 0.024
0.030 0.045
0.386 0.410
0.018 0.023
0.090 BSC
4
2
Z
A
H
S
1
3
H
J
9.80 10.40
U
0.46
0.58
L
2.29 BSC
R
S
U
V
Z
0.180 0.215
0.024 0.040
4.57
0.60
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
F
J
0.020
0.035 0.050
0.155 −−−
−−−
L
STYLE 2:
PIN 1. GATE
2. DRAIN
D 2 PL
M
0.13 (0.005)
T
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
1.6
0.063
6.172
0.243
0.228
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
NTD60N02R
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
B
R
C
V
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.09
A
B
C
D
E
F
G
H
J
K
R
V
W
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
A
K
SEATING PLANE
W
2.29 BSC
F
0.87
0.46
3.40
4.57
0.89
1.01
0.58
3.60
5.46
1.27
0.25
J
G
H
D 3 PL
0.000 0.010 0.000
0.13 (0.005) W
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7
NTD60N02R
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE B
C
B
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
4
2
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
PIN 1. GATE
G
M
T
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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NTD60N02R/D
相关型号：
NTD60N02RT4G
32A, 25V, 0.0105ohm, N-CHANNEL, Si, POWER, MOSFET, LEAD FREE, CASE 369AA-01, DPAK-3
ROCHESTER
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