NTD60N03-1 [ONSEMI]

Power MOSFET 60 Amps, 28 Volts; 功率MOSFET 60安培, 28伏
NTD60N03-1
型号: NTD60N03-1
厂家: ONSEMI    ONSEMI
描述:

Power MOSFET 60 Amps, 28 Volts
功率MOSFET 60安培, 28伏

晶体 晶体管 功率场效应晶体管 开关 脉冲
文件: 总10页 (文件大小:90K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
NTD60N03  
Power MOSFET  
60 Amps, 28 Volts  
N-Channel DPAK  
Designed for low voltage, high speed switching applications in  
power supplies, converters and power motor controls and bridge  
circuits.  
http://onsemi.com  
60 AMPERES  
28 VOLTS  
RDS(on) = 6.1 mW (Typ.)  
Typical Applications  
Power Supplies  
Converters  
Power Motor Controls  
Bridge Circuits  
N-Channel  
D
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
Unit  
G
Drain-to-Source Voltage  
V
28  
Vdc  
Vdc  
Adc  
DSS  
Gate-to-Source Voltage - Continuous  
V
±20  
GS  
4
Drain Current - Continuous @ T = 25°C  
I
D
60*  
A
S
4
Drain Current - Single Pulse (t = 10 ms)  
I
120  
p
DM  
Total Power Dissipation @ T = 25°C  
P
75  
Watts  
A
D
2
1
Operating and Storage  
Temperature Range  
T , T  
J
- 55 to  
150  
°C  
stg  
3
1
2
3
CASE 369A  
DPAK  
(Bend Lead)  
STYLE 2  
Single Pulse Drain-to-Source Avalanche  
E
AS  
733  
mJ  
CASE 369  
DPAK  
Energy - Starting T = 25°C  
J
(V = 28 Vdc, V = 10 Vdc,  
DD  
GS  
(Straight Lead)  
STYLE 2  
I = 17 Apk, L = 5.0 mH, R = 25 W)  
L
G
Thermal Resistance  
°C/W  
-
Junction-to-Case  
R
R
R
1.65  
67  
120  
MARKING DIAGRAMS  
& PIN ASSIGNMENTS  
q
JC  
JA  
JA  
- Junction-to-Ambient (Note 1)  
- Junction-to-Ambient (Note 2)  
q
q
4
Maximum Lead Temperature for Soldering  
Purposes, 1/8from case for 10 seconds  
T
260  
°C  
Drain  
L
4
Drain  
YWW  
T
4228  
1. When surface mounted to an FR4 board using 1pad size,  
2
(Cu Area 1.127 in ).  
YWW  
T
4228  
2. When surface mounted to an FR4 board using the minimum recommended  
2
pad size, (Cu Area 0.412 in ).  
*Chip current capability limited by package.  
1
Gate  
3
2
1
Gate  
3
Source  
Drain  
Source  
2
Drain  
Y
= Year  
WW  
T
= Work Week  
= MOSFET  
4228  
= Device Code  
ORDERING INFORMATION  
Device  
Package  
Shipping  
75 Units/Rail  
NTD60N03  
DPAK  
DPAK  
NTD60N03T4  
NTD60N03-1  
2500 Tape & Reel  
75 Units/Rail  
DPAK  
Straight Lead  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
March, 2003 - Rev. 5  
NTD60N03/D  
NTD60N03  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
J
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain-to-Source Breakdown Voltage (Note 3)  
V
Vdc  
(BR)DSS  
(V = 0 Vdc, I = 250 mAdc)  
Temperature Coefficient (Positive)  
28  
-
30.6  
25  
-
-
GS  
D
mV/°C  
mAdc  
Zero Gate Voltage Drain Current  
I
DSS  
(V = 0 Vdc, V = 28 Vdc)  
-
-
-
-
1.0  
10  
GS  
DS  
(V = 0 Vdc, V = 28 Vdc, T = 150°C)  
GS  
DS  
J
Gate-Body Leakage Current (V = ±20 Vdc, V = 0 Vdc)  
I
-
-
±100  
nAdc  
Vdc  
GS  
DS  
GSS  
ON CHARACTERISTICS (Note 3)  
Gate Threshold Voltage (Note 3)  
(V = V , I = 250 mAdc)  
V
GS(th)  
1.0  
-
1.9  
-3.8  
3.0  
-
DS  
GS  
D
Threshold Temperature Coefficient (Negative)  
Static Drain-to-Source On-Resistance (Note 3)  
(V = 10 Vdc, I = 30 Adc)  
mV/°C  
mW  
R
DS(on)  
-
-
-
6.1  
9.2  
6.4  
7.5  
-
-
GS  
D
(V = 4.5 Vdc, I = 30 Adc)  
GS  
D
(V = 10 Vdc, I = 10 Adc)  
GS  
D
Forward Transconductance (V = 15 Vdc, I = 10 Adc) (Note 3)  
g
FS  
-
20  
-
Mhos  
pF  
DS  
D
DYNAMIC CHARACTERISTICS  
Input Capacitance  
Output Capacitance  
Transfer Capacitance  
C
-
-
-
2150  
680  
-
-
-
iss  
(V = 24 Vdc, V = 0 Vdc,  
DS  
GS  
C
oss  
f = 1.0 MHz)  
C
260  
rss  
SWITCHING CHARACTERISTICS (Note 4)  
Turn-On Delay Time  
Rise Time  
t
-
-
-
-
-
-
-
10  
18  
-
-
-
-
-
-
-
ns  
nC  
d(on)  
(V = 15 Vdc, I = 15 Adc,  
DD  
D
t
r
V
GS  
= 10 Vdc,  
Turn-Of f Delay Time  
Fall Time  
t
32  
d(off)  
R
= 3.3 W)  
G
t
f
15  
Gate Charge  
Q
30  
T
(V = 24 Vdc, I = 15 Adc,  
DS  
D
Q1  
Q2  
6.5  
18.4  
V
GS  
= 4.5 Vdc) (Note 3)  
SOURCE-DRAIN DIODE CHARACTERISTICS  
Forward On-Voltage  
V
SD  
Vdc  
(I = 2.3 Adc, V = 0 Vdc) (Note 3)  
-
-
-
0.75  
1.2  
0.65  
1.0  
-
-
S
GS  
(I = 30 Adc, V = 0 Vdc)  
S
GS  
(I = 2.3 Adc, V = 0 Vdc, T = 150°C)  
S
GS  
J
Reverse Recovery Time  
t
-
-
-
-
39  
21  
-
-
-
-
ns  
rr  
(I = 2.3 Adc, V = 0 Vdc,  
dI /dt = 100 A/ms) (Note 3)  
S
S
GS  
t
a
b
t
18  
Reverse Recovery Stored Charge  
Q
0.043  
mC  
rr  
3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.  
4. Switching characteristics are independent of operating junction temperatures.  
http://onsemi.com  
2
NTD60N03  
50  
40  
30  
60  
50  
3.8 V  
T = 25°C  
J
V
10 V  
DS  
10 V  
8 V  
6 V  
3.6 V  
40  
30  
20  
5 V  
4.5 V  
4 V  
3.4 V  
3.2 V  
T = 25°C  
J
20  
10  
0
T = 125°C  
J
3 V  
10  
0
V
GS  
= 2.8 V  
T
J
= -55°C  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
2
5
4
3
4
5
6
V
, DRAIN-TO-SOURCE VOLTAGE (V)  
V
, GATE-T O-SOURCE VOLTAGE (V)  
DS  
GS  
Figure 1. On-Region Characteristics  
Figure 2. Transfer Characteristics  
0.07  
0.06  
0.05  
0.04  
0.03  
0.02  
0.015  
0.01  
I
D
= 10 A  
T = 25°C  
J
T = 25°C  
J
V
= 4.5 V  
= 10 V  
GS  
V
GS  
0.005  
0
0.01  
0
0
2
4
6
8
10  
10  
15  
20  
25  
30  
V
, GATE-T O-SOURCE VOLTAGE (V)  
I , DRAIN CURRENT (A)  
D
GS  
Figure 3. On-Resistance versus  
Gate-To-Source Voltage  
Figure 4. On-Resistance versus Drain Current  
and Gate Voltage  
1.8  
1000  
100  
V
= 0 V  
GS  
I
V
= 30 A  
D
= 10 V  
1.6  
1.4  
1.2  
DS  
T = 125°C  
J
T = 100°C  
J
10  
1
1.0  
0.8  
0.6  
-50 -25  
0
25  
50  
75  
100  
125 150  
8
12  
16  
20  
T , JUNCTION TEMPERATURE (°C)  
J
V
DS  
, DRAIN-TO-SOURCE VOLTAGE (V)  
Figure 5. On-Resistance Variation with  
Temperature  
Figure 6. Drain-To-Source Leakage  
Current versus Voltage  
http://onsemi.com  
3
NTD60N03  
5000  
4500  
4000  
3500  
3000  
2500  
2000  
1500  
1000  
8
C
iss  
T = 25°C  
J
6
4
2
0
Q
T
C
rss  
Q
Q
2
1
V
C
GS  
iss  
C
oss  
I
D
= 15 A  
T = 25°C  
J
500  
0
C
rss  
V
= 0 V V = 0 V  
GS  
DS  
15  
10  
5
0
5
10  
15  
20  
25  
0
8
16  
24  
32  
V
GS  
V
DS  
Q , TOTAL GATE CHARGE (nC)  
g
GATE-T O-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)  
Figure 7. Capacitance Variation  
Figure 8. Gate-to-Source and  
Drain-to-Source Voltage versus Total Charge  
1000  
100  
10  
5
V
I
= 24 V  
= 20 A  
= 10 V  
DD  
V
= 0 V  
D
GS  
4
3
2
V
GS  
T = 25°C  
J
t
f
t
d(off)  
t
r
t
d(on)  
1
0
1
1
10  
R , GATE RESISTANCE (W)  
100  
0.1  
0.3  
0.5  
0.7  
0.9  
V
SD  
, SOURCE-TO-DRAIN VOLTAGE (V)  
G
Figure 9. Resistive Switching Time Variation  
versus Gate Resistance  
Figure 10. Diode Forward Voltage versus  
Current  
http://onsemi.com  
4
NTD60N03  
100  
100 ms  
di/dt  
I
S
1 ms  
V
= 10 V  
SINGLE PULSE  
GS  
t
rr  
10  
t
a
t
b
T
= 25°C  
C
10 ms  
dc  
TIME  
0.25 I  
t
p
S
R
DS(on)  
LIMIT  
THERMAL LIMIT  
PACKAGE LIMIT  
I
S
1
0.1  
1
10  
100  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)  
Figure 12. Diode Reverse Recovery Waveform  
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
1000  
100  
10  
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT  
DUTY CYCLE  
D = 0.5  
0.2  
0.1  
0.05  
0.02  
0.01  
1
R
q
(t) = r(t) R  
q
JA  
JA  
P
(pk)  
D CURVES APPLY FOR POWER  
PULSE TRAIN SHOWN  
READ TIME AT t  
t
1
0.1  
t
2
1
T
− T = P  
A
R (t)  
q
JA  
J(pk)  
(pk)  
SINGLE PULSE  
DUTY CYCLE, D = t /t  
1 2  
0.01  
1E−05  
1E−04  
1E−03  
1E−02  
1E−01  
1E+00  
1E+01  
1E+02  
1E+03  
t, TIME (seconds)  
Figure 13. Thermal Response - Various Duty Cycles  
http://onsemi.com  
5
NTD60N03  
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE  
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS  
Surface mount board layout is a critical portion of the  
total design. The footprint for the semiconductor packages  
must be the correct size to ensure proper solder connection  
interface between the board and the package. With the  
correct pad geometry, the packages will self align when  
subjected to a solder reflow process.  
0.165  
4.191  
0.118  
3.0  
0.100  
2.54  
0.063  
1.6  
0.190  
4.826  
0.243  
6.172  
inches  
mm  
SOLDER STENCIL GUIDELINES  
Prior to placing surface mount components onto a printed  
circuit board, solder paste must be applied to the pads.  
Solder stencils are used to screen the optimum amount.  
These stencils are typically 0.008 inches thick and may be  
made of brass or stainless steel. For packages such as the  
SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143,  
SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode  
packages, the stencil opening should be the same as the pad  
size or a 1:1 registration. This is not the case with the DPAK  
pattern of the opening in the stencil for the drain pad is not  
critical as long as it allows approximately 50% of the pad to  
be covered with paste.  
SOLDER PASTE  
OPENINGS  
2
and D PAK packages. If one uses a 1:1 opening to screen  
STENCIL  
solder onto the drain pad, misalignment and/or  
“tombstoning” may occur due to an excess of solder. For  
these two packages, the opening in the stencil for the paste  
should be approximately 50% of the tab area. The opening  
for the leads is still a 1:1 registration. Figure 14 shows a  
Figure 14. Typical Stencil for DPAK and  
D2PAK Packages  
2
typical stencil for the DPAK and D PAK packages. The  
SOLDERING PRECAUTIONS  
The melting temperature of solder is higher than the rated  
temperature of the device. When the entire device is heated  
to a high temperature, failure to complete soldering within  
a short time could result in device failure. Therefore, the  
following items should always be observed in order to  
minimize the thermal stress to which the devices are  
subjected.  
Always preheat the device.  
The delta temperature between the preheat and  
soldering should be 100°C or less.*  
When shifting from preheating to soldering, the  
maximum temperature gradient shall be 5°C or less.  
After soldering has been completed, the device should  
be allowed to cool naturally for at least three minutes.  
Gradual cooling should be used as the use of forced  
cooling will increase the temperature gradient and  
result in latent failure due to mechanical stress.  
Mechanical stress or shock should not be applied  
during cooling.  
When preheating and soldering, the temperature of the  
leads and the case must not exceed the maximum  
temperature ratings as shown on the data sheet. When  
using infrared heating with the reflow soldering  
method, the difference shall be a maximum of 10°C.  
The soldering temperature and time shall not exceed  
260°C for more than 10 seconds.  
* Soldering a device without preheating can cause excessive  
thermal shock and stress which can result in damage to the  
device.  
* Due to shadowing and the inability to set the wave height  
2
to incorporate other surface mount components, the D PAK  
is not recommended for wave soldering.  
http://onsemi.com  
6
NTD60N03  
TYPICAL SOLDER HEATING PROFILE  
For any given circuit board, there will be a group of  
temperature versus time. The line on the graph shows the  
actual temperature that might be experienced on the surface  
of a test board at or near a central solder joint. The two  
profiles are based on a high density and a low density  
board. The Vitronics SMD310 convection/infrared reflow  
soldering system was used to generate this profile. The type  
of solder used was 62/36/2 Tin Lead Silver with a melting  
point between 177-189 °C. When this type of furnace is  
used for solder reflow work, the circuit boards and solder  
joints tend to heat first. The components on the board are  
then heated by conduction. The circuit board, because it has  
a large surface area, absorbs the thermal energy more  
efficiently, then distributes this energy to the components.  
Because of this effect, the main body of a component may  
be up to 30 degrees cooler than the adjacent solder joints.  
control settings that will give the desired heat pattern. The  
operator must set temperatures for several heating zones  
and a figure for belt speed. Taken together, these control  
settings make up a heating “profile” for that particular  
circuit board. On machines controlled by a computer, the  
computer remembers these profiles from one operating  
session to the next. Figure 15 shows a typical heating  
profile for use when soldering a surface mount device to a  
printed circuit board. This profile will vary among  
soldering systems, but it is a good starting point. Factors  
that can affect the profile include the type of soldering  
system in use, density and types of components on the  
board, type of solder used, and the type of board or  
substrate material being used. This profile shows  
STEP 1  
PREHEAT  
ZONE 1  
“RAMP”  
STEP 2  
VENT  
“SOAK” ZONES 2 & 5  
“RAMP”  
STEP 3  
HEATING  
STEP 4  
HEATING  
ZONES 3 & 6  
“SOAK”  
STEP 5  
HEATING  
ZONES 4 & 7  
“SPIKE”  
STEP 6  
VENT  
STEP 7  
COOLING  
205° TO 219°C  
PEAK AT  
SOLDER  
JOINT  
170°C  
DESIRED CURVE FOR HIGH  
MASS ASSEMBLIES  
200°C  
150°C  
100°C  
5°C  
160°C  
150°C  
SOLDER IS LIQUID FOR  
40 TO 80 SECONDS  
(DEPENDING ON  
100°C  
140°C  
MASS OF ASSEMBLY)  
DESIRED CURVE FOR LOW  
MASS ASSEMBLIES  
TIME (3 TO 7 MINUTES TOTAL)  
T
MAX  
Figure 15. Typical Solder Heating Profile  
http://onsemi.com  
7
NTD60N03  
PACKAGE DIMENSIONS  
DPAK, STRAIGHT LEAD  
CASE 369-07  
ISSUE M  
C
B
R
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
V
E
INCHES  
DIM MIN MAX  
MILLIMETERS  
4
2
MIN  
5.97  
6.35  
2.19  
0.69  
0.84  
0.94  
MAX  
6.35  
6.73  
2.38  
0.88  
1.01  
1.19  
A
B
C
D
E
F
0.235  
0.250  
0.086  
0.027  
0.033  
0.037  
0.250  
0.265  
0.094  
0.035  
0.040  
0.047  
A
K
1
3
S
-T-  
SEATING  
PLANE  
0.090 BSC  
2.29 BSC  
G
H
J
0.034  
0.018  
0.350  
0.175  
0.050  
0.030  
0.040  
0.023  
0.380  
0.215  
0.090  
0.050  
0.87  
0.46  
8.89  
4.45  
1.27  
0.77  
1.01  
0.58  
9.65  
5.46  
2.28  
1.27  
K
R
S
V
J
F
H
D 3 PL  
STYLE 2:  
PIN 1. GATE  
G
M
T
0.13 (0.005)  
2. DRAIN  
3. SOURCE  
4. DRAIN  
http://onsemi.com  
8
NTD60N03  
PACKAGE DIMENSIONS  
DPAK  
CASE 369A-13  
ISSUE AB  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
SEATING  
-T-  
PLANE  
2. CONTROLLING DIMENSION: INCH.  
C
B
R
INCHES  
DIM MIN MAX  
MILLIMETERS  
E
V
MIN  
5.97  
6.35  
2.19  
0.69  
0.84  
0.94  
MAX  
6.35  
6.73  
2.38  
0.88  
1.01  
1.19  
A
B
C
D
E
F
0.235  
0.250  
0.086  
0.027  
0.033  
0.037  
0.250  
0.265  
0.094  
0.035  
0.040  
0.047  
4
2
Z
A
K
S
1
3
G
H
J
0.180 BSC  
4.58 BSC  
U
0.034  
0.018  
0.102  
0.040  
0.023  
0.114  
0.87  
0.46  
2.60  
1.01  
0.58  
2.89  
K
L
0.090 BSC  
2.29 BSC  
F
J
R
S
U
V
Z
0.175  
0.020  
0.020  
0.030  
0.138  
0.215  
0.050  
−−−  
0.050  
−−−  
4.45  
0.51  
0.51  
0.77  
3.51  
5.46  
1.27  
−−−  
1.27  
−−−  
L
H
D 2 PL  
M
G
0.13 (0.005)  
T
STYLE 2:  
PIN 1. GATE  
2. DRAIN  
3. SOURCE  
4. DRAIN  
http://onsemi.com  
9
NTD60N03  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make  
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any  
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all  
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be  
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may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC  
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  
PUBLICATION ORDERING INFORMATION  
Literature Fulfillment:  
JAPAN: ON Semiconductor, Japan Customer Focus Center  
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051  
Phone: 81-3-5773-3850  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada  
Email: ONlit@hibbertco.com  
ON Semiconductor Website: http://onsemi.com  
For additional information, please contact your local  
Sales Representative.  
N. American Technical Support: 800-282-9855 Toll Free USA/Canada  
NTD60N03/D  

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