ADV7800BSTZ-80 [ROCHESTER]
SPECIALTY CONSUMER CIRCUIT, PQFP176, 26 X 26 MM, ROHS COMPLIANT, MS-026BGA, LQFP-176;
| 型号： | ADV7800BSTZ-80 |
| 厂家： | 
Rochester Electronics |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PQFP176, 26 X 26 MM, ROHS COMPLIANT, MS-026BGA, LQFP-176 |
| 文件： | 总29页 (文件大小：1776K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, SDTV/HDTV 3D Comb Filter,
Video Decoder, and Graphics Digitizer
ADV7800
Data Sheet
DDR/SDR SDRAM
INTERFACE
FEATURES
ADDRESS (14)
CONTROL (9)
Four 10-bit ADCs
DATA (16)
CLK
ADV7800
10-bit high dynamic range processing
12-channel analog input mux
10-bit deep color processing
Analog monitor output
NTSC/PAL/SECAM color standards support
NTSC/PAL 3D comb filter
3D digital noise reduction (DNR)
Advanced time base correction (TBC) with frame
synchronization
Interlaced-to-progressive conversion for 525i and 625i
Advanced VBI data slicer, including Teletext, CC, and V-chip
IF compensation filter
SCART fast blank support including slow switch detect
Programmable internal antialias filters
Weak, poor time base, and nonstandard signal support
Vertical peaking, horizontal peaking, CTI, LTI
Simultaneous interlaced and progressive parallel output for
525i/525p and 625i/625p
ANALOG INPUT INTERFACE
10
10
10
DDR/SDR
SDRAM
Y
GR RGB
YPrPb
CLAMP
CLAMP
CLAMP
ADC
ADC
ADC
ADC
INTERFACE
Cb
Cr
STANDARD
DEFINITION
PROCESSOR
(SDP)
SCART
CVBS
S-VIDEO
CLAMP
DAC
ADC_CLK
CORE_CLK
DIGITAL INPUT
INTERFACE
HS_IN1
VS_IN1
SOG
SYNC CP
SDP
PLL
ANA
DIG
HS
XTAL
VS
ADC, CORE, MEMORY
CLK GENERATION
FLD
DE
CORE_CLK
DDS FOR SDP LINE-LOCKED
CLK GENERATION
COMPONENT
PROCESSOR
(CP)
CP
DAC
SDP
LLC
2
I C CONFIGURATION
ANALOG
DIGITAL
Figure 1. Simplified Functional Block Diagram
GENERAL DESCRIPTION
The ADV78001 is a high quality, single-chip, multiformat 3D
comb filter, video decoder, and graphics digitizer. This multi-
format 3D comb filter decoder supports the conversion of PAL,
NTSC, and SECAM standards in the form of a composite or an
S-Video into a digital ITU-R BT.656 format. The ADV7800 also
supports the decoding of a component RGB/YPrPb video signal
into a digital YCrCb or RGB pixel output stream.
525p/625p component progressive scan support
720p/1080i/1080p component HDTV support
Digitizes RGB graphics with maximum pixel clock rate
of 150 MHz (150 MHz speed grade only)
24-bit digital input port supports data from DVI/HDMI Rx IC
Any-to-any, advanced 3 × 3 color space conversion matrix
Flexible output pixel interface supporting 8-/10-/16-/
20-/24-/30-bit SDR/DDR 4:2:2/4:4:4 data formats
Programmable interrupt request output pin
The support for component video includes standards such as
525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HD
and SMPTE standards. Graphics digitization is supported by
the ADV7800; it is capable of digitizing RGB graphics signals
from VGA to SXGA rates and converting them into a digital
RGB or YCrCb pixel output stream. SCART and overlay
functionality are enabled by the ability of the ADV7800 to
simultaneously process CVBS and standard definition RGB
signals.
APPLICATIONS
AV receivers
LCD HDTVs
PDP HDTVs
CRT HDTVs
HDTV STBs with PVR
DVD recorders with progressive scan input support
Projectors
The ADV7800 contains two main processing sections. The first
section is the standard definition processor (SDP), which processes
all PAL, NTSC, SECAM, and component (up to 525p/625p)
signal types. The second section is the component processor
(CP), which processes YPrPb and RGB component formats,
including RGB graphics.
1 Protected by U.S. Patent Number 4,907,093 and other intellectual
property rights.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADV7800
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Key Features................................................................................ 13
Analog Front End....................................................................... 13
Standard Definition Processor ................................................. 13
VBI Data Processor.................................................................... 14
Component Processor ............................................................... 14
Additional Features.................................................................... 15
External Memory Requirements.................................................. 16
Single Data Rate (SDR).............................................................. 16
Double Data Rate (DDR) .......................................................... 16
Recommended External Loop Filter Components.................... 17
Typical Connection Diagrams...................................................... 18
Pixel Input/Output Formatting .................................................... 20
Pixel Data Output Modes Highlights ...................................... 20
Digital Video Input Port Highlights ........................................ 20
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Electrical Characteristics............................................................. 4
Video Specifications..................................................................... 5
Timing Characteristics ................................................................ 6
Timing Diagrams.......................................................................... 7
Analog Specifications................................................................... 8
Absolute Maximum Ratings............................................................ 9
Package Thermal Performance................................................... 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Theory of Operation ...................................................................... 13
REVISION HISTORY
8/11—Revision C: Initial Version
Rev. C | Page 2 of 28
Data Sheet
ADV7800
FUNCTIONAL BLOCK DIAGRAM
2
0 - 0 7 6 0 6
R E T A T R M O
D F A O N F I F T U P U T O
X
M U
X U M T U P I N
Figure 2.
Rev. C | Page 3 of 28
ADV7800
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR),
DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. TA = 0°C to 85°C, unless otherwise noted.
Table 1.
Parameter1
Symbol
Test Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE2, 3
Resolution (Each ADC)
Integral Nonlinearity4
N
10
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
INL
BSL at 27 MHz (at a 10-bit level)
BSL at 54 MHz (at a 10-bit level)
BSL at 74 MHz (at a 10-bit level)
BSL at 110 MHz (at a 10-bit level)
BSL at 150 MHz (at an 8-bit level)
At 27 MHz (at a 10-bit level)
At 54 MHz (at a 10-bit level)
At 74 MHz (at a 10-bit level)
At 110 MHz (at a 10-bit level)
At 150 MHz (at an 8-bit level)
−0.3/+0.4
−0.4/+0.5
−0.3/+0.2
−0.3/+0.6
−0.6/+0.6
−0.2/+0.3
−0.2/+0.3
−0.5/+0.4
−0.2/+0.3
−0.2/+0.4
Differential Nonlinearity4
DNL
POWER REQUIREMENTS5
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
DVDD
1.75
3.0
1.8
3.3
1.8
3.3
2.5
3.3
236
103
236
319
6
1.85
3.6
V
DVDDIO
PVDD
V
1.71
3.15
2.35
3.2
1.89
3.45
2.65
3.4
V
Analog Power Supply
AVDD
V
Memory Interface Power Supply
DVDDIO_SDRAM
DDR
V
SDR
V
Digital Core Supply Current
IDVDD
CVBS input sampling at 54 MHz
Graphics RGB sampling at 78 MHz
SCART RGB FB sampling at 54 MHz
525p input sampling at 54 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 78 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 78 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 78 MHz
SCART RGB FB sampling at 54 MHz
CVBS input sampling at 54 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
Digital I/O Supply Current
PLL Supply Current
IDVDDIO
IPVDD
15
13
10
Analog Supply Current
IAVDD
99
263
269
17
Memory Interface Supply Current
Power-Down Current
Power-Up Time
IVDDRAM
IPWRDN
TPWRUP
8
20
DIGITAL INPUTS
Input High Voltage
VIH
VIL
IIN
2
V
Input Low Voltage
0.8
10
15
V
Input Current
µA
pF
Input Capacitance
CIN
DIGITAL OUTPUTS
Output High Voltage6
Output Low Voltage6
High Impedance Leakage Current
Output Capacitance
VOH
VOL
ISOURCE = 0.4 mA
ISINK = 3.2 mA
2.4
0.4
10
V
V
ILEAK
COUT
μA
pF
20
1 Temperature range TMIN to TMAX
.
2 All ADC linearity tests performed with part configured for component video input.
3 All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%.
4 Maximum INL and DNL specifications obtained with part configured for component video input.
5 Guaranteed by characterization.
6 VOH and VOL levels obtained using default drive strength.
Rev. C | Page 4 of 28
Data Sheet
ADV7800
VIDEO SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR),
DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V. TA = 0°C to 85°C, unless otherwise noted.
Table 2.
Parameter1
Symbol
Test Conditions
Min
Typ
Max
Unit
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
DP
DG
LNL
CVBS input (modulated 5-step)
CVBS input (modulated 5-step)
CVBS input (modulated 5-step)
0.47
0.47
0.8
Degrees
%
%
Luma ramp
Luma flat field
61
62
60
dB
dB
dB
Analog Front-End Crosstalk
LOCK TIME SPECIFICATIONS (SDP)
Horizontal Lock Range
Vertical Lock Range
5
%
Hz
40
70
Subcarrier Lock Range, fSC
Color Lock-In Time
0.8
60
kHz
Lines
%
Sync Depth Range2
20
1
200
200
Color Burst Range
%
Vertical Lock Time
Horizontal Lock Time
300
100
ms
Lines
CHROMA SPECIFICATIONS (SDP)
Chroma Amplitude Error
Chroma Phase Error
0.4
0.3
0.2
%
Degrees
%
Chroma Luma Intermodulation
1 Guaranteed by characterization.
2 Nominal sync depth is 300 mV at 100% sync depth range.
Rev. C | Page 5 of 28
ADV7800
Data Sheet
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR),
DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V. TA = 0°C to 85°C, unless otherwise noted.
Table 3.
Parameter1
Symbol
Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
28.63636
MHz
ppm
kHz
50
90
150
14.8
12.825
MHz
I2C PORT
SCLK Frequency
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time (Stop Condition)
FAST I2C PORT2
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
SCLK Frequency
3.4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time (Stop Condition)
RESET FEATURE
t1
t2
t3
t4
t5
t6
t7
t8
60
160
160
160
10
10
10
80
80
160
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS3
Data Output Transition Time, SDR (SD Core)
t9, t10
t11
45:55
55:45
% duty cycle
Negative clock edge to start of
valid data
End of valid data to negative
clock edge
Negative clock edge to start of
valid data
End of valid data to negative
clock edge
4.5
0
ns
ns
ns
ns
Data Output Transition Time, SDR (SD Core) t12
Data Output Transition Time, SDR (CP Core)
Data Output Transition Time, SDR (CP Core)
t13
t14
2.5
0.2
DATA AND CONTROL INPUTS4
Input Setup Time (Digital Input Port)
t17
HS_IN1, VS_IN1
HS_IN2, VS_IN2
DE_IN, data inputs
HS_IN1, VS_IN1
HS_IN2, VS_IN2
DE_IN, data inputs
9.5
ns
2
−4
ns
ns
Input Hold Time (Digital Input Port)
t18
0.8
ns
1 Guaranteed by characterization.
2 With a bus line load less than 100 pF.
3 Timing figures obtained using default drive strength value.
4 TTL input values are 0 V to 3 V, with rise/fall times ≥ 3 ns, measured between the 10% and 90% points.
Rev. C | Page 6 of 28
Data Sheet
ADV7800
TIMING DIAGRAMS
t3
t5
t3
SDA1/SDA2
t6
t1
SCLK1/SCLK2
t2
t7
t4
t8
Figure 3. I2C Timing
t9
t10
LLC
t11
t12
P0 TO P53, VS_OUT,
HS_OUT, FLD_DE_OUT
Figure 4. Pixel Port and Control SDR Output Timing (SD Core)
t9
t10
LLC
t13
t14
P0 TO P53, VS_OUT,
HS_OUT, FLD_DE_OUT
Figure 5. Pixel Port and Control SDR Output Timing (CP Core)
DCLK_IN
t18
HS_IN1,
VS_IN1,
HS_IN2,
VS_IN2,
DE_IN
CONTROL
INPUTS
P30 TO P39,
P40 TO P43,
P44 TO P53
t17
Figure 6. Digital Input Port and Control Input Timing
Rev. C | Page 7 of 28
ADV7800
Data Sheet
ANALOG SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR),
DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V. TA = 0°C to 85°C, unless otherwise noted. Recommended analog
input video signal range is 0.5 V to 1.6 V, typically 1 V p-p. Recommended external clamp capacitor value is 0.1 μF.
Table 4.
Parameter1, 2
Test Conditions
Min
Typ
Max
Unit
CLAMP CIRCUITRY
Input Impedance3
Input Impedance of Pin 90 (FB)
CML
Clamps switched off
10
20
2.0
MΩ
kΩ
V
ADC Full-Scale Level
ADC Zero-Scale Level
ADC Dynamic Range
Clamp Level (When Locked)
CML + 0.8
CML − 0.8
1.6
V
V
V
V
V
V
V
V
V
V
mA
mA
µA
µA
CVBS input
CML − 0.292
CML − 0.3
CML − 0.292
CML − 0
CML − 0.3
CML − 0
CML − 0.3
0.75
SCART RGB input (R, G, B signals)
S-Video input (Y signal)
S-Video input (C signal)
Component input (Y signal)
Component input (Pr, Pb signals)
PC RGB input (R, G, B signals)
SDP only
SDP only
SDP only
SDP only
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
0.9
17
17
1 The minimum/maximum specifications are guaranteed over 0°C to 85°C.
2 Guaranteed by characterization.
3 Except Pin 90 (FB).
Rev. C | Page 8 of 28
Data Sheet
ADV7800
ABSOLUTE MAXIMUM RATINGS
Table 5.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part, the user is
advised to turn off any unused ADCs.
Parameter
Rating
AVDD to AGND
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
4.0 V
2.2 V
2.2 V
4.0 V
2.7 V
The junction temperature must always stay below the
maximum junction temperature (TJ MAX) of 125°C. This
equation shows how to calculate the junction temperature:
DVDDIO_SDRAM to
DGND_SDRAM (DDR)
TJ = TA MAX + (θJA × WMAX
where:
A MAX = 85°C
JA = 21.0330°C/W
)
DVDDIO_SDRAM to
DGND_SDRAM (SDR)
4.0 V
T
θ
DVDDIO to AVDD
−0.3 V to +0.3 V
−0.3 V to +2 V
DVDDIO to DVDD
W
MAX = ((AVDD × IAVDD) + (DVDD × IDVDD) + (DVDDIO ×
DVDDIO_SDRAM to DVDD (DDR)
DVDDIO_SDRAM to DVDD (SDR)
AVDD to PVDD
−0.3 V to +2.5 V
−0.3 V to +3.3 V
−0.3 V to +2 V
IDVDDIO) + (PVDD × IPVDD)+(DVDD_SDRAM ×
IDVDD_SDRAM )).
AVDD to DVDD
−0.3 V to +2 V
THERMAL RESISTANCE
DVDDIO to DVDDIO_SDRAM (DDR)
DVDDIO to DVDDIO_SDRAM (SDR)
AVDD to DVDDIO_SDRAM (DDR)
AVDD to DVDDIO_SDRAM (SDR)
Digital Inputs Voltage to DGND
−0.3 V to +2 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
−0.3 V to +3.3 V
−0.3 V to +2.5 V
−0.3 V to +1.8 V
DGND − 0.3 V to DVDDIO + 0.3 V
Table 6. Thermal Resistance
Package Type
1
2
DVDDIO_SDRAM Inputs to
DGND_SDRAM
DGND_SDRAM − 0.3 V to
DVDDIO_SDRAM + 0.3 V
θJA
θJC
Unit
176-Lead LQFP
21
7
°C/W
Analog Inputs to AGND
AGND − 0.3 V to AVDD + 0.3 V
DVDDIO − 0.3 V to DVDDIO + 3.6 V
125°C
1 4-layer PCB with solid ground plane.
SCLK/SDA Data Pins to DVDDIO
2 4-layer PCB with solid ground plane (still air).
Maximum Junction Temperature
(TJ MAX
)
ESD CAUTION
Storage Temperature Range
−65°C to +150°C
260°C
Infrared Reflow Soldering (20 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 9 of 28
ADV7800
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P48
P49
P50
P51
P52
P53
DE_IN
VS_IN1
VS_IN2
INT
SCLK
SDA
ALSB
HS_IN2
HS_IN1
FUNCT1
AOUT
AIN6
PIN 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P0
DVDDIO
DGND
LLC
CS/HS_OUT
SFL/SYNC_OUT
FLD_DE_OUT
VS_OUT
DGND
AIN12
AIN5
AIN11
AIN4
ADV7800
TOP VIEW
(Not to Scale)
DVDD
AIN10
CAPC2
CAPC1
CAPY1
BIAS
AVDD
AGND
CML
REFOUT
AVDD
AGND
AGND
AIN3
AIN9
AIN2
AIN8
AIN1
AIN7
SOG
SOY
FB
SDRAM_A11
SDRAM_A9
SDRAM_A8
SDRAM_A7
SDRAM_A6
SDRAM_A5
SDRAM_A4
SDRAM_A3
SDRAM_A2
SDRAM_A1
SDRAM_A0
DGND
98
97
DVDD
96
DVDDIO_SDRAM
DGND_SDRAM
SDRAM_A10
SDRAM_BA1
SDRAM_BA0
SDRAM_CS
SDRAM_RAS
SDRAM_CAS
95
94
93
92
91
90
89
AGND
Figure 7. Pin Configuration
Rev. C | Page 10 of 28
Data Sheet
ADV7800
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1 Description
1 to 14, 155 to 158, 161 to
169, 172 to 174
P0 to P29
O
Video Pixel Output Port. See Figure 7 for details on pin mapping.
15, 79, 143, 170
16, 22, 35, 59, 77, 82, 138,
144, 160, 171, 176
DVDDIO
DGND
P
GND
Digital Input/Output Supply Voltage (3.3 V).
Digital Ground.
17
18
LLC
CS/HS_OUT
O
O
Line-Locked Output Clock for the Pixel Data.
Horizontal Synchronization or Composite Synchronization Signal. This
signal can be selected while in SDP mode.
19
SFL/SYNC_OUT
FLD_DE_OUT
O
Subcarrier Frequency Lock. This pin contains a serial output stream, which
can be used to lock the subcarrier frequency when this decoder is con-
nected to any digital video encoder from Analog Devices, Inc. SYNC_OUT
is the sliced synchronization output signal available only in CP mode.
Field Synchronization Output Signal (All Interlaced Video Modes). This pin
can also be enabled as a data enable signal (DE) to allow direct connection
to a HDMI™/DVI Tx IC.
20
O
21
VS_OUT
DVDD
SDRAM_A0 to
SDRAM_A11
O
P
O
Vertical Synchronization Output Signal (SDP and CP modes).
Digital Core Supply Voltage (1.8 V).
Address Outputs. Interface to external RAM address lines. See Figure 7 for
details on pin mapping.
23, 36, 60, 76, 137, 159, 175
24 to 34, 39
37, 47, 61
DVDDIO_SDRAM
P
External Memory Interface Digital Input/Output Supply (2.5 V for DDR, or
3.3 V for SDR).
38, 48, 62
40, 41
DGND_SDRAM
SDRAM_BA1,
SDRAM_BA0
GND
O
External Memory Interface Digital GND.
Bank Address Outputs. Interface to external RAM bank address lines.
42
SDRAM_CS
SDRAM_RAS
SDRAM_CAS
SDRAM_WE
O
O
O
O
O
SDRAM_CS is a chip select function that enables and disables the command
decoder on the RAM.
Row Address Select Command Signal. SDRAM_RAS, SDRAM_CAS,
SDRAM_WE, and SDRAM_CS define the command to the RAM.
43
44
Column Address Select Command Signal. SDRAM_RAS, SDRAM_CAS,
SDRAM_WE, and SDRAM_CS define the command to the RAM.
45
Write Enable Output Command Signal. SDRAM_RAS, SDRAM_CAS,
SDRAM_WE, and SDRAM_CS define the command to the RAM.
46, 72
SDRAM_LDM,
SDRAM_UDM
Data Mask Output. Data is masked when DM is high, for write data to the
external RAM. LDM corresponds to the data on SDRAM_DQ0 to
SDRAM_DQ7, and UDM corresponds to the data on SDRAM_DQ8 to
SDRAM_DQ15.
49
SDRAM_LDQS
I/O
I/O
Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This
is an output with read data and an input with write data. It is edge aligned
with write data and centered in read data. SDRAM_ LDQS corresponds to
the data on SDRAM_DQ0 to SDRAM_DQ7.
Data Bus. Interface to external RAM 16-bit data bus. See Figure 7 for details
on pin mapping.
50 to 57, 63 to 70
SDRAM_DQ0 to
SDRAM_DQ15
58
71
SDRAM_VREF
SDRAM_UDQS
P
I/O
1.25 V reference for DDR SDRAM interface or 1.65 V for SDR SDRAM interface.
Upper Data Strobe Pin. Data strobe pins for the RAM interface. This is an
output with read data and an input with write data. It is edge aligned with
write data and centered in read data. SDRAM_UDQS corresponds to the
data on SDRAM_DQ8 to SDRAM_DQ16.
73, 74
SDRAM_CK,
SDRAM_CK
O
Differential Clock Output. All address and control output signals to the
RAM should be sampled on the positive edge of SDRAM_CK and on the
negative edge of SDRAM_CK.
75
78
SDRAM_CKE
CLKIN
O
I
Clock Enable. This pin is used to enable the clock signals of the external RAM.
Clock Input Signal. Used in 24-bit digital input mode (for example,
processing 24-bit RGB data from a DVI/HDMI Rx IC) and also in digital CVBS
input mode.
Rev. C | Page 11 of 28
ADV7800
Data Sheet
Pin No.
80
Mnemonic
XTAL
Type1 Description
I
Crystal Input. Input pin for 28.63636 MHz crystal.
81
83
XTAL1
RESET
O
I
Crystal Output. This pin should be connected to the 28.63636 MHz crystal.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7800 circuitry.
84, 87
85, 89, 99, 100, 104
86, 88
PVDD
AGND
ELPF1, ELPF2
P
GND
I
PLL Supply Voltage (1.8 V).
Analog Ground.
External Loop Filter. The recommend external loop filter must be connected
to each ELPF pin (see Figure 8).
90
FB
I
SCART Fast Blank Input.
91
92
SOY
SOG
AIN1 to AIN12
AVDD
REFOUT
CML
I
I
I
P
O
O
O
Sync On Luma Input. Used in embedded synchronization mode.
Sync On Green Input. Used in embedded synchronization mode.
Analog Video Input Channels. See Figure 7 for details on pin mapping.
Analog Supply Voltage (3.3 V).
Internal Voltage Reference Output.
Common-Mode Level Pin Used for the Internal ADCs.
93 to 98, 110 to 115
101, 105
102
103
106
BIAS
External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ)
between the pin and ground.
107
108, 109
116
117
118
CAPY1
CAPC1, CAPC2
AOUT
FUNCT1
HS_IN1
I
I
O
I
I
ADC Capacitor Network.
ADC Capacitor Network.
Analog Monitor Output.
SCART Function Select Input.
Horizontal Synchronization Input Signal. Used in CP mode for 5-wire
timing mode.
119
120
HS_IN2
I/O
I
Horizontal Synchronization Input Signal. Used in 24-bit digital input mode
port mode (for example, processing 24-bit RGB data from an HDMI Rx IC).
HS_IN2 in conjunction with VS_IN2 can be configured as a fast I2C interface
for teletext data extraction. HS_IN2 is used as the I2C port serial clock input.
ALSB selects the I2C address for the ADV7800 control. ALSB set to Logic 0
configures the address for a write to the input/output port of 0x40. ALSB
set to Logic 1 configures the address for a write to the input/output port of
0x42.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).
Interrupt Output. This pin can be active low or active high. When SDP/CP
status bits change, this pin triggers. The set of events that triggers an
interrupt is under user control.
ALSB
121
122
123
SDA
SCLK
INT
I/O
I
O
124
VS_IN2
I/O
Vertical Synchronization Input Signal. Used in 24-bit digital input mode (for
example, processing 24-bit RGB data from an DVI/HDMI Rx IC). VS_IN2 in
conjunction with HS_IN2 can be configured as a fast I2C interface for
teletext data extraction. VS_IN2 is used as the I2C port serial data
input/output pins.
125
126
VS_IN1
DE_IN
I
I
Vertical Synchronization Input Signal.
Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from an DVI/HDMI Rx IC).
127 to 136, 139 to 142, 145
to 154
P30 to P53
I/O
Video Pixel Input/Output Port. See Figure 7 for details on pin mapping.
1 GND = ground, I = input, I/O = input/output, O = output, P = power.
Rev. C | Page 12 of 28
Data Sheet
ADV7800
THEORY OF OPERATION
KEY FEATURES
Analog front-end features include
•
•
•
•
Four 150 MHz, 10-bit ADCs that enable true 10-bit video
decoding
The ADV7800 is a high quality, single-chip, multiformat 3D
comb filter video decoder, and graphics digitizer. Key features
of the device include
12-channel analog input mux that enables multiple source
connections without the requirement of an external mux
•
•
•
•
•
•
•
Four 10-bit ADCs
Four current and voltage clamp control loops that ensure
any dc offsets are removed from the video signal
NTSC/PAL/SECAM video decoder
Adaptive 3D comb filtering
SCART functionality and SD RGB overlay on CVBS
controlled by fast blank input
3D digital noise reduction
Advanced frame time-base correction (TBC)
Composite, S-Video, YPrPb/RGB SCART support
•
•
SCART source switching detection through FUNCT1 input
Four programmable antialias filters on standard definition
video signals and enhance definition
YPrPb component HD and RGB graphics
input support
•
CVBS monitor output
•
30-bit digital YPrPb/RGB output supporting 10-bit deep
color
STANDARD DEFINITION PROCESSOR
The standard definition processor (SDP) is capable of decoding
a large selection of baseband video signals in composite, S-Video,
and YUV formats. The video standards supported by the SDP
include PAL, PAL 60, PAL M, PAL N, PAL NC, NTSC M/J,
NTSC 4.43, and SECAM. The ADV7800 can automatically
detect the video standard and process it accordingly. The
ADV7800 can process video up to 525p/625p formats.
ANALOG FRONT END
The ADV7800 analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the
SDP or CP.
The front end includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7800 without
the requirement of an external mux. Current and voltage clamps
are positioned in front of each ADC to ensure the video signal
remains within the range of the converter.
The SDP has a 3D temporal comb filter and a 5-line adaptive
2D comb filter that gives superior chrominance and luminance
separation when decoding a composite video signal. This highly
adaptive filter automatically adjusts its processing mode according
to the video standard and signal quality with no user interven-
tion required. The SDP has an IF filter block that compensates
for attenuation in the high frequency chroma spectrum due
to a tuner SAW filter. The SDP has specific luminance and
chrominance parameter controls for brightness, contrast,
saturation, and hue.
The ADCs are configured to run up to 4× oversampling mode
when decoding composite and S-Video inputs or components
up to 525i and 625i. 2× oversampling is available for 525p and
625p. All other video standards are 1× oversampled. In
oversampling the video signals, a reduction in the cost and
complexity of external antialiasing filters can be obtained with the
benefit of an increased signal-to-noise ratio (SNR).
The ADV7800 implements a patented adaptive digital line length
tracking (ADLLT) algorithm to track varying video line lengths
from sources such as a VCR. ADLLT enables the ADV7800 to
track and decode poor quality video sources (such as VCRs)
and noisy sources (such as tuner outputs, VCRs, and camcor-
ders). Frame TBC ensures stable clock synchronization between
the decoder and the downstream devices to prevent disruptions.
Optional internal antialiasing filters with programmable
bandwidth are positioned in front of each ADC. These filters
can be used to band-limit standard definition video signals,
removing spurious, out-of-band noise.
The ADV7800 can support simultaneous processing of
CVBS and RGB standard definition signals to enable SCART
compatibility and overlay functionality. A combination of
CVBS and RGB inputs can be mixed and can be output under
the control of I2C registers and the fast blank pin.
The SDP also contains both a luma transient improvement
(LTI) and a chroma transient improvement (CTI) processor.
This processor increases the edge rate on the luma and chroma
transitions, resulting in a sharper video image.
Rev. C | Page 13 of 28
ADV7800
Data Sheet
The SDP has a Macrovision® detection circuit, which allows
Type I, Type II, and Type III Macrovision protection levels. The
decoder is also fully robust to all Macrovision signal inputs.
VBI DATA PROCESSOR
The VBI data processor (VDP) of the ADV7800 is capable of
slicing multiple vertical blanking interval data standards on SD
video and component video. The VDP decodes the VBI data on
the incoming CVBS/YC or YUV data processed by the SDP
core. It can also decode VBI data on the luma channel of YUV
data processed through the CP core.
SDP features include
•
•
•
Full automatic detection and autoswitching of all
worldwide standards (PAL, NTSC, and SECAM)
Advanced adaptive 3D comb with concurrent 3D noise
reduction (using either external DDR or SDR memory)
The VDP can process a variety of VBI data services, such as
•
•
•
•
•
•
Teletext
Adaptive 2D 5-line comb filters for NTSC and PAL that
give superior chrominance and luminance separation for
composite video
Video programming system (VPS)
Vertical interval time codes (VITC)
Closed captioning (CC) and extended data service (EDS)
Wide screen signaling (WSS)
•
Automatic gain control with white peak mode that
ensures the video is always processed without loss of the
video processing range
Copy generation management system (CGMS,
CGMS Type B)
•
•
Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
•
•
Gemstar® 1×/2× electronic program guide compatible
IF filter block that compensates for high frequency luma
attenuation due to a tuner SAW filter
Extended data service (SDS); the data extracted can be read
back over a fast I2C interface
•
•
•
LTI and CTI
COMPONENT PROCESSOR
Vertical and horizontal programmable luma peaking filters
The component processor (CP) is capable of decoding and
digitizing a wide range of component video formats in any
color space. The CP can accept video data from the analog front
end or from the HDMI receiver. Component video standards
supported by the CP include 525i, 625i, 525p, 625p, 720p, 1080i,
1080p, and VGA (up to SXGA at 75 Hz), and many other
standards.
10-bit deep color processing path from front to back end in
RGB/YCrCb formats
•
•
Macrovision copy protection detection on composite
and S-Video for all worldwide formats (PAL, NTSC,
and SECAM)
4× oversampling (54 MHz) for CVBS, S-Video, and
YUV modes
A fully programmable any-to-any, 3 × 3 color space conversion
(CSC) matrix is placed before the CP. This enables YPrPb-to-
RGB and RGB-to-YCrCb conversions of video data coming
from the analog front end or from the HDMI receiver. Many
other standards of color space can be implemented using the
color space converter.
•
•
•
2× oversampling (54 MHz) for 525p and 625p modes
Line-locked clock output (LLC)
Free run output mode that provides stable timing when no
video input is present
•
•
Internal color bar test pattern
The CP of the ADV7800 contains an automatic gain control
(AGC) block. The AGC is followed by a clamp circuit that
ensures the video signal is clamped to the correct blanking level.
Automatic adjustments within the CP include gain (contrast)
and offset (brightness). Manual adjustment controls are also
supported. In cases where no embedded synchronization is
preset, the video gain can be set manually.
Advanced TBC with frame synchronization, which ensures
nominal clock and data for nonstandard input
•
•
Interlace-to-progressive conversion for 525i and 625i
formats, enabling direct drive of HDMI Tx devices
Color controls that include hue, brightness, saturation, and
contrast
•
•
•
Differential gain (DG), typically 0.45%
Differential phase (DP), typically 0.45°
Video SNR, typically 61 dB
Rev. C | Page 14 of 28
Data Sheet
ADV7800
The CP contains circuitry to enable the detection of Macrovision
encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is
designed to be fully robust to these types of signals.
•
•
•
Contrast, brightness, hue, and saturation controls
32-phase DLL that allows optimum pixel clock sampling
Automatic detection of synchronization source and
polarity by SSPD block
CP features include
•
525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other
HDTV formats supported
•
•
Standard identification enabled by STDI block
RGB that can be color space converted to YCrCb and
decimated to a 4:2:2 format for videocentric back-end IC
interfacing
•
Automatic adjustments including gain (contrast) and
offset (brightness); manual adjustment controls also
supported
•
•
DE output signal that is supplied for direct connection to
HDMI/DVI Tx IC
•
•
•
Support for analog component YPrPb and RGB video
formats with embedded synchronization or with separate
HS, VS, or CS
Arbitrary pixel sampling support for nonstandard video
sources
Any-to-any, 3 × 3 color space conversion matrix that
supports YCrCb-to-RGB and RGB-to-YCrCb, fully
programmable or preprogrammable configurations
ADDITIONAL FEATURES
The ADV7800 also includes
Synchronization source polarity detector (SSPD) that
determines the source and polarity of the synchronization
signals that accompany the input video
•
HS, VS, FIELD, and DE output signals with programmable
position, polarity, and width
•
Programmable interrupt request output pin (
signals SDP/CP status changes
)that
INT
•
•
•
•
•
Macrovision copy protection detection on component
formats (525i, 625i, 525p, and 625p)
•
•
•
Two I2C host port interface (control and VBI) support
Free run output mode that provides stable timing when no
video input is present
Integrated programmable antialiasing filters
176-lead, 26 mm × 26 mm, RoHS-compliant LQFP
Arbitrary pixel sampling support for nonstandard
video sources
For more detailed product information about the ADV7800,
email video.products@analog.com or contact a local Analog
Devices sales representative.
150 MHz conversion rate, which supports RGB input
resolutions up to 1280 × 1024 at 75 Hz
Automatic or manual clamp-and-gain controls for
graphics modes
Rev. C | Page 15 of 28
ADV7800
Data Sheet
EXTERNAL MEMORY REQUIREMENTS
SINGLE DATA RATE (SDR)
DOUBLE DATA RATE (DDR)
The ADV7800 uses DDR external memory for simultaneous 3D
comb, frame synchronizer, and 3D-DNR operation.
The ADV7800 uses SDR external memory for 3D comb, frame
synchronizer operation, or 3D-DNR nonconcurrent operation.
•
•
128 Mb DDR SDRAM minimum memory requirement
•
•
64 Mb SDR SDRAM minimum memory requirement
The memory architecture required is four banks of
2 Mb × 16 (8M16)
The memory architecture required is four banks of
1 Mb × 16 (4M16)
•
•
•
Speed grade of 133 MHz at CAS latency (CL) 2.5 is
required
•
•
Speed grade of 133 MHz at CAS latency (CL) 3 is required
22 Ω series termination resistors are recommended for this
configuration
Termination resistors not recommended for this
configuration
•
Recommended memory that is compatible with the
ADV7800 includes the MT48LC4M16A2 from Micron
Recommended memory that is compatible with the
ADV7800 includes K4H281638B-TCB0 from Samsung,
the MT46V8M16-TGP-75 from Micron, and the
HYB25D128160CE-6 from Infineon
Rev. C | Page 16 of 28
Data Sheet
ADV7800
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
The external loop filter components for the ELPF pins should be placed as close as possible to the respective pins. Figure 8 shows the
recommended component values.
PIN 86 (ELPF1)
PIN 88 (ELPF2)
1.69kΩ
10nF
160Ω
39nF
82nF
820nF
PVDD = 1.8V
PVDD = 1.8V
Figure 8. ELPF Components
Rev. C | Page 17 of 28
ADV7800
Data Sheet
TYPICAL CONNECTION DIAGRAMS
ADV7800
Figure 9. Typical Connection Diagram (External DDR Memory)
Rev. C | Page 18 of 28
Data Sheet
ADV7800
ADV7800
Figure 10. Typical Connection Diagram (External SDR Memory)
Rev. C | Page 19 of 28
ADV7800
Data Sheet
PIXEL INPUT/OUTPUT FORMATTING
There are several modes in which the ADV7800 pixel port
can be configured. These modes are under the I2C control of
OP_FORMAT_SEL[5:0].
•
•
•
DDR 8-/10-bit 4:2:2 YCrCb for all standards
DDR 24-/30-bit 4:4:4 RGB for all standards
Simultaneous output modes 16-/20-bit YCrCb and
8-/10-bit 4:2:2 YCrCb up to 525i/525p and 625i/625p
PIXEL DATA OUTPUT MODES HIGHLIGHTS
The ADV7800 has a flexible pixel port, which can be configured
in a variety of formats to accommodate downstream ICs. See
Table 8 and Table 9 for more information on each mode. The
output pixel port features include
DIGITAL VIDEO INPUT PORT HIGHLIGHTS
The ADV7800 contains a 24-bit digital input port. Main
features are as follows:
•
Support for 24-bit RGB input data from the DVI/HDMI
Rx IC, pass-through, or output converted to 4:2:2 YCrCb
•
8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS_OUT, VS_OUT, and FLD_DE_OUT pin
timing
•
Support for 24-bit 4:4:4, 16-/20-bit 4:2:2 525i, 625i, 525p,
625p, 1080i, 720p, 1080p, and VGA to SXGA at 75 Hz
input data from the DVI/HDMI Rx IC chip, pass-through,
or output converted to 4:2:2 YCrCb
•
•
16-/20-/24-bit YCrCb with embedded time codes and/or
HS_OUT, VS_OUT, and FLD_DE_OUT pin timing
24-/30-bit YCrCb/RGB with embedded time codes and/or
HS_OUT, VS_OUT, and FLD_DE_OUT pin timing
•
Dedicated synchronization and pixel port inputs
Rev. C | Page 20 of 28
Data Sheet
ADV7800
Table 8. SDR Pixel Port Output Modes1
OP_FORMAT_SEL [5:0]
0x00
0x01
0x05
0x06
0x0A
0x2C
8-Bit SDR
ITU-656 Mode 1
10-Bit SDR ITU-656
Mode 1
16-Bit SDR ITU-656
4:2:2 Mode 1
20-Bit SDR ITU-656
4:2:2 Mode 1
24-Bit SDR 4:4:4
Mode 1
24-Bit SDR 4:4:4
Mode 2
Pixel Output
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
Y7, Cb7, Cr7
Y9, Cb9, Cr9
Y7
Y9
G7
G6
G5
G4
G3
G2
G1
G0
Z
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
R7
R6
R5
R4
R3
R2
R1
R0
Z
Y6, Cb6, Cr6
Y8, Cb8, Cr8
Y6
Y8
Y5, Cb5, Cr5
Y7, Cb7, Cr7
Y5
Y7
Y4, Cb4, Cr4
Y6, Cb6, Cr6
Y4
Y6
Y3, Cb3, Cr3
Y5, Cb5, Cr5
Y3
Y5
Y2, Cb2, Cr2
Y4, Cb4, Cr4
Y2
Y4
Y1, Cb1, Cr1
Y3, Cb3, Cr3
Y1
Y3
Y0, Cb0, Cr0
Y2, Cb2, Cr2
Y0
Y2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Y1, Cb1, Cr1
Z
Y1
Y0, Cb0, Cr0
Z
Y0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Cb7, Cr7
Cb9, Cr9
B7
B6
B5
B4
B3
B2
B1
B0
Z
Cb6, Cr6
Cb8, Cr8
Cb5, Cr5
Cb7, Cr7
Cb4, Cr4
Cb6, Cr6
Cb3, Cr3
Cb5, Cr5
Cb2, Cr2
Cb4, Cr4
Cb1, Cr1
Cb3, Cr3
Cb0, Cr0
Cb2, Cr2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Cb1, Cr1
Cb0, Cr0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
R7
R6
R5
R4
R3
R2
R1
R0
Z
P8
P7
P6
P5
P4
Z
P3
Z
P2
Z
P1
Z
P0
Z
Z
1 It is recommended to print this table (located on this page and the following page) and read as one horizontal expanded table.
Rev. C | Page 21 of 28
ADV7800
Data Sheet
OP_FORMAT_SEL [5:0]
0x2D
0x2E
0x0B
0x28
0x29
24-Bit SDR 4:4:4
Mode 1
24-Bit SDR 4:4:4
Mode 1
30-Bit SDR 4:4:4
Mode 1
16-Bit and 8-Bit SDR 4:2:2
Mode 1 Parallel Output
20-Bit and 10-Bit SDR 4:2:2
Mode 1 Parallel Output
Pixel Output
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
Z
B7
B6
B5
B4
B3
B2
B1
B0
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
Z
G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Main Y7
Main Y9
Main Y6
Main Y8
Main Y5
Main Y7
Main Y4
Main Y6
Main Y3
Main Y5
Main Y2
Main Y4
Main Y1
Main Y3
Main Y0
Main Y2
Z
Main Y1
Z
Main Y0
Main Cb7, Cr7
Main Cb6, Cr6
Main Cb5, Cr5
Main Cb4, Cr4
Main Cb3, Cr3
Main Cb2, Cr2
Main Cb1, Cr1
Main Cb0, Cr0
Z
Main Cb9, Cr9
Main Cb8, Cr8
Main Cb7, Cr7
Main Cb6, Cr6
Main Cb5, Cr5
Main Cb4, Cr4
Main Cb3, Cr3
Main Cb2, Cr2
Main Cb1, Cr1
Main Cb0, Cr0
Aux Y9, Cb9, Cr9
Aux Y8, Cb8, Cr8
Aux Y7, Cb7, Cr7
Aux Y6, Cb6, Cr6
Aux Y5, Cb5, Cr5
Aux Y4, Cb4, Cr4
Aux Y3, Cb3, Cr3
Aux Y2, Cb2, Cr2
Aux Y1, Cb1, Cr1
Aux Y0, Cb0, Cr0
Z
Aux Y7, Cb7, Cr7
Aux Y6, Cb6, Cr6
Aux Y5, Cb5, Cr5
Aux Y4, Cb4, Cr4
Aux Y3, Cb3, Cr3
Aux Y2, Cb2, Cr2
Aux Y1, Cb1, Cr1
Aux Y0, Cb0, Cr0
Z
P8
P7
P6
P5
P4
Z
Z
P3
Z
Z
P2
Z
Z
P1
Z
Z
P0
Z
Z
Z
Rev. C | Page 22 of 28
Data Sheet
ADV7800
Table 9. DDR Pixel Port Output Modes1
OP_FORMAT_SEL [5:0]
0x10
0x11
0x3D
0x3E
24-Bit DDR 4:2:2 RGB (CLK/2) mode 2
8-Bit DDR ITU-656
10-Bit DDR ITU-656
24-Bit DDR 4:2:2 RGB (CLK/2) Mode 1
Pixel Output
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
Clock Rise
Clock Fall
Clock Rise
Clock Fall
Clock Rise
B7-0
B6-0
B5-0
B4-0
B3-0
B2-0
B1-0
B0-0
R7-0
R6-0
R5-0
R4-0
R3-0
R2-0
R1-0
R7-0
G7-0
G6-0
G5-0
G4-0
G3-0
G2-0
G1-0
G0-0
Z
Clock Fall
B7-1
B6-1
B5-1
B4-1
B3-1
B2-1
B1-1
B0-1
R7-1
R6-1
R5-1
R4-1
R3-1
R2-1
R1-1
R7-1
G7-1
G6-1
G5-1
G4-1
G3-1
G2-1
G1-1
G0-1
Z
Clock Rise
R7-0
R6-0
R5-0
R4-0
R3-0
R2-0
R1-0
R0-0
G7-0
G6-0
G5-0
G4-0
G3-0
G2-0
G1-0
G0-0
B7-0
B6-0
B5-0
B4-0
B3-0
B2-0
B1-0
B0-0
Z
Clock Fall
R7-1
R6-1
R5-1
R4-1
R3-1
R2-1
R1-1
R0-1
G7-1
G6-1
G5-1
G4-1
G3-1
G2-1
G1-1
G0-1
B7-1
B6-1
B5-1
B4-1
B3-1
B2-1
B1-1
B0-1
Z
Cb7, Cr7
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Z
Cb9, Cr9
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Z
Cb6, Cr6
Cb8, Cr8
Cb5, Cr5
Cb7, Cr7
Cb4, Cr4
Cb6, Cr6
Cb3, Cr3
Cb5, Cr5
Cb2, Cr2
Cb4, Cr4
Cb1, Cr1
Cb3, Cr3
Cb0, Cr0
Cb2, Cr2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Cb1, Cr1
Z
Cb0, Cr0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
P8
Z
Z
P7
Z
Z
P6
Z
Z
P5
Z
Z
P4
Z
Z
Z
Z
Z
Z
P3
Z
Z
Z
Z
Z
Z
P2
Z
Z
Z
Z
Z
Z
P1
Z
Z
Z
Z
Z
Z
P0
Z
Z
Z
Z
Z
Z
1 It is recommended to print this table (located on this page and the following page) and read as one horizontal expanded table.
Rev. C | Page 23 of 28
ADV7800
Data Sheet
OP_FORMAT_SEL [5:0]
0x38
0x39
0x3C
16-Bit and 8-Bit DDR 4:2:2 Mode 1
Parallel Output (CLK/2)
20-Bit and 10-Bit DDR 4:2:2 Mode 1
Parallel Output (CLK/2)
24-Bit DDR 4:2:2RGB (CLK/2)
Pixel Output
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
Clock Rise
Main Y7
Main Y6
Main Y5
Main Y4
Main Y3
Main Y2
Main Y1
Main Y0
Z
Clock Fall
Main Y7
Main Y6
Main Y5
Main Y4
Main Y3
Main Y2
Main Y1
Main Y0
Z
Clock Rise
Main Y9
Clock Fall
Main Y9
Main Y8
Main Y7
Main Y6
Main Y5
Main Y4
Main Y3
Main Y2
Main Y1
Main Y0
Main Cr9
Main Cr8
Main Cr7
Main Cr6
Main Cr5
Main Cr4
Main Cr3
Main Cr2
Main Cr1
Main Cr0
Aux Y9
Clock Rise
G7-0
G6-0
G5-0
G4-0
G3-0
G2-0
G1-0
G0-0
B7-0
B6-0
B5-0
B4-0
B3-0
B2-0
B1-0
B0-0
R7-0
R6-0
R5-0
R4-0
R3-0
R2-0
R1-0
R0-0
Z
Clock Fall
G7-1
G6-1
G5-1
G4-1
G3-1
G2-1
G1-1
G0-1
B7-1
B6-1
B5-1
B4-1
B3-1
B2-1
B1-1
B0-1
R7-1
R6-1
R5-1
R4-1
R3-1
R2-1
R1-1
R0-1
Z
Main Y8
Main Y7
Main Y6
Main Y5
Main Y4
Main Y3
Main Y2
Main Y1
Z
Z
Main Y0
Main Cb7
Main Cb6
Main Cb5
Main Cb4
Main Cb3
Main Cb2
Main Cb1
Main Cb0
Z
Main Cr7
Main Cr6
Main Cr5
Main Cr4
Main Cr3
Main Cr2
Main Cr1
Main Cr0
Z
Main Cb9
Main Cb8
Main Cb7
Main Cb6
Main Cb5
Main Cb4
Main Cb3
Main Cb2
Main Cb1
Main Cb0
Aux Cb9, Cr9
Aux Cb8, Cr8
Aux Cb7, Cr7
Aux Cb6, Cr6
Aux Cb5, Cr5
Aux Cb4, Cr4
Aux Cb3, Cr3
Aux Cb2, Cr2
Aux Cb1, Cr1
Aux Cb0, Cr0
Z
Z
Aux Cb7, Cr7
Aux Cb6, Cr6
Aux Cb5, Cr5
Aux Cb4, Cr4
Aux Cb3, Cr3
Aux Cb2, Cr2
Aux Cb1, Cr1
Aux Cb0, Cr0
Z
Aux Y7
Aux Y6
Aux Y5
Aux Y4
Aux Y3
Aux Y2
Aux Y1
Aux Y0
Z
P8
Aux Y8
P7
Aux Y7
P6
Aux Y6
P5
Aux Y5
P4
Aux Y4
Z
Z
P3
Aux Y3
Z
Z
P2
Aux Y2
Z
Z
P1
Aux Y1
Z
Z
P0
Z
Z
Aux Y0
Z
Z
Rev. C | Page 24 of 28
Data Sheet
ADV7800
Table 10. Pixel Port Input Modes
IP_DATA_SEL[5:0]
0x00
0x01
0x04
0x06
0x07
Pixel Input
24-Bit 4:4:4 Input 20-Bit 4:2:2 Input 16-Bit 4:2:2 Input 10-Bit 4:2:2 Input 8-Bit 4:2:2 Input
P53
P52
P51
P50
P49
P48
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
G7
Y9
Y8
Y7
Y6
Y7
Y6
Y5
Y4
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
R7
R6
R5
R4
R3
R2
R1
R0
Y5
Y4
Y3
Y2
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Y1
Y0
Z
Z
Cb1, Cr1
Cb0, Cr0
Z
Y3
Y2
Y1
Y0
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Rev. C | Page 25 of 28
ADV7800
Data Sheet
OUTLINE DIMENSIONS
26.20
26.00 SQ
25.80
0.75
0.60
0.45
1.60
MAX
133
132
176
1
PIN 1
24.20
24.00 SQ
23.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.15
0.05
89
44
45
SEATING
PLANE
0.08 MAX
COPLANARITY
88
VIEW A
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90° CCW
LEAD PITCH
COMPLIANT TO JEDEC STANDARDS MS-026-BGA
Figure 11. 176-Lead Low Profile Quad Flat Package [LQFP]
(ST-176)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ST-176
ST-176
ADV7800BSTZ-80
ADV7800BSTZ-150
EVAL-ADV7800EB1Z
0°C to +85°C
0°C to +85°C
176-Lead Low Profile Quad Flat Package (LQFP)
176-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board (External DDR SD Memory)
1 Z = RoHS Compliant Part.
Rev. C | Page 26 of 28
Data Sheet
NOTES
ADV7800
Rev. C | Page 27 of 28
ADV7800
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06760-0-8/11(C)
Rev. C | Page 28 of 28
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