ADV7850_技术文档

Complete AV Front End

ADV7850

Data Sheet

Audio codec

FEATURES

24-bit, 48 kHz stereo codec

5-channel stereo analog input mux with a stereo output

Main features

4-port HDMI Xpressview receiver

170 MHz video and graphics digitizer

Complete 3D comb video decoder

Stereo audio codec

High speed serial output (TMDS)

HDMI support

General

Internal EDID RAM for HDMI and graphics

Dual STDI (standard identification) function support for

dual input detection

Simultaneous analog processing and HDMI monitoring for

fast input switching

3D TV support

Audio return channel (ARC)

APPLICATIONS

Extended colorimetry, including sYCC601, Adobe RGB,

Adobe YCC 601, and xvYCC extended gamut color

4:1 HDMI 297 MHz receiver

HDTVs, set-top boxes, AV receivers, projectors, video matrix

switchers

Fast switching of HDMI ports (Xpressview)

3D TV video format support

FUNCTIONAL BLOCK DIAGRAM

DDR2 SDRAM

HDCP 1.4 support with internal HDCP keys

Adaptive HDMI equalizer

CVBS × 2/YC

SCART RGB

+ CVBS

CVBS

SCART G

SCART B

SCART R

Full HDCP repeater support

ADC

SDP

CVBS

3D COMB

YC

HS/VS/DE

S/PDIF interface for 4 single-mode ARC outputs

Up to 36-bit Deep Color support

Complete HDMI audio support

CVBS

YC

CLK

DATA

SCART

YPbPr

Audio extraction available

HDMI

GRAPHICS

RGB

Support for up to 16 VSIs (including THX Media Director^™)

High speed serial output (TMDS 297 MHz)

Full transmitter support including encryption

Can operate in a transceiver configuration

Audio insertion available

CP

YPbPr

525p/625p

720p/1080i

1080p/

Y/G

Pb/B

Pb/R

HS/VS/DE

AUDIO L/R

5

CLK

DATA

UXGA

RGB

AUDIO L/R

ADC

DAC

2

Video and graphics digitizer

AUDIO L/R

HP L/R

I S INTERFACE

Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA)

SD, ED, and HD TV support up to 1080p at 60 Hz

Low refresh rates (24 Hz/25 Hz/30 Hz) support for

720p/1080p

13-channel analog video input channels with 2 outputs

3D comb video decoder

Full NTSC/PAL/SECAM color standards support

Adaptive 3D comb filter video decoder

Advanced time-base correction (TBC) with frame

synchronization for SD formats

36

HDMI 1

HDMI 2

HDMI 3

HDMI 4

TMDS

DDC

2

I S

AUDIO

4

OUTPUT

5

S/PDIF

DSD/DST

HBR

DEEP

TMDS

DDC

COLOR

HDMI Rx

MCLK

TMDS

DDC

MCLK

SCLK

TMDS

DDC

FAST

SWITCH

SCLK

HDCP

KEYS

ARC

4

S/PDIF

ARC

5V HDMI + VGA

5

5V EDID

REG

SPI

ADV7850

INTERFACE

Complete SCART support

Advanced VBI data slicer

EDID EPROM

IF compensation filters

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7850

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Power-Up Sequence ................................................................... 24

Power-Down Sequence.............................................................. 24

Power Supply requirements ...................................................... 24

Functional Overview...................................................................... 25

HDMI Receiver........................................................................... 25

Analog Front End....................................................................... 25

Standard Definition Processor ................................................. 26

Component Processor ............................................................... 26

VBI Data Processor (VDP)....................................................... 27

TMDS Output............................................................................. 27

External Memory Requirements.............................................. 27

Other Features ............................................................................ 27

Audio Overview.............................................................................. 28

Analog Audio MUX Functionality .......................................... 28

Audio Codec Functionality....................................................... 28

Register Map Architecture ............................................................ 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications..................................................................................... 5

Electrical Characteristics............................................................. 5

Power Specifications .................................................................... 6

Analog Specifications................................................................... 7

Video Specifications..................................................................... 9

Timing Characteristics .............................................................. 10

Timing Diagrams........................................................................ 11

Absolute Maximum Ratings.......................................................... 13

Package Thermal Performance................................................. 13

ESD Caution................................................................................ 13

Pin Configuration and Function Descriptions........................... 14

Power Supply Sequencing.............................................................. 24

REVISION HISTORY

5/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

Data Sheet

ADV7850

GENERAL DESCRIPTION

also includes an integrated equalizer that ensures robust opera-

tion of the interface with cable lengths up to 30 meters. The HDMI

receiver has advanced audio functionality, such as a mute flag,

that prevents audible extraneous noise in the audio output.

The ADV7850 is a high quality, single chip, multiformat video

decoder graphics digitizer with an integrated 4:1 multiplexed

HDMI® receiver.

This multiformat 3D comb filter decoder supports the conversion

of PAL, NTSC, and SECAM standards in the form of a composite

or an S-Video input signal into a HDMI output stream. SCART

and overlay functionality are enabled by the ability of the

ADV7850 to process CVBS and standard definition RGB signals

simultaneously.

In addition, the HDMI receiver incorporates internal EDID

support, which can be made available in full power, power-

down, and power-off modes. An internal regulator supplies

external EDID memory from the HDMI 5 V signal in power-

off mode.

The ADV7850 incorporates Xpressview™ fast switching on all

HDMI input ports. Using the Analog Devices, Inc., hardware-

based HDCP engine that minimizes software overhead,

Xpressview technology allows fast switching between any two

HDMI input ports in less than 1 second.

The ADV7850 contains one main component processor (CP)

that processes YPrPb and RGB component formats, including

RGB graphics. The ADV7850 can operate in quad HDMI and

analog input mode, thus allowing for fast switching between the

analog video inputs and HDMI.

The ADV7850 offers a flexible audio output port for the audio

data decoded from the HDMI stream. HDMI audio formats,

including super audio CD (SACD) via DSD, DST, and HBR are

supported.

The ADV7850 supports the decoding of a component RGB/

YPrPb video signal into a HDMI output stream. The support

for component video includes 525i, 625i, 525p, 625p, 720p,

1080i, 1080p, and 1250i standards, as well as many other

SMPTE and HD standards.

The ADV7850 also features the single mode audio return

channel (ARC) feature. ARC simplifies cabling by combining

upstream audio capability in a conventional HDMI cable.

The ADV7850 supports graphics digitization. The ADV7850 is

capable of digitizing RGB graphics signals from VGA to UXGA

rates and converting them into an HDMI output stream. Internal

EDID RAM is available for one graphics port.

The stereo audio ADC converts analog audio inputs and

provides the data to the back end via the HDMI interface. The

stereo audio DAC receives I²

S data from the back end and

The ADV7850 incorporates a quad input HDMI-compatible

receiver that supports all HDTV formats up to 3D 1080p 60 Hz

and 2160P 24 Hz.

converts it to analog audio output. The audio output is available

as both high impedance and a driven output, which is suitable

for driving headphones directly.

The ADV7850 supports full HDCP decryption with internal

key storage. The ADV7850 features HDCP authentication on all

ports simultaneously. The feature allows fast switching between

HDMI ports. Sync measurements and status monitoring are

also available for all HDMI ports. Each HDMI port has dedi-

cated 5 V detect and hot plug assert pins. The HDMI receiver

Fabricated in an advanced CMOS process, the ADV7850 is

provided in a 19 mm × 19 mm, 425-ball, CSP_BGA, surface-

mount, RoHS-compliant package, and is specified over the

−20°C to +70°C temperature range.

Rev. 0 | Page 3 of 32

ADV7850

Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

2

0 0 A 5 8 - 0 7 7

T E T R A R M F O T T P U U O O U A D I

R

T E T A R M F T O T P U U O O D E V I

E R L S T F I N O I T A M I C

A B M L E D R E A G M O R P

X

+ M U

I D E C O H D M C K + B L O

G I N H C I T W S T S A F

D E

Figure 2. Detailed Functional Block Diagram

Rev. 0 | Page 4 of 32

Data Sheet

ADV7850

SPECIFICATIONS

AVDD = 1.8 V 5%, VDD to GND = 1.8 V 5%, PVDD = 1.8 V 5%, TX_AVDD = 1.8 V 5%, TX_PVDD = 1.8 V 5%, SAVDD =

1.8 V 5%, SDVDD = 1.8 V 5%, CVDD = 1.8 V 5%, DVDDIO = 3.3 V 5%, TX_VDD33 = 3.3 V 5%, TVDD = 3.3 V 5%,

AC_AVDD = 3.3 V 5%. T_MINto T_MAX= −20°C to +70°C, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each ADC)

Integral Nonlinearity

N

INL

12

Bits

LSB

27 MHz (at a 12-bit level)

54 MHz (at a 12-bit level)

74.25 MHz (at a 12-bit level)

108 MHz (at a 11-bit level)

170 MHz (at a 9-bit level)

27 MHz (at a 12-bit level)

54 MHz (at a 12-bit level)

75 MHz (at a 12-bit level)

108 MHz (at a 11-bit level)

170 MHz (at a 9-bit level)

−3.0 to +8.0

−4.0 to +7.0

−3.5 to +8.0

−0.7 to +1.8

−0.7 to +0.8

−0.6 to +0.5

Differential Nonlinearity

DNL

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

V_IH

V_IL

V_IH

V_IL

C_IN

XTALN and XTALP pins

Other digital inputs

1.2

2

V

0.4

0.8

10

Input Capacitance

HDMI

pF

TMDS Differential Pin Capacitance

DIGITAL INPUTS (5 V TOLERANT)¹

Input High Voltage

Input Low Voltage

Input Current

0.3

pF

V_IH

V_IL

I_IN

3.0

V

µA

0.8

+82

−82

2.4

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

High Impedance Leakage Current

V_OH

V_OL

I_LEAK

V

µA

0.4

DDC_SCL, DDCA_SDA, DDCB_SCL,

DDCB_SDA, DDCC_SCL,

30

DDCC_SDA, DDCD_SCL,

DDCD_SDA, VGA_SCL, VGA_SDA,

SPDIF_IN, SHARED_EDID

I_LEAK

RXA_5V, RXB_5V, RXC_5V, RXD_5V

and VGA_5V

All other digital pins

20

10

µA

I_LEAK

C_OUT

µA

pF

Output Capacitance

20

¹The following pins are 5 V tolerant: HS_IN1/TRI7, HS_IN2/TRI5, VS_IN1/TRI8, VS_IN2/TRI6, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA,

DDCD_SCL, DDCD_SDA, VGA_SCL, VGA_SDA, TX_DDC_SCL, TX_DDC_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V, and VGA_5V.

Rev. 0 | Page 5 of 32

ADV7850

Data Sheet

POWER SPECIFICATIONS

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

Digital Core Power Supply

Digital I/O Power Supply

Memory Interface Analog Power Supply

Memory Interface Digital Power Supply

DPLL Power Supply

Video Analog Power Supply

Terminator Power Supply

Comparator Power Supply

Audio Block Supply

HDMI Tx Analog Power Supply

HDMI Tx Digital Power Supply

HDMI Tx PLL Regulator Power Supply

CURRENT CONSUMPTION^{1, 2, 3}

Digital Core Supply Current

Digital I/O Supply Current

DPLL Supply Current

Video Analog Supply Current

Memory Interface Analog Power Supply

Memory Interface Digital Power Supply

Comparator Supply Current

Audio Block Supply Current

HDMI Tx Analog Supply Current

HDMI Tx Digital Supply Current

HDMI Tx PLL Regulator Supply Current

Terminator Supply Current⁴

VDD

1.75

3.14

1.71

3.14

1.71

3.14

1.71

3.14

1.8

3.3

1.8

3.3

1.8

3.3

1.8

3.3

1.85

3.46

1.89

3.46

1.89

3.46

1.89

3.46

V

DVDDIO

SAVDD

SDVDD

PVDD

AVDD

TVDD

CVDD

AC_AVDD

TX_AVDD

TX_PVDD

TX_VDD33

I_VDD

I_DVDDIO

I_PVDD

400

3

36

270

4

15

300

80

20

43

2

80

280

1

1.5

0.5

1

2.5

0.5

25

440

4

45

290

5

18

350

84

25

50

5

mA

ms

I_AVDD

I_SAVDD

I_SDVDD

I_CVDD

I_{AC_AVDD}

I_{TX_AVDD}

I_{TX_PVDD}

I_{TX_VDD33}

I_TVDD

85

290

One port connected

Four ports connected

Power-Down Currents⁵

I_VDD

I_DVDDIO

I_PVDD

I_AVDD

I_SAVDD

I_SDVDD

I_TVDD

I_CVDD

I_{AC_AVDD}

I_{TX_AVDD}

I_{TX_PVDD}

I_{TX_VDD33}

t_PWRUP

Power-Up Time

¹All maximum current values are guaranteed by characterization to assist in power supply design.

²Typical current consumption values are recorded with nominal voltage supply levels, SMPTE bar video pattern, and at room temperature.

³Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature.

⁴Termination power supply includes TVDD current consumed off chip.

⁵Power-down mode entered by setting the I²C Bit POWER_DOWN high.

Rev. 0 | Page 6 of 32

Data Sheet

ADV7850

ANALOG SPECIFICATIONS

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLAMP CIRCUITRY¹

Input Impedance

Analog (AIN1 to AIN12)

ADC Midscale (CML)

ADC Full-Scale Level

ADC Zero-Scale Level

ADC Dynamic Range

Clamp Level (When Locked)

Clamps switched off

10

MΩ

0.91

V

mA

μA

CML + 0.55

CML − 0.55

1.1

CML − 0.12

CML

Component input, Y signal

Component input, Pr signal

Component input, Pb signal

PC RGB input (R, G, B signals)

CVBS input

SCART RGB input (R, G, B signals)

S-Video input (Y signal)

S-Video input (C signal)

SDP only

CML

CML − 0.12

CML − 0.205

CML

0.3

0.4

9

8

Large Clamp Source Current

Large Clamp Sink Current

Fine Clamp Source Current

Fine Clamp Sink Current

AUDIO ADC SECTION²

Number of Channels

SDP only

Stereo pair

1

50

24

Channel

µA rms

Bits

Full-Scale Input Level

Resolution

Dynamic Range (Stereo Channel)

A-Weighted

−60 dBFS with respect to full-scale

analog input

−3 dBFS with respect to full-scale

analog input

Left- and right-channel gain

mismatch

90

dB

Total Harmonic Distortion + Noise (Stereo Channel)

Gain Mismatch

−85

0.2

Crosstalk (Left to Right, Right to Left)

Gain Error

Power Supply Rejection

AUDIO ADC DIGITAL DECIMATOR FILTER CHARACTERISTICS²

Pass Band

Pass-Band Ripple

Stop Band

Stop-Band Attenuation

Group Delay

−90

−1.1

−89

dB

Input signal = 2.8 V rms

1 kHz, 300 mV p-p signal at AVDD

At 48 kHz, guaranteed by design

22.5

0.0002

26.5

100

1040

kHz

dB

kHz

dB

µs

AUDIO DAC SECTION²

Number of Auxiliary Output Channels

Resolution

Full-Scale Analog Output

Dynamic Range

Stereo pair

1

24

1.0

Channel

Bits

V rms

A-Weighted

−60 dBFS with respect to full-

scale code input

−3 dBFS with respect to full-scale

code input

93

dB

Total Harmonic Distortion + Noise

−89

Rev. 0 | Page 7 of 32

ADV7850

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

−104

0.1

Max

Unit

dB

Crosstalk (Left to Right, Right to Left)

Interchannel Gain Mismatch

Left- and right-channel gain

mismatch

Gain Error

Power Supply Rejection

1 V rms output

1 kHz, 300 mV p-p signal at AVDD

At 48 kHz, guaranteed by design

0.525

−101

dB

AUDIO DAC DIGITAL INTERPOLATION FILTER

CHARACTERISTICS²

Pass Band

21.769

0.01

23.95

26.122

75

kHz

dB

kHz

dB

Pass-Band Ripple

Transition Band

Stop Band

Stop-Band Attenuation

Group Delay

HEADPHONE AMPLIFIER²

580

µs

Measured at headphone output

with 32 Ω load

Number of Channels

Dynamic Range

A-Weighted

Stereo pair

1

Channel

−60 dBFS with respect to full-

scale code input

−3 dBFS with respect to full-scale

code input

92

dB

Total Harmonic Distortion + Noise

−86

Interchannel Gain Mismatch

Power Supply Rejection

ANALOG AUDIO MUX²

0.1

−82

dB

1 kHz, 300 mV p-p signal at AVDD

Number of Input Channels

Number of Output Channels

Gain Mismatch Between Left and Right Channels

REFERENCE SECTION

Stereo pair

5

1

5

Channel

%

Absolute Voltage V_REF

1.5

V

¹Specified for external clamp capacitor of 100 nF.

²Guaranteed by lab characterization.

Rev. 0 | Page 8 of 32

Data Sheet

ADV7850

VIDEO SPECIFICATIONS

Table 4.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

NONLINEAR SPECIFICATIONS¹

Differential Phase

Differential Gain

Luma Nonlinearity

NOISE SPECIFICATIONS¹

DP

DG

LNL

CVBS input (modulated five-step)

Measured at 27 MHz LLC

Luma ramp

0.5

0.6

0.9

Degrees

%

SNR Unweighted

59

60

dB

Luma flat field

Analog Front-End Crosstalk

LOCK TIME SPECIFICATIONS (SDP)²

Horizontal Lock Range

Vertical Lock Range

Subcarrier Lock Range

Color Lock-In Time

5

%

Hz

kHz

Lines

%

40

70

f_SC

0.8

60

Sync Depth Range

Color Burst Range

20

1

200

%

Vertical Lock Time

300

100

ms

Lines

Horizontal Lock Time

CHROMA SPECIFICATIONS (SDP)¹

Chroma Amplitude Error

Chroma Phase Error

Chroma Luma Intermodulation

0.9

0.3

0.6

%

Degrees

%

¹Guaranteed by lab characterization.

²Guaranteed by design.

Rev. 0 | Page 9 of 32

ADV7850

Data Sheet

TIMING CHARACTERISTICS

Data, SPI, and I²C Timing Characteristics

Table 5.

Parameter

Symbol Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Crystal Frequency

Crystal Frequency Stability

I²C PORT¹

27

MHz

ppm

±±0

400

See Figure 3

SCL Frequency

kHz

ns

μs

ns

μs

SCL Minimum Pulse Width High

SCL Minimum Pulse Width Low

Start Condition Hold Time

Start Condition Setup Time

SDA Setup Time

SCL and SDA Rise Time

SCL and SDA Fall Time

Stop Condition Setup Time

RESET FEATURE

t₁

t₂

t₃

t₄

t_±

t₆

t₇

t₈

600

1.3

600

100

1000

300

0.6

±

Reset Pulse Width

ms

HDMI AUDIO I²S PORT, MASTER MODE

HA_SCLK Mark-Space Ratio

LRCLK²Data Transition Time

See Figure 4

t_1±:t₁₆

t₁₇

4±:±±

2

% duty cycle

ns

End of valid data to negative

HA_SCLK edge

LRCLK²Data Transition Time

I2Sx³Data Transition Time

t₁₈

t₁₉

t₂₀

Negative HA_SCLK edge to start of

valid data

End of valid data to negative

HA_SCLK edge

Negative HA_SCLK edge to start of

valid data

2

ns

AUDIO CODEC MASTER CLOCK

AC_MCLK Frequency Range

AC_MCLK Frequency

f_MCLK

4.096

128 × f_S

24.±76 MHz

Hz

SPI READ AND WRITE OPERATIONS¹

See Figure ±, Figure 7, and Figure 8

SCLK Frequency

13.±

MHz

Master Mode

TTX_SCLK Falling Edge to

CS/TTX_MOSI Valid

t₂₁, t₂₂

3.0

4.1

ns

TTX_MISO Setup Time

TTX_MISO Hold Time

Slave Mode

t₂₃

t₂₄

1±.3

2.1

ns

CS Falling Edge to TTX_SCLK

Rising Edge

TTX_SCLK Falling Edge to CS

Rising Edge

t_2±, t₂₆

t₂₇, t₂₈

4.0

ns

TTX_MOSI Setup Time

TTX_MOSI Hold Time

TTX_SCLK Falling Edge to

CS/MOSI Valid

t₂₉

t₃₀

t₃₁, t₃₂

1.8

2.7

ns

7.3

1±.±

¹Guaranteed by design.

²LRCLK is a signal accessible via HA_AP±.

³I2Sx are signals accessible via Ball HA_AP1 to Ball HA_AP4.

Rev. 0 | Page 10 of 32

Data Sheet

ADV7850

TIMING DIAGRAMS

t₃

t₅

t₃

SDA

t₆

t₁

SCL

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₁₅

HA_SCLK

t₁₆

t₁₇

LRCLK

t₁₈

t₁₉

I2Sx

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

MSB

t₂₀

t₁₉

I2Sx

2

I S MODE

MSB – 1

t₂₀

t₁₉

I2Sx

RIGHT-JUSTIFIED

MODE

MSB

LSB

t₂₀

NOTES

2

1. THE SUFFIX x REFERS TO THE I S OUTPUT 0, 1, 2, 3.

2. LRCLK IS A SIGNAL ACCESSIBLE VIA HA_AP5 BALL.

3. I2Sx ARE SIGNALS ACCESSIBLE VIA HA_AP1 TO HA_AP4 BALL.

Figure 4. HDMI Audio I²S Timing

t₂₁

t₂₃

t₂₄

t₂₂

TTX_SCLK

TTX_MOSI

TTX_CS

TTX_MISO

Figure 5. SPI Master Mode Timing

Rev. 0 | Page 11 of 32

ADV7850

Data Sheet

TTX_CS

TTX_SCLK

TTX_MOSI

INSTRUCTION (0x0B)

24-BIT ADDRESS

DUMMY BYTE

23 22 21 ...

3

2

1

0

7

6

5

4

3

2

1

0

DATA OUT 1

DATA OUT 2

TTX_MISO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Figure 6. SPI Master Mode Overview

t₃₂

t₂₉

t₃₁

t₃₀

TTX_SCLK

TTX_MOSI

TTX_CS

TTX_MISO

Figure 7. SPI Slave Mode Timing

t₂₇

t₂₅

t₂₈

t₂₆

CS

CPCL CPHA

0

TTX_SCLK

0

1

0

1

TTX_SCLK

W/R

DEVICE ADDRESS

TTX_MOSI

TTX_MISO

7

6

5

4

3

2

1 0

DUMMY BYTE

DATA OUT 0

7

6

5

4

3

2

1

0

Figure 8. SPI Slave Mode Overview

Rev. 0 | Page 12 of 32

Data Sheet

ADV7850

ABSOLUTE MAXIMUM RATINGS

Table 6.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the ADV7850, the

user is advised to turn off unused sections of the part.

Parameter

Rating

2.2 V

AVDD to GND

VDD to GND

Due to PCB metal variation, and, therefore, variation in PCB

heat conductivity, the value of θ_JAmay differ for various PCBs.

PVDD to GND

TX_AVDD to GND

TX_PVDD to GND

SAVDD to GND

SDVDD to GND

CVDD to GND

DVDDIO to GND

TVDD to GND

AC_AVDD to GND

2.2 V

4.0 V

The most efficient measurement solution is obtained using the

package surface temperature to estimate the die temperature

because this eliminates the variance associated with the θ_JAvalue.

The maximum junction temperature (T_{J MAX}) of 125°C must not be

exceeded. The following equation calculates the junction tempera-

ture using the measured package surface temperature and applies

only when no heat sink is used on the device under test (DUT):

4.0 V

Maximum Difference Across All 1.8 V

Supplies

−0.3 V to +0.3 V

T_J= T_S+

(

Ψ _JT×W_TOTAL

)

Maximum Difference Across All 3.3 V

Supplies

Maximum Difference Between 3.3 V

Domain Supplies and 1.8 V Domain

Supplies

−0.3 V to +0.3 V

−0.3 V to +2.2 V

where:

T_Sis the package surface temperature (°C).

_JT= 0.7°C/W for the 425-ball CSP_BGA.

_TOTAL= (PVDD × I_PVDD) + (0.4 × TVDD × I_TVDD) +

Ψ

W

Digital Inputs Voltage to GND

Digital Outputs Voltage to GND

5 V Tolerant Digital Inputs to GND¹

Analog Inputs to GND

−0.3 V to DVDDIO + 0.3 V

5.5 V

−0.3V to AVDD + 0.3 V−0.3V

to AC_AVDD + 0.3 V

(CVDD × I_CVDD) + (AVDD × I_AVDD) + (VDD × I_VDD) +

(DVDDIO × I_DVDDIO) + (TX_AVDD × I_{TX_AVDD}) +

(TX_PVDD × I_{TX_PVDD}) + (SAVDD × I_SAVDD) + (SDVDD ×

I_SDVDD) + (TX_VDD33 × I_{TX_VDD33}) + (AC_AVDD × I_{AC_AVDD})

XTALN and XTALP to GND

Maximum Junction Temperature (T_{J MAX}

Storage Temperature Range

−0.3 V to PVDD + 0.3 V

125°C

−65°C to +150°C

260°C

where 0.4 reflects the 40% of TVDD power that is dissipated on

the part itself.

)

ESD CAUTION

Infrared Reflow Soldering (20 sec)

¹The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI7,

HS_IN2/TRI5, VS_IN1/TRI8, VS_IN2/TRI6, DDCA_SCL, DDCA_SDA, DDCB_SCL,

DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, VGA_SCL,

VGA_SDA, TX_DDC_SCL, TX_DDC_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V

and VGA_5V.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 13 of 32

ADV7850

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

GND

RXB_2+ RXB_1+ RXB_0+ RXB_C+ ARC_B

TVDD

RXC_2+ RXC_1+ RXC_0+ RXC_C+ ARC_C

RXC_2– RXC_1– RXC_0– RXC_C– HPA_C

GND

RXD_2+ RXD_1+ RXD_0+ RXD_C+ ARC_D

RXD_2– RXD_1– RXD_0– RXD_C– HPA_D

GND

A

B

A

B

ACMUXO ACMUXO

UT_R UT_L

ARC_A

HPA_A

GND

RXB_2– RXB_1– RXB_0– RXB_C– HPA_B

VDD_EEP

TVDD

GND

ACMUXIN ACMUXIN

_1R _1L

RXA_C+ RXA_C– CVDD

GND

TVDD

VREG

TVDD

GND

C

ROM

DDCA_

SCL

DDCA_

SDA

DDCB_

SCL

DDCB_

SDA

DDCC_

SCL

DDCC_

SDA

DDCD_

SCL

DDCD_

SDA

ACMUXIN ACMUXIN

VGA_SCL VGA_SDA TVDD AC_AVDD AC_AVDD AC_AVDD

RXA_0+ RXA_0–

RXA_1+ RXA_1–

RXA_2+ RXA_2–

CVDD

TVDD

RXD_5V VGA_5V

RXC_5V

D

_2R

_2L

ACMUXIN ACMUXIN

_3R _3L

GND

E

ACMUXIN ACMUXIN

_4R _4L

RXB_5V

PLL_LF

F

ACMUXIN ACMUXIN

_5R

TVDD

GND TEST1 CVDD CVDD CVDD CVDD CVDD CVDD CVDD

GND

AC_AVDD GND

G

H

G

H

_5L

VREF_AU

DIO

EP_MISO EP_MOSI SPDIF_IN RXA_5V

SHARED_

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

TEST2

GND

FILTA

EP_CS EP_SCK

RESET

AC_AVDD GND

ISET

AC_

FILTD

AC_

J

EDID

GND

DVDDIO DVDDIO

AC_AVDD AC_AVDD

DACOUT_ DACOUT_

R

K

L

HA_AP5 HA_SCLK

INT1

INT2

SDA

SCL

AC_AVDD AC_AVDD HPOUT_R HPOUT_L

L

HA_AP3/

HA_AP4

AC_AVDD GND

GND

XTALN

GND

XTALP

GND

M

N

M

N

INT3

AC_

LRCLK

HA_AP2 HA_AP1 AC_MCLK

PVDD

GND

PVDD

GND

HA_MCLK

OUT

HA_AP0

AC_SDI AC_SCLK

P

TTX_

SCLK

TTX_

MOSI

TTX_

TTX_CS

MISO

GND

REFN

AVDD

AVIN11

AVDD

AVIN9

REFP

AVDD

AVIN10

AVDD

AVIN8

AVIN7

R

DVDDIO DVDDIO

TX_AVDD TX_AVDD

GND

AVDD

AVIN13

AVDD

GND

AVDD

AVIN12

AVDD

AVOUT2

T

TX_DDC_

SCL

U

TX_DDC_

SDA

TX_2+

TX_1+

TX_0+

TX_C+

TX_2–

TX_1–

TX_0–

TX_C–

V

TX_HPD

GND

W

Y

W

Y

A7

A9

A3

A5

A6

A4

A10

A1

BA0

BA1

CAS

CS

CKE

WE

GND

VREF

CK

DQ6

DQ4

DQ7

DQ5

DQ0

DQ2

DQ3

DQ1

DQ8

DQ11

DQ10

DQ9

UDQS

UDQSN

DQ12

SDVDD

DQ14

SAVDD

GND

TRI1

TRI2

GND

AVOUT1 SYNC3

HS_IN1/ VS_IN1/

TRI7

HS_IN2/ VS_IN2/

TRI5

TX_

AVDD

GND

TRI3

AA

AB

AC

AA

AB

AC

TRI8

TRI6

TX_

PVDD

TX_

PLVDD

SDVDD

A11

A8

A2

RAS

CKN

SDVDD

LDQSN

LDQS

GND

SYNC1

AVIN3

GND

SYNC2

AVIN4

AVIN6

TRI4

GND

TX_

VDD33

TX_

RTERM

A0

DQ15

DQ13

GND

AVIN1

AVIN2

GND

AVIN5

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Figure 9. Pin Configuration

Rev. 0 | Page 14 of 32

Data Sheet

ADV7850

Table 7. Pin Function Descriptions

Pin No. Mnemonic

Description

A1

GND

Ground.

A2

GND

Ground.

A3

GND

Ground.

A4

A5

A6

A7

A8

A9

RXB_2+

RXB_1+

RXB_0+

RXB_C+

ARC_B

TVDD

Digital Input Channel 2 True of Port B in the HDMI Interface.

Digital Input Channel 1 True of Port B in the HDMI Interface.

Digital Input Channel 0 True of Port B in the HDMI Interface.

Digital Input Clock True of Port B in the HDMI interface.

Single-Ended Audio Return Channel of Port B in the HDMI Interface.

HDMI Termination Supply (3.3 V).

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

RXC_2+

RXC_1+

RXC_0+

RXC_C+

ARC_C

GND

RXD_2+

RXD_1+

RXD_0+

RXD_C+

ARC_D

GND

ARC_A

HPA_A

GND

Digital Input Channel 2 True of Port C in the HDMI Interface.

Digital Input Channel 1 True of Port C in the HDMI Interface.

Digital Input Channel 0 True of Port C in the HDMI Interface.

Digital Input Clock True of Port C in the HDMI Interface.

Single-Ended Audio Return Channel of Port C in the HDMI Interface.

Ground.

Digital Input Channel 2 True of Port D in the HDMI Interface.

Digital Input Channel 1 True of Port D in the HDMI Interface.

Digital Input Channel 0 True of Port D in the HDMI Interface.

Digital Input Clock True of Port D in the HDMI Interface.

Single-Ended Audio Return Channel of Port D in the HDMI Interface.

Ground.

Single-Ended Audio Return Channel of Port A in the HDMI Interface.

Hot Plug Assert for Port A.

Ground.

B2

B3

B4

B5

B6

B7

B8

B9

RXB_2−

RXB_1−

RXB_0−

RXB_C−

HPA_B

TVDD

Digital Input Channel 2 Complement of Port B in the HDMI Interface.

Digital Input Channel 1 Complement of Port B in the HDMI Interface.

Digital Input Channel 0 Complement of Port B in the HDMI Interface.

Digital Input Clock Complement of Port B in the HDMI Interface.

Hot Plug Assert for Port B.

HDMI Termination Supply (3.3 V).

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

C1

RXC_2−

RXC_1−

RXC_0−

RXC_C−

HPA_C

GND

RXD_2−

RXD_1−

RXD_0−

RXD_C−

HPA_D

GND

ACMUXOUT_R

ACMUXOUT_L

RXA_C+

RXA_C−

CVDD

Digital Input Channel 2 Complement of Port C in the HDMI Interface.

Digital Input Channel 1 Complement of Port C in the HDMI Interface.

Digital Input Channel 0 Complement of Port C in the HDMI Interface.

Digital Input Clock Complement of Port C in the HDMI Interface.

Hot Plug Assert for Port C.

Ground.

Digital Input Channel 2 Complement of Port D in the HDMI Interface.

Digital Input Channel 1 Complement of Port D in the HDMI Interface.

Digital Input Channel 0 Complement of Port D in the HDMI Interface.

Digital Input Clock Complement of Port D in the HDMI Interface.

Hot Plug Assert for Port D.

Ground.

Audio Codec Mux Output Right Channel.

Audio Codec Mux Output Left Channel.

Digital Input Clock True of Port A in the HDMI Interface.

Digital Input Clock Complement of Port A in the HDMI Interface.

HDMI Comparator Supply (1.8 V).

C2

C3

C4

GND

Ground.

C5

GND

Ground.

C6

GND

Ground.

Rev. 0 | Page 15 of 32

ADV7850

Data Sheet

Pin No. Mnemonic

Description

C7

GND

Ground.

C8

C9

VDD_EEPROM

TVDD

External EDID EEPROM Power Supply.

HDMI Termination Supply (3.3 V).

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

TVDD

GND

TVDD

GND

ACMUXIN_1R

ACMUXIN_1L

RXA_0+

RXA_0−

CVDD

HDMI Termination Supply (3.3 V).

Ground.

HDMI Termination Supply (3.3 V).

Ground.

Audio Codec Mux Input 1 Right Channel.

Audio Codec Mux Input 1 Left Channel.

Digital Input Channel 0 True of Port A in the HDMI Interface.

Digital Input Channel 0 Complement of Port A in the HDMI Interface.

HDMI Comparator Supply (1.8 V).

D2

D3

D4

D5

D6

D7

D8

D9

RXD_5V

VGA_5V

DDCA_SCL

DDCA_SDA

DDCB_SCL

DDCB_SDA

DDCC_SCL

DDCC_SDA

DDCD_SCL

DDCD_SDA

VREG

5 V Detect Pin for Port D in the HDMI Interface.

5 V Detect I/O for VGA Connector.

Serial Clock for DDC Bus of Port A. DDCA_SCL is 5 V tolerant.

Serial Data for DDC Bus of Port A. DDCA_SDA is 5 V tolerant.

Serial Clock Port for DDC Bus of Port B. DDCB_SCL is 5 V tolerant.

Serial Data Port for DDC Bus of Port B. DDCB_SDA is 5 V tolerant.

Serial Clock Port for DDC Bus of Port C. DDCC_SCL is 5 V tolerant.

Serial Data Port for DDC Bus of Port C. DDCC_SDA is 5 V tolerant.

Serial Clock Port for DDC Bus of Port D. DDCD_SCL is 5 V tolerant.

Serial Data Port for DDC Bus of Port D. DDCD_SDA is 5 V tolerant.

Voltage Regulator Output. Must be decoupled to GND via 1 µF capacitor.

Ground.

Serial Clock for VGA Interface. VGA_SCL is 5 V tolerant.

Serial Data for VGA Interface. VGA_SDA is 5 V tolerant.

HDMI Termination Supply (3.3 V).

Audio Block Supply (3.3 V).

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

E1

GND

VGA_SCL

VGA_SDA

TVDD

AC_AVDD

ACMUXIN_2R

ACMUXIN_2L

RXA_1+

RXA_1−

CVDD

Audio Block Supply (3.3 V).

Audio Codec Mux Input 2 Right Channel.

Audio Codec Mux Input 2 Left Channel.

Digital Input Channel 1 True of Port A in the HDMI Interface.

Digital Input Channel 1 Complement of Port A in the HDMI Interface.

HDMI Comparator Supply (1.8 V).

E2

E3

E4

RXC_5V

GND

ACMUXIN_3R

ACMUXIN_3L

RXA_2+

RXA_2−

CVDD

5 V Detect Pin for Port C in the HDMI Interface.

Ground.

Audio Codec Mux Input 3 Right Channel.

Audio Codec Mux Input 3 Left Channel.

Digital Input Channel 2 True of Port A in the HDMI Interface.

Digital Input Channel 2 Complement of Port A in the HDMI Interface.

HDMI Comparator Supply (1.8 V).

E20

E21

E22

E23

F1

F2

F3

F4

F20

RXB_5V

PLL_LF

5 V Detect Pin for Port B in the HDMI Interface.

Loop Filter Ball for Audio Codec PLL.

Rev. 0 | Page 16 of 32

Data Sheet

ADV7850

Pin No. Mnemonic

Description

F21

F22

F23

G1

GND

Ground.

ACMUXIN_4R

ACMUXIN_4L

TVDD

Audio Codec Mux Input 4 Right Channel.

Audio Codec Mux Input 4 Left Channel.

HDMI Termination Supply (3.3 V).

G2

TVDD

HDMI Termination Supply (3.3 V).

G3

TVDD

HDMI Termination Supply (3.3 V).

G4

TVDD

HDMI Termination Supply (3.3 V).

G7

GND

Ground.

G8

G9

TEST1

CVDD

GND

AC_AVDD

GND

ACMUXIN_5R

ACMUXIN_5L

EP_MISO

EP_MOSI

SPDIF_IN

RXA_5V

GND

Test Pin. Do not connect.

HDMI Comparator Supply (1.8 V).

Ground.

Audio Block Supply (3.3 V).

Ground.

Audio Codec Mux Input 5 Right Channel.

Audio Codec Mux Input 5 Left Channel.

External EDID EEPROM Interface.

G10

G11

G12

G13

G14

G15

G16

G17

G20

G21

G22

G23

H1

H2

H3

H4

H7

S/PDIF Digital Audio Input for Audio Return Channel (ARC).

5 V Detect Pin for Port A in the HDMI Interface.

Ground.

H8

GND

Ground.

H9

GND

Ground.

H10

H11

H12

H13

H14

H15

H16

H17

H20

H21

H22

H23

J1

GND

FILTA

VREF_AUDIO

EP_CS

EP_SCK

SHARED_EDID

RESET

GND

Ground.

Audio Codec ADC Filter Capacitor.

Audio Codec Block Reference Voltage Capacitor.

External EDID EEPROM Interface.

J2

J3

J4

J7

J8

J9

J10

J11

J12

J13

J14

External EDID EEPROM Interface.

EDID Selection Signal for HDMI Port D.

Chip Reset. Active low. Minimum low time guarantee reset is 5 ms.

Ground.

Rev. 0 | Page 17 of 32

ADV7850

Data Sheet

Pin No. Mnemonic

Description

J15

J16

J17

J20

J21

J22

J23

K1

GND

AC_AVDD

GND

ISET

FILTD

GND

Ground.

Audio Block Supply (3.3 V).

Ground.

Audio Codec ADC Current Settings.

Audio Codec DAC Filter Capacitor.

Ground.

K2

GND

Ground.

K3

K4

K7

K8

DVDDIO

VDD

I/O Supply (3.3 V).

Video Digital Supply (1.8 V).

Ground.

GND

K9

GND

Ground.

K10

K11

K12

K13

K14

K15

K16

K17

K20

K21

K22

K23

L1

GND

Ground.

AC_AVDD

Audio Block Supply (3.3 V).

AC_DACOUT_R Audio Codec DAC Output Right Channel.

AC_DACOUT_L Audio Codec DAC Output Left Channel

HA_AP5

HA_SCLK

INT1

SDA

VDD

GND

HDMI Audio Port Output.

HDMI Audio Port Serial Clock Output.

External Interrupt 1.

I²C Port Serial Data Input/Output.

Video Digital Supply (1.8 V).

Ground.

L2

L3

L4

L7

L8

L9

GND

Ground.

L10

L11

L12

L13

L14

L15

L16

L17

L20

L21

L22

L23

M1

M2

GND

AC_AVDD

HPOUT_R

HPOUT_L

HA_AP4

HA_AP3/INT3

Ground.

Audio Block Supply (3.3 V).

Headphone Output Right Channel.

Headphone Output Left Channel.

HDMI Audio Port Output.

HDMI Audio Port Output/External Interrupt 3. This pin can be configured as a TTL output interrupt pin for the

VDP SPI interface.

M3

M4

M7

M8

M9

INT2

SCL

VDD

GND

External Interrupt 2.

I²C Port Serial Clock Input.

Video Digital Supply (1.8 V).

Ground.

Rev. 0 | Page 18 of 32

Data Sheet

ADV7850

Pin No. Mnemonic

Description

M10

M11

M12

M13

M14

M15

M16

M17

M20

M21

M22

M23

N1

GND

Ground.

AC_AVDD

GND

Audio Block Supply (3.3 V).

Ground.

GND

Ground.

HA_AP2

HA_AP1

AC_MCLK

AC_LRCLK

VDD

HDMI Audio Port Output.

Audio Codec/DAC Clock Input.

Audio DAC Left/Right Clock Input.

Video Digital supply (1.8 V).

Ground.

N2

N3

N4

N7

N8

GND

N9

GND

Ground.

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

N22

N23

P1

GND

PVDD

XTALN

XTALP

HA_AP0

HA_MCLKOUT

AC_SDI

AC_SCLK

VDD

Ground.

DPLL Supply (1.8 V).

Crystal Output.

Crystal Input or External Clock Input.

HDMI Audio Port Output.

HDMI Audio Master Clock Output.

Audio DAC Data Input.

Audio DAC SCLK Input.

Video Digital Supply (1.8 V).

Ground.

P2

P3

P4

P7

P8

GND

P9

GND

Ground.

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

R1

GND

TTX_SCLK

TTX_MOSI

TTX_MISO

Ground.

Ground

VBI Data Interface.

R2

R3

Rev. 0 | Page 19 of 32

ADV7850

Data Sheet

Pin No. Mnemonic

Description

R4

TTX_CS

VDD

VBI Data Interface.

R7

Video Digital Supply (1.8 V).

R8

GND

Ground.

R9

GND

Ground.

R10

R11

R12

R13

R14

R15

R16

R17

R20

R21

R22

R23

T1

GND

Ground.

GND

Ground.

REFN

REFP

DVDDIO

GND

Negative Analog Video Reference Output.

Positive Analog Video Reference Output.

I/O Supply (3.3 V).

Ground.

T2

T3

T4

GND

Ground.

T7

T8

VDD

GND

Video Digital Supply (1.8 V).

Ground.

T9

GND

Ground.

T10

T11

T12

T13

T14

T15

T16

T17

T20

T21

T22

T23

U1

GND

AVDD

TX_AVDD

GND

Ground.

Video Analog Supply Voltage (1.8 V).

HDMI Tx Analog Supply (1.8 V).

Ground.

U2

U3

U4

U7

U8

U9

TX_DDC_SCL

VDD

TEST2

GND

AVIN13

AVIN12

AVIN11

Serial Clock for DDC Bus of HDMI Tx. TX_DDCA_SCL is 5 V tolerant.

Video Digital Supply (1.8 V).

Test Pin. Do not connect.

Ground.

U10

U11

U12

U13

U14

U15

U16

U17

U20

U21

U22

Ground.

Analog Video Mux Input Channel.

Rev. 0 | Page 20 of 32

Data Sheet

ADV7850

Pin No. Mnemonic

Description

U23

V1

V2

AVIN10

TX_2+

TX_2−

Analog Video Mux Input Channel.

Digital Output Channel 2 True of the HDMI Tx.

Digital Output Channel 2 Complement of the HDMI Tx.

Ground.

V3

GND

V4

V20

V21

TX_DDC_SDA

AVDD

Serial Data for DDC Bus of HDMI Tx. TX_DDCA_SDA is 5 V tolerant.

Video Analog Supply Voltage (1.8 V).

V22

V23

W1

W2

W3

AVDD

TX_1+

TX_1−

GND

Video Analog Supply Voltage (1.8 V).

Digital Output Channel 1 True of the HDMI Tx.

Digital Output Channel 1 Complement of the HDMI Tx.

Ground.

W4

TX_HPD

GND

Hot Plug Detect Signal of the HDMI Tx.

Ground.

W20

W21

W22

W23

Y1

AVOUT2

AVIN9

AVIN8

TX_0+

TX_0−

GND

Analog Video Mux Output 2.

Analog Video Mux Input Channel.

Digital Output Channel 0 True of the HDMI Tx.

Digital Output Channel 0 Complement of the HDMI Tx.

Ground.

Y2

Y3

Y4

GND

Ground.

Y5

A7

SDRAM Address Line.

Y6

A3

SDRAM Address Line.

Y7

A10

SDRAM Address Line.

Y8

Y9

BA0

CKE

SDRAM Block Address Signal.

SDRAM Clock Enable.

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

GND

DQ6

DQ7

DQ0

Ground.

SDRAM Data Line.

SDRAM Upper Data Strobe True Signal.

Memory Interface Supply.

DQ8

UDQS

SDVDD

SAVDD

TRI1

TRI2

GND

AVOUT1

SYNC3

AVIN7

TX_C+

TX_C−

TX_AVDD

GND

A9

A5

A1

BA1

WE

GND

DQ4

DQ5

SDRAM Interface Supply.

Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector.

Ground.

Analog Video Mux Output 1.

This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode.

Analog Video Mux Input Channel.

Digital Output Clock True of the HDMI Tx.

Digital Output Clock Complement of the HDMI Tx.

HDMI Tx Analog Supply (1.8 V).

Ground.

SDRAM Address Line.

SDRAM Block Address Signal.

SDRAM Write Enable Signal.

Ground.

SDRAM Data Line.

DQ2

SDRAM Data Line.

Rev. 0 | Page 21 of 32

ADV7850

Data Sheet

Pin No. Mnemonic

Description

AA14

AA15

AA16

AA17

AA18

DQ11

SDRAM Data Line.

UDQSN

SDVDD

GND

SDRAM Upper Data Strobe Complement Signal.

Memory Interface Supply.

Ground.

HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The

HS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the

SCART or D-connector.

HS_IN1/TRI7

AA19

VS_IN1/TRI8

VS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The VS

input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or

D-connector.

AA20

AA21

AA22

GND

TRI3

HS_IN2/TRI5

Ground.

Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector.

HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The

HS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the

SCART or D-connector.

AA23

VS_IN2/TRI6

HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The VS

input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or

D-connector.

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

GND

Ground.

HDMI Tx Digital Supply (1.8 V).

HDMI Tx PLL Digital Supply (1.8 V). It is important to ensure that this supply pin has a clean voltage input.

Memory Interface Supply.

SDRAM Address Line.

TX_PVDD

TX_PLVDD

SDVDD

A11

A6

A2

CAS

SDRAM Interface Column Address Select Command Signal. One of four command signals to the external

SDRAM.

AB9

RAS

SDRAM Interface Row Address Select Command Signal. One of four command signals to the external SDRAM.

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

VREF

Termination Reference Voltage for Memory Interface.

Memory Interface Supply.

SDRAM Lower Data Strobe Complement Signal.

SDRAM Data Line.

Ground.

This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode.

Analog Video Mux Input Channel.

Ground.

This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode.

Analog Video Mux Input Channel.

Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector.

Ground.

SDVDD

LDQSN

DQ3

DQ10

DQ12

DQ14

GND

SYNC1

AVIN3

GND

SYNC2

AVIN6

TRI4

GND

AC2

AC3

AC4

AC5

TX_RTERM

TX_VDD33

SDVDD

A8

This signal sets the internal termination resistance. A 500 Ωresistor between this ball and GND should be used.

HDMI Tx PLL Regulator Supply Input (3.3V). This pin is an internal voltage regulator input.

Memory Interface Supply.

SDRAM Address Line.

AC6

A4

SDRAM Address Line.

AC7

A0

SDRAM Address Line.

AC8

CS

SDRAM Interface Chip Select. SDRAM CS enables and disables the command decoder on the RAM. One of four

command signals to the external SDRAM.

AC9

CKN

CK

SDRAM Interface Differential Clock Compliment Output. All address and control output signals to the RAM

should be sampled on the positive edge of CK and on the negative edge of CKN.

SDRAM Interface Differential Clock Right Output. All address and control output signals to the RAM should be

sampled on the positive edge of CK and on the negative edge of CKN.

AC10

Rev. 0 | Page 22 of 32

Data Sheet

ADV7850

Pin No. Mnemonic

Description

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

SDVDD

LDQS

DQ1

Memory Interface Supply.

SDRAM Lower Data Strobe True Signal.

SDRAM Data Line.

DQ9

DQ15

DQ13

GND

AVIN1

AVIN2

GND

AVIN4

AVIN5

GND

SDRAM Data Line.

Ground.

Analog Video Mux Input Channel.

Ground.

Analog Video Mux Input Channel.

Ground.

Rev. 0 | Page 23 of 32

ADV7850

Data Sheet

POWER SUPPLY SEQUENCING

In this case, care must be taken to ensure that a lower rated supply

does not go above a higher rated supply level as the supplies are

being established.

POWER-UP SEQUENCE

The recommended power-up sequence of the ADV7850 is as

follows:

POWER-DOWN SEQUENCE

1. 3.3 V supplies

2. 1.8 V supplies

The ADV7850 supplies can be powered down simultaneously as

long as the 3.3 V supply domain does not go below the 1.8 V

supply domain.

3.3V

3.3V SUPPLIES

POWER SUPPLY REQUIREMENTS

Table 8 shows the current rating recommendations for power

supply design. These values should be used when designing a

power supply section to ensure that an adequate current can be

supplied to the ADV7850.

1.8V SUPPLIES

1.8V

Table 8. Current Rating Recommendation for Power Supply

Design

Parameter

Rating

600 mA

450 mA

400 mA

350 mA

150 mA

100 mA

60 mA

50 mA

20 mA

I_DVDD

I_CVDD

I_TVDD

I_AVDD

I_{AC_AVDD}

I_{TX_PVDD}

I_PVDD

I_{TX_VDD33}

I_SDVDD

I_{TX_AVDD}

I_DVDDIO

I_SAVDD

3.3V SUPPLIES

POWER-UP

1.8V SUPPLIES

POWER-UP

Figure 10. Recommended Power-Up Sequence

Notes

RESET should be held low while the supplies are being

powered up.



3.3 V supplies should be powered up first.

1.8 V supplies should be powered up last.

The ADV7850 can alternatively be powered up by asserting all

supplies simultaneously.

Rev. 0 | Page 24 of 32

Data Sheet

ADV7850

FUNCTIONAL OVERVIEW

•

Internal E-EDID RAM

Hot plug assert output pin for each HDMI port

HDMI RECEIVER

The ADV7850 front end incorporates a 4:1 multiplexed HDMI

receiver with Xpressview fast switching technology and support

for HDMI features including ARC and 3D TV. Building on the

feature set of Analog Devices existing HDMI devices, the

ADV7850 also offers support for all HDTV formats up to 3D

1080p at 60 Hz and 2160p at 24 Hz. Xpressview fast switching

technology, using the Analog Devices hardware-based HDCP

engine that minimizes software overhead, allows switching

between any two input ports in less than 1 second.

ANALOG FRONT END

The ADV7850 analog front end comprises four 170 MHz, 12-bit

ADCs that digitize the analog video signal before applying it

to the standard definition processor (SDP) or component

processor (CP).

The front end also includes a 13-channel input mux that enables

multiple video signals to be applied to the ADV7850 without

the requirement of an external mux.

With the inclusion of HDCP 1.4, the ADV7850 can receive

encrypted video content. The HDMI interface of the ADV7850

allows for authentication of a video receiver, decryption of encoded

data at the receiver, and renewal of that authentication during

transmission, as specified by the HDCP 1.4 protocol. Repeater

support is also offered by the ADV7850.

Current and voltage clamp control loops ensure that any dc

offsets are set properly for the video signal. The clamps are

positioned in front of each ADC to ensure that the video signal

remains within the range of the converter.

The ADCs are configured to run up to 4× oversampling mode

when decoding composite, S-Video, or SCART inputs. For

component 525i, 625i, 525p, and 625p sources, 4× oversampling is

performed. Higher frequency video standards can be 2× or 1×

oversampled. Oversampling the video signals reduces the cost

and complexity of external antialiasing filters with the benefit of

an increased signal-to-noise ratio (SNR).

The ADV7850 supports the audio return channel feature. There

is a dedicated S/PDIF input on which audio can be received for

retransmission on the HDMI input. Wide ranges of 3D video

formats are supported, including frame packing up to 3D 1080p

at 60 Hz and 2160p at 24 Hz.

The HDMI receiver incorporates active equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. It is capable of equaliz-

ing for cable lengths up to 30 meters to achieve robust receiver

performance at even the highest HDMI data rates.

Optional internal antialiasing filters with programmable

bandwidth are positioned in front of each ADC. These filters

can be used to band-limit video signals, removing spurious out-

of-band noise.

The ADV7850 can support the simultaneous processing of

CVBS and RGB standard definition signals to enable SCART

compatibility and overlay functionality. A combination of

CVBS and RGB inputs can be mixed with the output under the

control of I²C registers.

The HDMI receiver offers advanced audio functionality. It sup-

ports multichannel I²S audio for up to eight channels. It also

supports a six-DSD channel interface with each channel carry-

ing an oversampled 1-bit representation of the audio signal as

delivered on SACD. The ADV7850 can also receive HBR audio

packet streams and outputs them through the HBR interface in

an S/PDIF format conforming to the IEC 60958 standard.

Analog front-end features include:

•

Four 170 MHz, 12-bit NSV ADCs that enable 10-bit (SD)/

12-bit (CP) video decoding

The receiver contains an audio mute controller that can detect a

variety of conditions that may result in audible extraneous noise

in the audio output. On detection of these conditions, the audio

signal can be muted to prevent audio clicks or pops.

13-channel analog input mux that enables multiple source

connections without the requirement of an external mux

Four current and voltage clamp control loops that ensure

any dc offsets are set properly for the video signal

SCART functionality and SD RGB overlay on CVBS

controlled by fastblank input

SCART source switching detection through the TRI1 to TRI8

inputs

Four programmable antialiasing filters

HDMI receiver features include:

•

4:1 multiplexed HDMI receiver

HDMI, ARC, and 3D format support, DVI 1.0

297 MHz HDMI receiver

Integrated equalizer

High-bandwidth Digital Content Protection (HDCP 1.4)

on background ports

•

Internal HDCP keys

36-/30-bit Deep Color support

PCM, HBR, DSD, and DST audio packet support

Repeater support

Rev. 0 | Page 25 of 32

ADV7850

Data Sheet

•

Advanced TBC with frame synchronization, which ensures

nominal clock and data for nonstandard input

Color controls that include hue, brightness, saturation,

and contrast

STANDARD DEFINITION PROCESSOR

The SDP is capable of decoding a large selection of baseband

video signals in composite, S-Video, and 525i/625i component

formats. The video standards supported by the SDP include

PAL, PAL 60, PAL M, PAL N, PAL NC, NTSC M/J, NTSC 4.43,

and SECAM. The ADV7850 can automatically detect the video

standard and process it accordingly.

COMPONENT PROCESSOR

The CP section of the ADV7850 is capable of decoding and

digitizing a wide range of component video formats in any color

space. Component video standards supported by the CP include

525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to

UXGA at 60 Hz, and many other standards.

The SDP has a 3D temporal comb filter and a five-line adaptive

2D comb filter that gives superior chrominance and luminance

separation when decoding a composite video signal. This highly

adaptive filter automatically adjusts its processing mode according

to the video standard and signal quality with no user intervention

required. The SDP has an IF filter block that compensates for

attenuation in the high frequency chroma spectrum due to a tuner

SAW filter. The SDP has specific luminance and chrominance

parameter controls for brightness, contrast, saturation, and hue.

The any-to-any, 3 × 3 CSC matrix is placed between the analog

front end and the CP section. This enables YPbPr-to-RGB and

RGB-to-YCbCr conversions. Many other standards of color

space can be implemented using the color space converter.

The CP section contains circuitry to enable the detection of

Macrovision encoded YPbPr signals for 525i, 625i, 525p, and

625p. It is designed to be fully robust when decoding these

types of signals.

The ADV7850 implements a patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7850 to track and decode poor quality video sources (such

as VCRs) and noisy sources (such as tuner outputs, VCR players,

and camcorders). Frame TBC ensures stable clock synchroniza-

tion between the decoder and the downstream devices.

CP features include:

•

525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other

HDTV formats are supported

Supports 720p at 24 Hz/25 Hz formats

Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation

•

The SDP also contains both a luma transient improvement (LTI)

block and a chroma transient improvement (CTI) block. These

increase the edge rate on the luma and chroma transitions,

resulting in a sharper video image.

•

Support for analog component YPbPr and RGB video

formats with embedded synchronization, composite

synchronization, or separate HS and VS

Any-to-any, 3 × 3 CSC matrix that supports YCbCr-to-

RGB and RGB-to-YCbCr, fully programmable or

preprogrammable configurations

Synchronization source polarity detector (SSPD) that

determines the source and polarity of the synchronization

signals that accompany the input video

Macrovision copy protection detection on component

formats (525i, 625i, 525p, and 625p)

Free-run output mode that provides stable timing when no

video input is present or video lock is lost

Arbitrary pixel sampling support for nonstandard video

sources

170 MHz conversion rate, which supports RGB input

resolutions up to 1600 × 1200 at 60 Hz

Automatic or manual clamp-and-gain controls for

graphics modes

32-phase ADC DLL that allows optimum pixel clock

sampling

Automatic detection of synchronization source and

polarity by SSPD block

Standard identification enabled by STDI block

RGB that can be color space converted to YCbCr and

decimated to a 4:2:2 format for video-centric back-end IC

interfacing

The SDP has a Macrovision® detection circuit that allows Type I,

Type II, and Type III Macrovision protection levels. The

decoder is also fully robust to all Macrovision signal inputs.

SDP features include:

•

Advanced adaptive 3D comb (using the external DDR2

memory)

•

Adaptive 2D five-line comb filters for NTSC and PAL that

give superior chrominance and luminance separation for

composite video

•

Full automatic detection and autoswitching of all

worldwide standards (PAL, NTSC, and SECAM)

Automatic gain control with white peak mode that

ensures the video is always processed without loss of

the video processing range

•

Proprietary architecture for locking to weak, noisy, and

unstable sources from VCRs and tuners

IF filter block that compensates for high frequency luma

attenuation due to tuner SAW filter

•

LTI and CTI

Vertical and horizontal programmable luma peaking filters

4× oversampling (54 MHz) for CVBS, and S-Video modes

Free-run output mode that provides stable timing when no

video input is present or video lock is lost

Internal color bar test pattern

•

Rev. 0 | Page 26 of 32

Data Sheet

ADV7850

Double Data Rate 2 (DDR2)

VBI DATA PROCESSOR (VDP)

The ADV7850 can use DDR2 external memory to simultane-

ously provide 3D comb and frame TBC operation.

VBI extraction of Teletext, CC, WSS, CGMS, PDC, UTC, VPS,

GEMSTAR, and VITC data is performed by the VBI data

processor of the ADV7850 at interlaced, progressive, and high

definition scanning rates. The data extracted can be read back

over the SPI interface.

It requires a minimum memory of 128 Mb with a speed grade of

200 MHz at CAS latency (CL) 3.

The recommended DDR2 memory compatible with the

ADV7850 include the MT47H32M16HR-25E:G from Micron

Technology, Inc.

TMDS OUTPUT

The ADV7850 incorporates a 297 MHz TMDS output. This

interface is designed to connect to any internal IC with an HDMI

or DVI input port.

OTHER FEATURES

The ADV7850 has one I²C host port interface.

The digital video interface contains an HDMI and a DVI 1.0-

compatible transmitter, and supports all HDTV formats up to 3D

1080p at 60 Hz and 2160p at 24 Hz. The ADV7850 transmitter

fully supports programmable AVI InfoFrames. With the inclusion

o f H D C P, t h e ADV7850 transmitter allows the secure transmission

of protected content as specified by the HDCP protocol. The

ADV7850 transmitter also fully supports EDID read operations.

The ADV7850 has two programmable interrupt request output

pins, INT1 and INT2. It also features a number of low power

modes and a full power-down mode. The ADV7850 contains an

internal power regulator to accommodate power-off mode. In

this mode, the ADV7850 is powered from the 5 V supply of the

HDMI/VGA cable connected to a source device or devices. In

this mode, EDID can be read over an HDMI/VGA DDC link.

The ADV7850 TMDS output supports the audio mode received

from the HDMI receiver, that is, PCM, HBR, DSD, and DST.

The ADV7850 is provided in a 19 mm × 19 mm, RoHS-compliant

CSP_BGA package and is specified over the −20°C to +70°C

temperature range.

EXTERNAL MEMORY REQUIREMENTS

The ADV7850 requires an external SDRAM for 3D comb and

frame TBC. The ADV7850 supports DDR2 memories.

For more detailed product information about the ADV7850,

contact your local Analog Devices sales office.

Rev. 0 | Page 27 of 32

ADV7850

Data Sheet

AUDIO OVERVIEW

AUDIO_L/R_1

AUDIO_L/R_2

AUDIO_L/R_3

AUDIO_L/R_4

AUDIO_L/R_5

5-CHANNEL

ADV7850

2

I S

EXTERNAL

INTERNAL

TO HDMI

STEREO

ADC

DAC

IMPEDANCE

Tx BLOCK

INPUT

MATRIX

AUDIO

PLL

22kΩ

10.1kΩ

2.8 V rms INPUT

MUX OUTPUT

AC_MCLK

ADC

AUDIO_L/R_OUT

DAC_L/R_OUT

AC_SCLK

AC_LRCLK

AC_SDI

HP_L/R_OUT

Figure 11. Audio Block

The ADV7850 supports an audio codec comprising a stereo

ADC and a stereo DAC. A 5:1 stereo mux is placed in front of

the ADC input. The DAC output is available as a line level

output and is passed through an internal headphone amplifier.

The integrated headphone amplifier eliminates the need for an

external amplifier when driving headphones.

Figure 12. High Level Overview of Analog Audio Input/Output Configuration

ANALOG AUDIO MUX FUNCTIONALITY

A factory calibration is applied during final test to ensure that

the gain through the mux circuit remains within 5%. Calibra-

tion is also applied to the ADC reference current to ensure that

the code swing from the ADC remains within 5% across the

part for a given input. External impedances with a tolerance of

1% are required.

The ADV7850 has five stereo analog audio inputs and one

stereo analog output. Any one of the stereo inputs can be

connected to the stereo ADC, and any one of the inputs can be

connected to the stereo output. In the case of the analog output,

the ADV7850 also supports mono in-stereo output. The I/O

connectivity is shown in Table 9.

AUDIO CODEC FUNCTIONALITY

The ADV7850 audio codec requires an external MCLK.

For MCLK with a frequency of 6.144 MHz, 12.288 MHz,

or 24.576 MHz, the ADC and DAC sample rate is 48 kHz.

If the MCLK is reduced to 5.6448 MHz, 11.2896 MHz, or

22.5792 MHz, the ADC and DAC sample rate reduces to

44.1 kHz.

Table 9. Analog Audio Inputs to ADC and Analog Audio

Outputs Connection Capability

Mux Output

ADC Input

Mux Input

Left

Right

OK

Left

OK

Right

Left

OK

N/A

OK

1

Right

Left

N/A

OK

The bandwidth of the digital filter is sufficient so that 20 kHz

pass band is maintained in this mode. The 32 kHz sampling is

also possible but with pass-band reduction.

The system controller must set an I²C control to select the

correct mode of operation for the internal PLL so that it always

generates an internal MCLK of 6.144 MHz. A fixed oversample

rate of 128× is implemented.

N/A

OK

2

3

4

5

Right

Left

N/A

OK

N/A

OK

Right

Left

N/A

OK

N/A

OK

Right

Left

N/A

OK

N/A

OK

Right

N/A

The word depth of both the ADC and DAC is 24 bits. The ADC

and DAC have independent LRCLK and SCLK signals but use a

common MCLK.

The ADC supports I²S mode, providing LRCLK, SCLK, and I²S

signals. These signals are sent to the HDMI Tx and embedded

into the HDMI stream.

The DAC supports I²S mode. The LRCLK, SCLK, and data

signals must be provided by the back-end SOC and must be

frequency locked with the MCLK but can be phase independ-

ent. The output level is 1 V rms full scale.

The ADV7850 is designed to use a combination of internal and

external resistances. Measured from the system audio input

connector, the total nominal input impedance is 32.1 kΩ. All

analog system audio inputs are designed to support 2.8 V rms

audio input. Figure 12 shows a high level overview of the

implementation.

The input level at the analog audio input pins on the ADV7850

is 880 mV rms. However, the ADV7850 incorporates a gain

stage to restore the mux output level to 1.0 V rms. An external

line driver is required to restore the audio output signals to the

SCART specification of 2.8 V rms. Analog audio mux output

signals are inverted with respect to mux input signals.

There is one stereo headphone amplifier output capable of

driving 32 Ω loads at 1 V rms. The headphone output

incorporates circuitry to suppress pop/click sounds during

power-on/off cycle.

Rev. 0 | Page 28 of 32

Data Sheet

ADV7850

REGISTER MAP ARCHITECTURE

The registers of the ADV7850 are controlled via a 2-wire serial

(I²C-compatible) interface. The ADV7850 has 17 maps. The IO

map and HDMI Tx map has a static I²C addresses. All other

map addresses must be programmed. This ensures that no

address clashes on the system. Figure 13 shows the register map

architecture.

Table 5.

Register Map Name

Default Address

0x40

0xB8

0x00

Programmable Address

Not programmable

Programmable

Location at Which Address Can Be Programmed

Not applicable

IO Map

HDMI Tx Map

VDP Map

IO map, Register 0xFE

IO map, Register 0xFD

IO map, Register 0xFB

IO map, Register 0xFA

IO map, Register 0xF9

IO map, Register 0xF8

IO map, Register 0xF5

IO map, Register 0xF2

IO map, Register 0xF1

IO map, Register 0xF0

IO map, Register 0xEF

IO map, Register 0xEC

IO map, Register 0xEB

IO map, Register 0xE7

IO map, Register 0xE3

CP Map

HDMI Rx Map

HDMI Rx EDID Map

KSV Map

AFE Map

InfoFrame Map

SDP_IO Map

SDP Map

HDMI Tx EDID Map

Tx UDP Map

VFE

Memory Map

Audio Codec Map

Tx TEST Map

0x00

IO

MAP

HDMI Tx

MAP

VDP

MAP

CP

MAP

HDMI Rx

MAP

HDMI Rx EDID

MAP

KSV

MAP

SLAVE

ADDRESS:

0x40

SLAVE

ADDRESS:

0xB8

SLAVE

ADDRESS:

PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE

SCL

SDA

SLAVE

ADDRESS:

PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE

AFE

MAP

INFOFRAME

MAP

SDP_IO

MAP

SDP

MAP

HDMI Tx EDID

MAP

SLAVE

ADDRESS:

PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE

Tx UDP

MAP

VFE

MAP

MEMORY

MAP

AUDIO CODEC

MAP

Tx TEST

MAP

Figure 13. Register Map Architecture

Rev. 0 | Page 29 of 32

ADV7850

Data Sheet

OUTLINE DIMENSIONS

19.20

A1 BALL

CORNER

19.00 SQ

18.80

22 20 18 16 14 12 10

23 21 19 17 15 13 11

8

6

4

2

A1 BALL

CORNER

9

7

5

3

1

A

C

E

G

J

B

D

F

H

K

M

P

T

17.60

BSC SQ

L

N

R

U

W

0.80

BSC

V

Y

AA

AB

AC

TOP VIEW

DETAIL A

BOTTOM VIEW

DETAIL A

1.50

1.36

1.21

1.11

1.01

0.91

0.65

NOM

0.35 NOM

0.30 MIN

0.35

NOM

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2.

Figure 14. 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-425-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Notes Temperature Range

Package Description

Package Option

2, 3

ADV7850KBCZ-5

EVAL-ADV7850EBZ

−20°C to +70°C

425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Low Cost, Blackfin-Based Evaluation Board with ADV7850

(with HDCP keys)

ADV7850 Evaluation Board with Complete Audio Support

(with HDCP Keys)

BC-425-1

3

EVAL-ADV7850EB1Z

¹Z = RoHS Compliant Part.

²Speed grade: 5 = 170 MHz.

³This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to

purchase any components with internal HDCP keys.

Rev. 0 | Page 30 of 32

Data Sheet

NOTES

ADV7850

Rev. 0 | Page 31 of 32

ADV7850

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D07758-0-5/12(0)

Rev. 0 | Page 32 of 32


型号：	ADV7850
厂家：	ADI
描述：	Complete AV Front End 完整的AV前端
文件：	总32页 (文件大小：505K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7850 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E