ADV7844_12_技术文档

Quad HDMI Fast Switching Receiver with 12-Bit, 170 MHz

Video and Graphics Digitizer and 3D Comb Filter Decoder

Data Sheet

ADV7844

Vertical peaking and horizontal peaking filters

Robust synchronization extraction for poor video source

Advanced VBI data slicer

FEATURES

Quad HDMI® 1.4 fast switching receiver

HDMI support

Audio return channel (ARC)

3D TV support

Content type bits

CEC 1.4-compatible

General

Highly flexible 36-bit pixel output interface

Internal EDID RAM for HDMI and graphics

Dual STDI (standard identification) function support

Any-to-any, 3 × 3 color space conversion (CSC) matrix

2 programmable interrupt request output pins

Simultaneous analog processing and HDMI monitoring

Extended colorimetry

HDMI 225 MHz receiver

Xpressview fast switching of HDMI ports

2 ARC interfaces for ARC support

SPDIF interface for ARC support

3D video format support, including frame packing 1080p

24 Hz, 720p 50 Hz, 720p 60 Hz

Full colorimetry support including sYCC601, Adobe RGB,

Adobe YCC 601

36-/30-bit Deep Color and 24-bit color support

HDCP 1.4 support with internal HDCP keys

5 V detect and hot plug assert for each HDMI port

Adaptive HDMI equalizer

APPLICATIONS

Advanced TVs

PDP HDTVs

LCD TVs (HDTV ready)

LCD/DLP® rear projection HDTVs

LCoS™ HDTVs

AVR video receivers

HDTV STBs with PVR

Projectors

Integrated CEC controller

HDMI repeater support

FUNCTIONAL BLOCK DIAGRAM

SDRAM

HDMI audio support including HBR and DSD

Advanced audio mute feature

Flexible digital audio output interfaces

Supports up to 5 S/PDIF outputs

Supports up to 4 I²S outputs

SCART

CVBS

48

CVBS

SCART RGB

+ CVBS

ADC

HS/VS

SDP

CVBS

3D YC

S-VIDEO

SCART

SCART G

SCART B

SCART R

CVBS

FIELD/DE

CLK

HS/VS

YC

Video and graphics digitizer

Four 170 MHz, 12-bit ADCs

DATA

FIELD/DE

SD/PS

YPbPr

CLK

HS/VS

CP

12-channel analog input mux

Y/G

Pb/B

Pb/R

YPbPr

525p/625p

720p/1080i

1080p/

UXGA

RGB

FIELD/DE

36-BIT

YCbCr/RGB

HD YpbPr

525i-/625i-component analog input

525p-/625p-component progressive scan support

720p-/1080i-/1080p-component HDTV support

Low refresh rates (24/25/30 Hz) support for 720p/1080p

Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA)

SCART fast blank support

GRAPHICS

RGB

CLK

DATA

36

HDMI 1

HDMI 2

HDMI 3

HDMI 4

TMDS

2

I S

DDC

4

AUDIO

OUTPUT

5

S/PDIF

DSD

DEEP

COLOR

HDMI Rx

TMDS

DDC

3D video decoder

TMDS

DDC

HBR

MCLK

SCLK

MCLK

SCLK

NTSC/PAL/SECAM color standards support

NTSC/PAL 2D/3D motion detecting comb filter

Advanced time-base correction (TBC) with frame

synchronization

TMDS

DDC

FAST

SWITCH

S/PDIF

ARC_1±

ARC_2±

HDCP

KEYS

ARC

TO AUDIO

PROCESSOR

ADV7844

Interlaced-to-progressive conversion for 525i and 625i

IF compensation filters

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7844

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Power-Up Sequence ................................................................... 23

Power-Down Sequence.............................................................. 23

Functional Overview...................................................................... 24

HDMI Receiver........................................................................... 24

Analog Front End....................................................................... 24

Standard Definition Processor ................................................. 25

Component Processor ............................................................... 25

Other Features ............................................................................ 26

External Memory Requirements.................................................. 27

Single Data Rate (SDR).............................................................. 27

Double Data Rate (DDR) .......................................................... 27

Pixel Input/Output Formatting .................................................... 28

Pixel Data Output Modes Features .......................................... 28

Register Map Architecture ............................................................ 29

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications..................................................................................... 5

Electrical Characteristics............................................................. 5

Power Specifications .................................................................... 6

Analog Specifications................................................................... 8

Video Specifications..................................................................... 9

Timing Characteristics .............................................................. 10

Timing Diagrams........................................................................ 11

Absolute Maximum Ratings.......................................................... 12

Package Thermal Performance................................................. 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Power Supply Sequencing.............................................................. 23

REVISION HISTORY

4/12—Rev. B: Initial Version

Rev. B | Page 2 of 32

Data Sheet

ADV7844

GENERAL DESCRIPTION

The ADV7844 is a high quality, single-chip, 4:1 multiplexed

HDMI receiver and graphics digitizer with an integrated

multiformat video decoder.

The multiformat 3D comb filter decoder supports the conversion

of PAL, NTSC, and SECAM standards in the form of a composite

or an S-Video input signal into a digital ITU-R BT.656 format.

SCART and overlay functionality are enabled by the ability of the

ADV7844 to process CVBS and standard definition RGB signals

simultaneously.

The ADV7844 incorporates a quad input HDMI-compatible

receiver that supports all HDTV formats up to 1080p and

display resolutions up to UXGA (1600 × 1200 at 60 Hz).

The ADV7844 contains one main component processor (CP),

which processes YPbPr and RGB component formats, including

RGB graphics. The CP also processes the video signals from the

HDMI receiver. The ADV7844 can operate in quad HDMI and

analog input mode, thus allowing for fast switching between the

ADCs and HDMI.

The ADV7844 incorporates Xpressview™ fast switching on all

input HDMI ports. Using the Analog Devices, Inc., hardware-

based HDCP engine that minimizes software overhead,

Xpressview™ technology allows fast switching between any

HDMI input ports in less than 1 second.

The ADV7844 supports all mandatory HDMI 3D TV formats in

addition to all HDTV formats up to 1080p 36-bit Deep Color.

The ADV7844 supports the decoding of a component RGB/

YPbPr video signal into a digital YCbCr or RGB pixel output

stream. The support for component video includes 525i, 625i,

525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as

many other SMPTE and HD standards.

The ADV7844 also integrates an HDMI CEC controller that

supports the capability discovery and control (CDC) feature.

The ADV7844 offers a flexible audio output port for the audio

data decoded from the HDMI stream. HDMI audio formats,

including super audio CD (SACD) via DSD and HBR are

supported. The ADV7844 also features the audio return

channel (ARC) feature. ARC simplifies cabling by combining

upstream audio capability in a conventional HDMI cable.

The ADV7844 supports graphics digitization. The ADV7844 is

capable of digitizing RGB graphics signals from VGA to UXGA

rates and converting them into a digital RGB or YCbCr pixel

output stream. Internal EDID is available for one graphic port.

Fabricated in an advanced CMOS process, the ADV7844 is

provided in a 19 mm × 19 mm, 425-ball, CSP BGA, surface-

mount, RoHS-compliant package, and is specified over the 0°C

to 70°C temperature range.

Each HDMI port has dedicated 5 V detect and hot plug assert

pins. The HDMI receiver also includes an integrated equalizer

that ensures robust operation of the interface with cable lengths

up to 30 meters. The HDMI receiver has advanced audio

functionality, such as a mute controller, that prevents audible

extraneous noise in the audio output.

Rev. B | Page 3 of 32

ADV7844

Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

0 2 0 0 - 8 5 0 8

R E T T A M R O F U P T U T O O

A U D I

R E T T A R M O F U P T U T O O D I E V

X

M U

X U + M

D E C O D I E H D M C K O + B L

N G C T H I I W S T A F S

Figure 2. Detailed Functional Block Diagram

Rev. B | Page 4 of 32

Data Sheet

ADV7844

SPECIFICATIONS

AVDD = 1.8 V 5ꢀ, CVDD = 1.8 V 5ꢀ, DVDD = 1.8 V 5ꢀ, PVDD = 1.8 V 5ꢀ, DVDDIO = 3.3 V 5ꢀ, TVDD = 3.3 V 5ꢀ,

VDD_SDRAM = 3.2 V to 3.4 V (SDR), VDD_SDRAM = 2.35 V to 2.65 V (DDR). T_MINto T_MAX= 0°C to 70°C, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each ADC)

Integral Nonlinearity

N

INL

12

Bits

LSB

27 MHz (at a 12-bit level)

54 MHz (at a 12-bit level)

74.25 MHz (at a 12-bit level)

108 MHz (at a 11-bit level)

170 MHz (at a 9-bit level)

27 MHz (at a 12-bit level)

54 MHz (at a 12-bit level)

75 MHz (at a 12-bit level)

108 MHz (at a 11-bit level)

170 MHz (at a 9-bit level)

−3.0 to +8.0

−4.0 to +7.0

−3.5 to +8.0

−0.7 to +1.5

−0.7 to +0.8

−0.6 to +0.5

Differential Nonlinearity

DNL

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

V_IH

V_IL

V_IH

V_IL

I_IN

XTALN and XTALP pins

Other digital inputs

Reset pin

EP_MISO pin

SPDIF_IN pin

TEST4 pin

TEST6 pin

1.2

2

V

μA

pF

0.4

0.8

60

10

Input Current

Other digital inputs

Input Capacitance

DIGITAL INPUTS (5 V TOLERANT) ¹

Input High Voltage

Input Low Voltage

Input Current

C_IN

V_IH

V_IL

I_IN

2.6

V

μA

0.8

+82

−82

2.4

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

High Impedance Leakage Current

Output Capacitance

V_OH

V_OL

I_LEAK

C_OUT

V

μA

pF

0.4

20

10

¹The following pins are 5 V tolerant: HS_IN1/TRI5, HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, RXA_5V, RXB_5V, RXC_5V, RXD_5V, DDCA_SCL, DDCA_SDA, DDCB_SCL,

DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, and DDCD_SDA.

Rev. B | Page 5 of 32

ADV7844

Data Sheet

POWER SPECIFICATIONS

Table 2.

Parameter

Symbol

Min Typ Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

Digital Core Power Supply

Digital I/O Power Supply

SDRAM Power Supply

VDD

DVDDIO

VDD_SDRAM

1.75 1.8

3.14 3.3

1.85

3.46

V

3.2

3.3

3.4

V

SDR memory

DDR memory

2.35 2.5

1.71 1.8

3.14 3.3

1.71 1.8

2.65

1.89

3.46

1.89

PLL Power Supply

Analog Power Supply

Terminator Power Supply

Comparator Power Supply

CURRENT CONSUMPTION^{1, 2, 3}

PVDD

AVDD

TVDD

CVDD

Digital Core Supply Current I_VDD

155 220

149 205

365 445

mA

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with all background ports enabled

148 210

298 385

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color with all background ports

enabled

440 475

480 525

mA

SD core 576i processing in simultaneous mode with all

background ports enabled

SCART processing in simultaneous mode with all

background ports enabled

Digital I/O Supply Current

I_DVDDIO

55

40

37

120

122

120

mA

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with all background ports enabled

15

14

175

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color with all background ports

enabled

9

11

10

mA

SD core 576i processing in simultaneous mode with all

background ports enabled

SCART processing in simultaneous mode with all

background ports enabled

PLL Supply Current

I_PVDD

27

25

24

30

29

28

mA

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with all background ports enabled

34

35

37

38

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color with all background ports

enabled

33

36

38

mA

SD core 576i processing in simultaneous mode with all

background ports enabled

SCART processing in simultaneous mode with all

background ports enabled

Rev. B | Page 6 of 32

Data Sheet

ADV7844

Parameter

Symbol

Min Typ Max

210 235

Unit

mA

Test Conditions/Comments

Analog Supply Current

I_AVDD

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with all background ports enabled

215 240

214 235

0

0.1

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color with all background ports

enabled

80

90

mA

SD core 576i processing in simultaneous mode with all

background ports enabled

SCART processing in simultaneous mode with all

background ports enabled

One port connected

Four ports connected

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color in simultaneous mode

with all background ports enabled

260 285

85 95

260 280

105 120

420 440

Terminator Supply Current⁴I_TVDD

Comparator Supply Current I_CVDD

mA

I_{VDD_SDRAM}

Memory Interface Supply

Current

28

35

mA

CVBS input sampling at 54 MHz

Power-Down Currents⁵

I_DVDDIO

I_{VDD_SDRAM}

I_VDD

I_AVDD

I_CVDD

I_TVDD

I_PVDD

t_PWRUP

0.1

2.6

10

0.1

0.5

2.2

1.7

mA

ms

Power-Up Time

25

¹All maximum current values are guaranteed by characterization to assist in power supply design.

²Typical current consumption values are recorded with nominal voltage supply levels, SMPTE bar video pattern, and at room temperature.

³Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature.

⁴Termination power supply includes TVDD current consumed off chip.

⁵Power-down mode entered by setting Bit POWER_DOWN high.

Rev. B | Page 7 of 32

ADV7844

Data Sheet

ANALOG SPECIFICATIONS

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLAMP CIRCUITRY ¹

Input Impedance

Analog (AIN1 – AIN12)

ADC Midscale (CML)

ADC Full-Scale Level

ADC Zero-Scale Level

ADC Dynamic Range

Clamp Level (When Locked)

Clamps switched off

10

MΩ

0.91

V

mA

ꢀA

CML + 0.55

CML − 0.55

1.1

CML − 0.12

CML

Component input, Y signal

Component input, Pr signal

Component input, Pb signal

PC RGB input (R, G, B signals)

CVBS input

SCART RGB input (R, G, B signals)

S-Video input (Y Signal)

S-Video input (C Signal)

SDP only

CML

CML − 0.12

CML − 0.205

CML

0.3

0.4

9

8

Large Clamp Source Current

Large Clamp Sink Current

Fine Clamp Source Current

Fine Clamp Sink Current

SDP only

¹Specified for external clamp capacitor of 100 nF.

Rev. B | Page 8 of 32

Data Sheet

ADV7844

VIDEO SPECIFICATIONS

Table 4.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

NONLINEAR SPECIFICATIONS

Differential Phase

Differential Gain

DP

DG

LNL

CVBS input (modulated five-step)

Measured at 27 MHz LLC

Luma ramp

0.6

0.8

0.9

Degrees

%

Luma Nonlinearity

NOISE SPECIFICATIONS

SNR Unweighted

63

64

60

dB

SNR Unweighted

Luma flat field

Analog Front-End Crosstalk

LOCK TIME SPECIFICATIONS (SDP)

Horizontal Lock Range

Vertical Lock Range

Subcarrier Lock Range

Color Lock-In Time

5

%

Hz

kHz

Lines

%

40

70

f_SC

0.8

60

Sync Depth Range¹

Color Burst Range

20

1

200

%

Vertical Lock Time

300

100

ms

Lines

Horizontal Lock Time

CHROMA SPECIFICATIONS (SDP)

Chroma Amplitude Error

Chroma Phase Error

Chroma Luma Intermodulation

0.9

0.3

%

Degrees

%

Rev. B | Page 9 of 32

ADV7844

Data Sheet

TIMING CHARACTERISTICS

Data and I²C Timing Characteristics

Table 5.

Parameter¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Crystal Frequency, XTAL

Crystal Frequency Stability

Horizontal Sync Input Frequency

LLC Frequency Range

28.63636

MHz

ppm

kHz

50

110

170

10

12.825

MHz

I²C PORTS

SCL Frequency

400

kHz

ns

μs

ns

μs

SCL Minimum Pulse Width High

SCL Minimum Pulse Width Low

Start Condition Hold Time

Start Condition Setup Time

SDA Setup Time

SCL and SDA Rise Time

SCL and SDA Fall Time

Stop Condition Setup Time

TTX I²C PORTS

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

600

1.3

600

100

1000

300

0.6

SCL Frequency

3.4

MHz

ns

SCL Minimum Pulse Width High

SCL Minimum Pulse Width Low

Start Condition Hold Time

Start Condition Setup Time

SDA Setup Time

SCL and SDA Rise Time

SCL and SDA Fall Time

Stop Condition Setup Time

RESET FEATURE

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

60

160

10

80

160

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC Mark-Space Ratio

t₉:t₁₀

45:55

55:45

% duty cycle

DATA AND CONTROL OUTPUTS²

Data Output Transition Time SDR (SDP)

Data Output Transition Time SDR (CP)

I²S PORT, MASTER MODE

SCLK Mark-Space Ratio

LRCLK Data Transition Time

I2Sx Data Transition Time

t₁₁

t₁₂

t₁₃

t₁₄

End of valid data to negative clock edge

Negative clock edge to start of valid data

End of valid data to negative clock edge

Negative clock edge to start of valid data

2.9

0.2

1.5

0.1

4.6

0.6

2.2

0.3

ns

t₁₅:t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

45:55

55:45

10

5

% duty cycle

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

ns

5

¹Guaranteed by characterization.

²With the DLL block on output clock bypassed.

Rev. B | Page 10 of 32

Data Sheet

ADV7844

TIMING DIAGRAMS

t₃

t₅

t₃

SDA

SCL

t₆

t₁

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₉

t₁₀

LLC

t₁₁

t₁₂

P0 TO P35, HS/CS,

VS/FIELD, FIELD/DE

Figure 4. Pixel Port and Control SDR Output Timing (SDP)

t₉

t₁₀

LLC

t₁₃

t₁₄

P0 TO P35, HS/CS,

VS/FIELD, FIELD/DE

Figure 5. Pixel Port and Control SDR Output Timing (CP)

t₁₅

SCLK

t₁₆

t₁₇

LRCLK

t₁₈

t₁₉

I2Sx

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

t₂₀

t₁₉

I2Sx

2

MSB

I S MODE

MSB – 1

t₂₀

t₁₉

I2Sx

RIGHT-JUSTIFIED

MODE

MSB

LSB

t₂₀

NOTES

1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3 ENDING PIN NAMES.

2. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN.

3. I2Sx ARE SIGNALS ACCESSIBLE VIA AP1 TO AP4 PINS.

Figure 6. I²S Timing

Rev. B | Page 11 of 32

ADV7844

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the ADV7844, the

user is advised to turn off unused sections of the part.

Parameter

Rating

AVDD to GND

2.2 V

VDD to GND

PVDD to GND

DVDDIO to GND

VDD_SDRAM to GND

CVDD to GND

2.2 V

4.0 V

2.2 V

4.0 V

Due to PCB metal variation, and therefore variation in PCB

heat conductivity, the value of θ_JAmay differ for various PCBs.

The most efficient measurement solution is obtained using the

package surface temperature to estimate the die temperature

because this eliminates the variance associated with the θ_JAvalue.

TVDD to GND

The maximum junction temperature (T_{J MAX}) of 125°C must not be

exceeded. The following equation calculates the junction tempera-

ture using the measured package surface temperature and applies

only when no heat sink is used on the device under test (DUT):

AVDD to PVDD

AVDD to VDD

TVDD to CVDD

−0.3 V to +0.3 V

−0.3 V to +2.2 V

−0.3 V to +3.3 V

−0.3 V to +2 V

−0.3 V to DVDDIO + 0.3 V

5.5 V

−0.3 V to AVDD + 0.3 V

−0.3 V to PVDD + 0.3 V

125°C

−65°C to +150°C

260°C

DVDDIO to VDD_SDRAM

VDD_SDRAM to AVDD

VDD_SDRAM to VDD

Digital Inputs Voltage to GND

Digital Outputs Voltage to GND

5 V Tolerant Digital Inputs to GND¹

Analog Inputs to GND

XTALN and XTALP to GND

Maximum Junction Temperature (T_{J MAX}

Storage Temperature Range

T_J= T_S+

(

Ψ _JT×W_TOTAL

)

where:

T_Sis the package surface temperature (°C).

Ψ_JT= 0.7°C/W for the 425-ball CSP_BGA.

W_TOTAL= (PVDD × I_PVDD) + (0.4 × TVDD × I_TVDD) +

(CVDD × I_CVDD) + (AVDD × I_AVDD) + (VDD × I_VDD) +

(A × DVDDIO × I_DVDDIO) + (VDD_SDRAM × I_{VDD_SDRAM}

)

Infrared Reflow Soldering

(20 sec)

where 0.4 reflects the 40ꢀ of TVDD power that is dissipated on

the part itself.

A = 0.5 when the output pixel clock is >74 MHz.

A = 0.75 when the output pixel clock is ≤74 MHz.

¹The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI5,

HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, DDCA_SCL, DDCA_SDA, DDCB_SCL,

DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, and DDCD_SDA.

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. B | Page 12 of 32

Data Sheet

ADV7844

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

ARC_1–

A

B

C

D

E

F

GND VS/FIELD TEST6 TEST7 TVDD RXD_2– RXD_1– RXD_0– RXD_C– ARC_2– TVDD RXC_2– RXC_1– RXC_0– RXC_C–

HS/CS ^FIELD/DETEST8 TEST9 TVDD RXD_2+ RXD_1+ RXD_0+ RXD_C+ ARC_2+ TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+

NC

TVDD RXB_2– RXB_1– RXB_0– RXB_C–

TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+

GND

A

B

C

D

E

F

ARC_1+

NC

GND

P0

P2

P1

P3

TEST10 TEST11 TVDD PWRDN1 TEST14 HPA_D RXD_5V RXC_5V TVDD GND GND GND GND GND GND TVDD TVDD TVDD TVDD TVDD TVDD

TEST12 TEST13 TVDD ^SYNC_OUTCEC HPA_C RXB_5V HPA_B TVDD RXA_5V HPA_A ^{DDCD_SDADDCD_SCLDDCC_SDADDCC_SCL}RTERMDDCB_SDADDCB_SCL TVDD RXA_2+ RXA_2–

DVDDIO DVDDIO GND

GND

DDCA_SDA CVDD RXA_1+ RXA_1–

DDCA_SCL CVDD RXA_0+ RXA_0–

VGA_SCL CVDD RXA_C+ RXA_C–

P5

P7

P4

P6 EP_CS EP_SCK

P8

P10 MCLK AP0

P12 AP5 SCLK

EP_MISO EP_MOSI

G

GND GND GND GND TEST1 TEST2 GND GND CVDD CVDD CVDD

GND GND GND GND GND GND GND GND CVDD CVDD CVDD

G

H

J

P9

TTX_SDA TTX_SCL

VGA_SDA CVDD

NC

H

J

P11

PVDD TEST3 GND GND

PVDD GND XTALN XTALP

GND GND GND GND GND GND GND GND GND GND

GND

K

L

P13

K

L

VDD

GND GND GND GND GND GND GND GND GND

DVDDIO DVDDIO GND

GND

AP3

AP1

SDA

GND GND GND GND

GND GND REFN REFP

AVDD AVDD AVDD AVDD

M

N

P

P15

P17

P18

P20

P22

P14

P16

P19

AP4

AP2

SCL

M

N

P

R

T

AVDD AVDD AIN11 AIN12

HS_IN2/TRI7 VS_IN2/TRI8

R

T

P21 TEST4 INT1

P23 TEST5 INT2

VDD

GND GND GND GND GND GND GND GND GND

GND

SYNC4 AIN10

GND GND GND GND

TRI4 TRI3 AIN9 AIN8

TRI1 TRI2 SYNC3 AIN7

AVDD AVDD AVDD AVDD

U

V

DVDDIO DVDDIO DVDDIO DVDDIO

VDD

GND GND

U

V

W

Y

LLC

P25

P27

P24 RESET AVLINK

W

Y

P26

P28

P30

P32

NC

SPDIF_IN

SDRAM_DQ15

SDRAM_CKE VDD_SDRAM

SDRAM_DQ11

VDD_SDRAM SDRAM_A11 SDRAM_A6

SDRAM_A2

SDRAM_CS SDRAM_LDQS

SDRAM_DQ6 SDRAM_DQ2

SDRAM_DQ5 SDRAM_DQ1

GND

P34

GND GND

GND

GND AOUT

GND NC

GND SYNC1

NC

AIN5 AIN6

SDRAM_DQ12 SDRAM_DQ8 SDRAM_CK VDD_SDRAM

VDD_SDRAM SDRAM_A9

SDRAM_A8

SDRAM_A5

SDRAM_A4

SDRAM_A1 SDRAM_RAS SDRAM_DQ7

AA P29

AB P31

NC SYNC2 AIN4 AA

SDRAM_BA1 SDRAM_CAS VDD_SDRAM SDRAM_DQ4 SDRAM_DQ0 SDRAM_DQ13 SDRAM_DQ9 SDRAM_CK VDD_SDRAM

HS_IN1/TRI5 VS_IN1/TRI6

SDRAM_A0

NC

GND DVDDIO

GND AB

SDRAM_DQ14 SDRAM_DQ10 SDRAM_UDQS VDD_SDRAM

SDRAM_A7

SDRAM_A3

SDRAM_A10 SDRAM_BA0 SDRAM_WE VDD_SDRAM SDRAM_DQ3 SDRAM_VREF

AC GND

1

P33

2

P35

3

NC

4

GND DVDDIO

GND AIN1 AIN2 AIN3 GND AC

19 20 21 22 23

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Figure 7. Pin Configuration

Rev. B | Page 13 of 32

ADV7844

Data Sheet

Table 7. Pin Function Descriptions

Pin No. Mnemonic

Type

Description

A1

A2

GND

VS/FIELD

Ground

Digital video output

Ground.

Vertical Synchronization Output Signal (VS).

Field Synchronization Output Signal in All Interlaced Video Modes (FIELD).

VS or FIELD can be configured for this pin.

A3

TEST6

Test pin

Float this pin.

A4

TEST7

Test pin

Float this pin.

A5

TVDD

Power

Terminator Supply Voltage (3.3 V).

A6

A7

A8

A9

RXD_2−

RXD_1−

RXD_0−

RXD_C−

ARC_2−

TVDD

RXC_2−

RXC_1−

RXC_0−

RXC_C−

NC

HDMI input

HDMI input/output

Power

HDMI input

No connect

Power

HDMI input

HDMI input/output

Ground

Digital Input Channel 2 Complement of Port D in the HDMI Interface.

Digital Input Channel 1 Complement of Port D in the HDMI Interface.

Digital Input Channel 0 Complement of Port D in the HDMI Interface.

Digital Input Clock Complement of Port D in the HDMI Interface.

Audio Return Channel (ARC) Complement in ARC Interface 2.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 2 Complement of Port C in the HDMI Interface.

Digital Input Channel 1 Complement of Port C in the HDMI Interface.

Digital Input Channel 0 Complement of Port C in the HDMI Interface.

Digital Input Clock Complement of Port C in the HDMI Interface.

No Connect.

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

TVDD

Terminator Supply Voltage (3.3 V).

RXB_2−

RXB_1−

RXB_0−

RXB_C−

ARC_1−

GND

Digital Input Channel 2 Complement of Port B in the HDMI Interface.

Digital Input Channel 1 Complement of Port B in the HDMI Interface.

Digital Input Channel 0 Complement of Port B in the HDMI Interface.

Digital Input Clock Complement of Port B in the HDMI Interface.

Audio Return Channel (ARC) Complement in ARC Interface 1.

Ground.

HS/CS

Digital video output

Horizontal Synchronization Output Signal (HS).

Composite Synchronization Signal (CS). CS is a single signal containing both

horizontal and vertical synchronization pulses.

HS or CS can be configured for this pin.

B2

FIELD/DE

Miscellaneous digital

Field Synchronization Output Signal in All Interlaced Video Modes (FIELD).

Data Enable (DE). DE is a signal that indicates active pixel data.

DE or FIELD can be configured for this pin.

B3

TEST8

Test pin

Float this pin.

B4

TEST9

Test pin

Float this pin.

B5

TVDD

Power

Terminator Supply Voltage (3.3 V).

B6

B7

B8

B9

RXD_2+

RXD_1+

RXD_0+

RXD_C+

ARC_2+

TVDD

RXC_2+

RXC_1+

RXC_0+

RXC_C+

NC

HDMI input

HDMI input/output

Power

HDMI input

No Connect

Power

HDMI input

HDMI input/output

Ground

Digital Input Channel 2 True of Port D in the HDMI Interface.

Digital Input Channel 1 True of Port D in the HDMI Interface.

Digital Input Channel 0 True of Port D in the HDMI Interface.

Digital Input Clock True of Port D in the HDMI Interface.

Audio Return Channel (ARC) True in ARC Interface 2.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 2 True Of Port C in the HDMI Interface.

Digital Input Channel 1 True Of Port C in the HDMI Interface.

Digital Input Channel 0 True Of Port C in the HDMI Interface.

Digital Input Clock True Of Port C in the HDMI Interface.

No Connect.

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

TVDD

Terminator Supply Voltage (3.3 V).

RXB_2+

RXB_1+

RXB_0+

RXB_C+

ARC_1+

GND

Digital Input Channel 2 True of Port B in the HDMI Interface.

Digital Input Channel 1 True of Port B in the HDMI Interface.

Digital Input Channel 0 True of Port B in the HDMI Interface.

Digital Input Clock True of Port B in the HDMI Interface.

Audio Return Channel (ARC) True in ARC Interface 1.

Ground.

Rev. B | Page 14 of 32

Data Sheet

ADV7844

Pin No. Mnemonic

Type

Description

C1

C2

C3

C4

C5

C6

P0

P1

TEST10

TEST11

TVDD

PWRDN1

Digital video output

Test pin

Power

Video Pixel Output Port.

Float this pin.

Terminator Supply Voltage (3.3 V).

Miscellaneous digital

Controls the Power-Up of the ADV7844. Should be connected to a digital 3.3 V I/O

supply to power up the ADV7844.

C7

C8

C9

TEST14

HPA_D

RXD_5V

RXC_5V

TVDD

GND

TVDD

Test pin

Tie this pin to ground via a 4.7 kΩ resistor.

Hot Plug Assert Signal Output for HDMI Port D.

5 V Detect Pin for Port D in the HDMI Interface.

5 V Detect Pin for Port C in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Ground.

Miscellaneous digital

HDMI input

Power

Ground

Power

Digital video output

Test pin

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

D2

D3

D4

D5

D6

D7

D8

D9

Ground.

Terminator Supply Voltage (3.3 V).

Video Pixel Output Port.

Float this pin.

Terminator Supply Voltage (3.3 V).

Sliced synchronization output.

Consumer Electronic Control Channel.

Hot Plug Assert Signal Output for HDMI Port C.

5 V Detect Pin for Port B in the HDMI Interface.

Hot Plug Assert Signal Output for HDMI Port B.

Terminator Supply Voltage (3.3 V).

5 V Detect Pin for Port A in the HDMI Interface.

Hot Plug Assert Signal Output for HDMI Port A.

HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant.

HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant.

HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.

P2

P3

TEST12

TEST13

TVDD

SYNC_OUT

CEC

HPA_C

RXB_5V

HPA_B

TVDD

RXA_5V

HPA_A

DDCD_SDA

DDCD_SCL

DDCC_SDA

DDCC_SCL

RTERM

Test pin

Power

Miscellaneous digital

Digital input/output

Miscellaneous digital

HDMI input

Miscellaneous digital

Power

HDMI input

Miscellaneous digital

Digital input/output

Digital input

Digital input/output

Digital input

Miscellaneous analog

D10

D11

D12

D13

D14

D15

D16

D17

D18

Sets Internal Termination Resistance. A 500 Ω resistor between this pin and GND

should be used.

D19

D20

D21

D22

D23

E1

DDCB_SDA

DDCB_SCL

TVDD

RXA_2+

RXA_2−

DVDDIO

GND

Digital input/output

Digital input

Power

HDMI input

Power

HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant.

HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 2 True of Port A in the HDMI Interface.

Digital Input Channel 2 Complement of Port A in the HDMI Interface.

Digital I/O Supply Voltage (3.3 V).

E2

E3

Power

Ground

Digital I/O Supply Voltage (3.3 V).

Ground.

E4

GND

Ground

Ground.

E20

E21

DDCA_SDA

CVDD

Digital input/output

Power

HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant.

Comparator Supply Voltage (1.8 V).

Rev. B | Page 15 of 32

ADV7844

Data Sheet

Pin No. Mnemonic

Type

Description

E22

E23

F1

F2

F3

RXA_1+

RXA_1−

P5

HDMI input

Digital video output

Digital output

Digital input

Power

HDMI input

Digital video output

Digital output

Ground

Digital Input Channel 1 True of Port A in the HDMI Interface.

Digital Input Channel 1 Complement of Port A in the HDMI Interface.

Video Pixel Output Port.

SPI Master In/Slave Out for External EDID Interface.

SPI Master Out/Slave In for External EDID Interface.

HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.

Comparator Supply Voltage (1.8 V).

Digital Input Channel 0 True of Port A in the HDMI Interface.

Digital Input Channel 0 Complement of Port A in the HDMI Interface.

Video Pixel Output Port.

P4

EP_MISO

EP_MOSI

DDCA_SCL

CVDD

RXA_0+

RXA_0−

P7

F4

F20

F21

F22

F23

G1

G2

G3

P6

EP_CS

EP_SCK

GND

SPI Chip Select for External EDID Interface.

G4

G7

SPI Clock for External EDID Interface.

Ground.

G8

GND

Ground

Ground.

G9

GND

Ground

Ground.

G10

G11

G12

G13

G14

G15

G16

G17

G20

G21

G22

G23

H1

GND

Ground

Test

Ground

Power

Ground.

Do Not Connect.

Ground.

TEST1

TEST2

GND

Ground.

CVDD

VGA_SCL

CVDD

RXA_C+

RXA_C−

P9

Comparator Supply Voltage (1.8 V).

DDC Port Serial Clock Input for VGA.

Comparator Supply Voltage (1.8 V).

Digital Input Clock True of Port A in the HDMI Interface.

Digital Input Clock Complement of Port A in the HDMI Interface.

Video Pixel Output Port.

Miscellaneous digital

Power

HDMI input

Digital video output

Miscellaneous digital

Ground

H2

H3

H4

H7

P8

Video Pixel Output Port.

TTX_SDA

TTX_SCL

GND

I²C Port Serial Data Input/Output. SDA is the data line for the teletext port.

I²C Port Serial Clock Input. SCL is the clock line for the teletext port.

Ground.

H8

GND

Ground

Ground.

H9

GND

Ground

Ground.

H10

H11

H12

H13

H14

H15

H16

H17

H20

H21

H22

H23

J1

GND

Ground

Power

Ground.

GND

Ground.

CVDD

VGA_SDA

CVDD

NC

P11

P10

MCLK

AP0

Comparator Supply Voltage (1.8 V).

DDC Port Serial Data Input/Output for VGA.

Comparator Supply Voltage (1.8 V).

No Connect.

Miscellaneous digital

Power

No Connect

Digital video output

Miscellaneous

Ground

No Connect.

Video Pixel Output Port.

Audio Master Clock Output.

Audio Output.

J2

J3

J4

J7

GND

Ground.

Rev. B | Page 16 of 32

Data Sheet

ADV7844

Pin No. Mnemonic

Type

Description

Ground.

PLL Supply Voltage (1.8 V).

Do Not Connect.

Ground.

J8

J9

GND

PVDD

TEST3

GND

P13

Ground

Power

Test

Ground

Digital video output

Miscellaneous

Miscellaneous digital

Power

Ground

Power

Ground

J10

J11

J12

J13

J14

J15

J16

J17

J20

J21

J22

J23

K1

Ground.

Video Pixel Output Port.

Audio Output.

Audio Serial Clock Output.

Digital Core Supply Voltage (1.8 V).

Ground.

K2

P12

K3

AP5

K4

K7

K8

K9

SCLK

VDD

GND

PVDD

GND

XTALN

XTALP

K10

K11

K12

K13

K14

K15

K16

K17

K20

K21

K22

K23

Ground.

PLL Supply Voltage (1.8 V).

Ground.

Input Pin for 28.63636 MHz Crystal.

Input pin for 28.63636 MHz Crystal or an external 1.8 V, 28.63636 MHz Clock Oscillator

Source to Clock the ADV7844.

Miscellaneous analog

L1

L2

L3

L4

L7

L8

L9

L10

L11

L12

L13

L14

L15

L16

L17

L20

L21

L22

L23

DVDDIO

GND

VDD

Power

Ground

Power

Digital I/O Supply Voltage (3.3 V).

Ground.

Digital Core Supply Voltage (1.8 V).

Ground.

GND

Ground

Ground.

Rev. B | Page 17 of 32

ADV7844

Data Sheet

Pin No. Mnemonic

Type

Description

M1

M2

M3

M4

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M20

M21

M22

M23

N1

N2

N3

N4

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

N22

N23

P1

P15

P14

AP4

AP3

Digital video output

Miscellaneous

Power

Ground

Miscellaneous analog

Digital video output

Miscellaneous

Power

Ground

Power

Video Pixel Output Port.

Audio Output.

Digital Core Supply Voltage (1.8 V).

Ground.

VDD

GND

REFN

REFP

P17

Ground.

Internal Voltage Reference Output.

Video Pixel Output Port.

Audio Output.

Digital Core Supply Voltage (1.8 V).

Ground.

P16

AP2

AP1

VDD

GND

AVDD

P18

Ground.

Analog Supply Voltage (1.8 V).

Video Pixel Output Port.

I²C Port Serial Clock Input. SCL is the clock line for the control port.

Power

Digital video output

Miscellaneous digital

Power

Ground

P2

P3

P4

P7

P8

P9

P10

P11

P12

P13

P14

P15

P16

P17

P19

SCL

SDA

VDD

GND

I²C Port Serial Data Input/Output. SDA is the data line for the control port.

Digital Core Supply Voltage (1.8 V).

Ground.

Rev. B | Page 18 of 32

Data Sheet

ADV7844

Pin No. Mnemonic

Type

Description

P20

P21

P22

P23

R1

R2

R3

R4

AVDD

AIN11

AIN12

P20

P21

TEST4

INT1

Power

Analog Supply Voltage (1.8 V).

Analog Video Input Channel.

Video Pixel Output Port.

This pin should be tied to ground.

Interrupt. This pin can be active low or active high. When status bits change, this pin

is triggered. The events that trigger an interrupt are under user control.

Analog video input

Digital video output

Test

Miscellaneous digital

R7

VDD

Power

Digital Core Supply Voltage (1.8 V).

R8

R9

GND

Ground

Ground.

R10

R11

R12

R13

R14

R15

R16

R17

R20

GND

HS_IN2/TRI7

Ground

Miscellaneous analog

HS on Graphics Port 2 (HS_IN2). The HS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI7). (Selection

available via the I²C.)

R21

R22

VS_IN2/TRI8

SYNC4

Miscellaneous analog

VS on Graphics Port 2 (VS_IN2). The VS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI8). (Selection

available via the I²C.)

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

R23

T1

T2

T3

T4

AIN10

P22

P23

TEST5

INT2

Analog video input

Digital video output

Test

Analog Video Input Channel.

Video Pixel Output Port.

Do Not Connect.

Interrupt. This pin can be active low or active high. When status bits change, this pin

is triggered. The events that trigger an interrupt are under user control.

Miscellaneous digital

T7

VDD

Power

Digital Core Supply Voltage (1.8 V).

T8

T9

GND

Ground

Power

Ground.

T10

T11

T12

T13

T14

T15

T16

T17

T20

T21

T22

T23

U1

DVDDIO

VDD

Digital I/O Supply Voltage (3.3 V).

Digital Core Supply Voltage (1.8 V).

U2

U3

U4

U7

Power

Rev. B | Page 19 of 32

ADV7844

Data Sheet

Pin No. Mnemonic

Type

Description

U8

U9

VDD

GND

TRI4

Power

Ground

Miscellaneous analog

Digital Core Supply Voltage (1.8 V).

Ground.

U10

U11

U12

U13

U14

U15

U16

U17

U20

Ground.

Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via

the I²C.)

U21

TRI3

Miscellaneous analog

Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via

the I²C.)

U22

U23

V1

V2

V3

AIN9

AIN8

LLC

P24

RESET

Analog video input

Digital video output

Miscellaneous digital

Analog Video Input Channel.

Line-Locked Output Clock for the Pixel Data.

Video Pixel Output Port.

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required

to reset the ADV7844 circuitry.

V4

V20

AVLINK

TRI1

Digital input/output

Miscellaneous analog

Digital SCART Control Channel.

Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via

the I²C.)

V21

V22

TRI2

Miscellaneous analog

Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via

the I²C.)

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

SYNC3

V23

W1

W2

W3

W4

W20

W21

W22

W23

Y1

AIN7

P25

P26

NC

SPDIF_IN

AVDD

Analog video input

Digital video output

No connect

Miscellaneous digital

Power

Analog Video Input Channel.

Video Pixel Output Port.

No Connect.

S/PDIF Stream Input.

Analog Supply Voltage (1.8 V).

Video Pixel Output Port.

Ground.

P27

P28

GND

Digital video output

Ground

Y2

Y3

Y4

GND

Ground

Ground.

Y5

GND

Ground

Ground.

Y6

Y7

Y8

Y9

VDD_SDRAM

SDRAM_A11

SDRAM_A6

SDRAM_A2

SDRAM_CS

Power

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Address Output. Interface to external RAM address lines.

Chip Select. SDRAM_CS enables and disables the command decoder on the RAM.

One of four command signals to the external SDRAM.

SDRAM interface

Y10

Y11

SDRAM_LDQS SDRAM interface

Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an

input when reading data from external memory and output when writing data to

external memory. It is edge-aligned when reading from external memory and

centered with data when reading to external memory. SDRAM_ LDQS corresponds

to the data on SDRAM_DQ7 to SDRAM_DQ0.

Y12

Y13

Y14

GND

SDRAM_DQ6

SDRAM_DQ2

Ground

SDRAM interface

Ground.

Data Bus. Interface to external RAM 16-bit data bus.

Rev. B | Page 20 of 32

Data Sheet

ADV7844

Pin No. Mnemonic

Type

Description

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

SDRAM_DQ15 SDRAM interface

SDRAM_DQ11 SDRAM interface

Data Bus. Interface to external RAM 16-bit data bus.

Clock Enable. This pin acts as an enable to the clock signals of the external RAM.

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Ground.

SDRAM_CKE

VDD_SDRAM

GND

SDRAM interface

Power

Ground

AOUT

Analog monitor output Analog Monitor Output.

NC

No connect

No Connect.

Analog Video Input Channel.

Video Pixel Output Port.

Ground.

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Address Output. Interface to external RAM address lines.

Row Address Select Command Signal. One of four command signals to the external

SDRAM.

AIN5

AIN6

P29

P30

Analog video input

Digital video output

Ground

GND

Ground

GND

Ground

VDD_SDRAM

SDRAM_A9

SDRAM_A5

SDRAM_A1

SDRAM_RAS

Power

SDRAM interface

AA11

AA12

AA13

AA14

AA15

AA16

AA17

SDRAM_DQ7

GND

SDRAM_DQ5

SDRAM_DQ1

SDRAM_DQ12 SDRAM interface

SDRAM_DQ8

SDRAM_CK

SDRAM interface

Ground

SDRAM interface

Data Bus. Interface to external RAM 16-bit data bus.

Ground.

Data Bus. Interface to external RAM 16-bit data bus.

Differential Clock Output. All address and control output signals to the RAM should

be sampled on the positive edge of SDRAM_CK and on the negative edge of

SDRAM_CK.

SDRAM interface

AA18

AA19

AA20

AA21

AA22

VDD_SDRAM

GND

NC

SYNC2

Power

Ground

No connect

Miscellaneous analog

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Ground.

No Connect.

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

AA23

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

AB10

AB11

AIN4

P31

P32

P34

NC

GND

DVDDIO

SDRAM_A8

SDRAM_A4

SDRAM_A0

SDRAM_BA1

SDRAM_CAS

Analog video input

Digital video output

No connect

Analog Video Input Channel.

Video Pixel Output Port.

No Connect.

Ground.

Digital I/O Supply Voltage (3.3 V).

Address Output. Interface to external RAM address lines.

Bank Address Output. Interface to external RAM bank address lines.

Ground

Power

SDRAM interface

Column Address Select Command Signal. One of four command signals to the

external SDRAM.

AB12

AB13

AB14

AB15

AB16

VDD_SDRAM

SDRAM_DQ4

SDRAM_DQ0

SDRAM_DQ13 SDRAM interface

SDRAM_DQ9 SDRAM interface

Power

SDRAM interface

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Data Bus. Interface to external RAM 16-bit data bus.

Rev. B | Page 21 of 32

ADV7844

Data Sheet

Pin No. Mnemonic

Type

Description

AB17

SDRAM_CK

SDRAM interface

Differential Clock Output. All address and control output signals to the RAM should

be sampled on the positive edge of SDRAM_CK and on the negative edge of

SDRAM_CK.

AB18

AB19

AB20

VDD_SDRAM

GND

SYNC1

Power

Ground

Miscellaneous analog

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Ground.

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

AB21

AB22

HS_IN1/TRI5

VS_IN1/TRI6

Miscellaneous analog

HS on Graphics Port 1 (HS_IN1). The HS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI5). (Selection

available via the I²C.)

VS on Graphics Port 1 (VS_IN2). The VS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI6). (Selection

available via the I²C.)

AB23

AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

AC10

AC11

GND

P33

P35

NC

GND

DVDDIO

SDRAM_A7

SDRAM_A3

SDRAM_A10

SDRAM_BA0

SDRAM_WE

Ground

Digital video output

No connect

Ground.

Video Pixel Output Port.

No Connect.

Ground.

Digital I/O Supply Voltage (3.3 V).

Address Output. Interface to external RAM address lines.

Bank Address Output. Interface to external RAM bank address lines.

Ground

Power

SDRAM interface

Write Enable Output Command Signal. One of four command signals to the external

SDRAM.

AC12

AC13

AC14

AC15

AC16

AC17

VDD_SDRAM

SDRAM_DQ3

SDRAM_VREF

SDRAM_DQ14 SDRAM interface

SDRAM_DQ10 SDRAM interface

SDRAM_UDQS SDRAM interface

Power

SDRAM interface

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Data Bus. Interface to external RAM 16-bit data bus.

1.25 V Reference for DDR SDRAM Interface or 1.65 V for SDR.

Data Bus. Interface to external RAM 16-bit data bus.

Upper Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an

input when reading data from external memory and an output when writing data

to external memory. It is edge-aligned with data when reading from external

memory and centered with data when writing to external memory. SDRAM_UDQS

corresponds to the data on SDRAM_DQ15 to SDRAM_DQ8.

AC18

AC19

AC20

AC21

AC22

AC23

VDD_SDRAM

GND

AIN1

AIN2

AIN3

Power

Ground

Analog video input

Ground

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Ground.

Analog Video Input Channel.

Ground.

GND

Rev. B | Page 22 of 32

Data Sheet

ADV7844

POWER SUPPLY SEQUENCING

Notes

Reset should be held low while the supplies are being powered up.

POWER-UP SEQUENCE

The recommended power-up sequence of the ADV7844 is as

follows:

•

3.3 V supplies should be powered up first.

2.5 V supply should be powered after the 3.3 V supplies are

established but before the 1.8 V supplies.

1. 3.3 V supplies

2. 2.5 V supply (applies only if using DDR memory)

3. 1.8 V supplies

•

1.8 V supplies should be powered up last.

3.3V SUPPLIES

3.3V

The ADV7844 can alternatively be powered up by asserting all

supplies simultaneously.

2.5V

In this case, care must be taken to ensure that a lower rated supply

does not go above a higher rated supply level, as the supplies are

being established.

2.5V SUPPLIES (IF ANY)

1.8V SUPPLIES

1.8V

POWER-DOWN SEQUENCE

The ADV7844 supplies can be deasserted simultaneously as long

as a higher rated supply does not go below a lower rated supply.

3.3V SUPPLIES

POWER-UP

2.5V SUPPLIES 1.8V SUPPLIES

POWER-UP POWER-UP

Figure 8. Recommended Power-Up Sequence

Rev. B | Page 23 of 32

ADV7844

Data Sheet

FUNCTIONAL OVERVIEW

•

Repeater support

Internal E-EDID RAM

Hot plug assert output pin for each HDMI port

CEC controller

HDMI RECEIVER

The ADV7844 front end incorporates a 4:1 multiplexed HDMI

receiver with Xpressview fast switching technology and support

for HDMI features including ARC and 3D TV. Building on the

feature set of Analog Devices existing HDMI devices, the

ADV7844 also offers support for all HD TV formats up to 12-

bit, 1080p Deep Color and all display resolutions up to UXGA

(1600 × 1200 at 60 Hz). Xpressview fast switching technology,

using Analog Devices hardware-based HDCP engine that

minimizes software overhead, allows switching between any

two input ports in less than 1 second.

ANALOG FRONT END

The ADV7844 analog front end comprises four 170 MHz, 12-bit

ADCs that digitize the analog video signal before applying it to

the standard definition processor (SDP) or component

processor (CP). The analog front end uses differential channels

to each ADC to ensure high performance in a mixed-signal

application.

With the inclusion of HDCP 1.4, the ADV7844 can receive

encrypted video content. The HDMI interface of the ADV7844

allows for authentication of a video receiver, decryption of encoded

data at the receiver, and renewal of that authentication during

transmission, as specified by the HDCP 1.4 protocol. Repeater

support is also offered by the ADV7844.

The front end also includes a 12-channel input mux that enables

multiple video signals to be applied to the ADV7844 without

the requirement of an external mux.

Current and voltage clamp control loops ensure that any dc

offsets are removed from the video signal. The clamps are

positioned in front of each ADC to ensure that the video signal

remains within the range of the converter.

The ADV7844 supports the audio return channel feature. There

is a dedicated S/PDIF input on which audio can be received for

retransmission on the HDMI input. A wide range of 3D video

formats is supported, including frame packing 1080p 24 Hz,

720p 50 Hz, and 720p 60 Hz.

The ADCs are configured to run up to 8× oversampling mode

when decoding composite or S-Video inputs. For component

525i, 625i, 525p, and 625p sources, 4× oversampling is performed.

All other video standards are 1× oversampled. Oversampling

the video signals reduces the cost and complexity of external

antialiasing filters with the benefit of an increased signal-to-

noise ratio (SNR).

The HDMI receiver incorporates active equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. It is capable of

equalizing for cable lengths up to 30 meters to achieve robust

receiver performance at even the highest HDMI data rates.

Optional internal antialiasing filters with programmable

bandwidth are positioned in front of each ADC. These filters

can be used to band limit video signals, removing spurious, out-

of-band noise.

The HDMI receiver offers advanced audio functionality. It

supports multichannel I²S audio for up to eight channels. It also

supports a 6-DSD channel interface with each channel carrying

an oversampled 1-bit representation of the audio signal as

delivered on SACD. The ADV7844 can also receive HBR audio

packet streams and outputs them through the HBR interface in

an S/PDIF format conforming to the IEC60958 standard.

The ADV7844 can support the simultaneous processing of

CVBS and RGB standard definition signals to enable SCART

compatibility and overlay functionality. A combination of

CVBS and RGB inputs can be mixed with the output under the

control of I²C registers.

Analog front-end features include:

The receiver contains an audio mute controller that can detect a

variety of conditions that may result in audible extraneous noise

in the audio output. On detection of these conditions, the audio

signal can be ramped to mute to prevent audio clicks or pops.

•

Four 170 MHz, NSV, 12-bit ADCs that enable true 12-bit

video decoding

12-channel analog input mux that enables multiple source

connections without the requirement of an external mux

Four current and voltage clamp control loops that ensure

any dc offsets are removed from the video signal

SCART functionality and SD RGB overlay on CVBS

controlled by fast blank input

SCART source switching detection through the TRI1 to TRI8

inputs

Four programmable antialiasing filters

HDMI receiver features include:

•

4:1 multiplexed HDMI receiver

HDMI, ARC, and 3D format support, DVI 1.0

225 MHz HDMI receiver

Integrated equalizer

High-bandwidth Digital Content Protection (HDCP 1.4)

on background ports

•

Internal HDCP keys

36-/30-bit Deep Color support

PCM, HBR, and DSD audio packet support

Rev. B | Page 24 of 32

Data Sheet

ADV7844

•

Internal color bar test pattern

STANDARD DEFINITION PROCESSOR

Advanced TBC with frame synchronization, which ensures

nominal clock and data for nonstandard input

Interlace-to-progressive conversion for 525i and 625i

formats, enabling direct drive of HDMI Tx devices

Color controls that include hue, brightness, saturation,

and contrast

The SDP is capable of decoding a large selection of baseband

video signals in composite and S-Video formats. The video

standards supported by the SDP include PAL, PAL 60, PAL M,

PAL N, PAL NC, NTSC M/J, NTSC 4.43, and SECAM. The

ADV7844 can automatically detect the video standard and

process it accordingly.

•

The SDP has a 3D temporal comb filter and a five-line adaptive

2D comb filter that gives superior chrominance and luminance

separation when decoding a composite video signal. This highly

adaptive filter automatically adjusts its processing mode according

to the video standard and signal quality with no user intervention

required. The SDP has an IF filter block that compensates for

attenuation in the high frequency chroma spectrum due to a tuner

SAW filter. The SDP has specific luminance and chrominance

parameter controls for brightness, contrast, saturation, and hue.

COMPONENT PROCESSOR

The CP section of the ADV7844 is capable of decoding and

digitizing a wide range of component video formats in any color

space. Component video standards supported by the CP are

525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to

UXGA at 60 Hz, and many other standards.

The any-to-any, 3 × 3 CSC matrix is placed between the analog

front end and the CP section. This enables YPbPr to RGB and

RGB to YCbCr conversions. Many other standards of color

space can be implemented using the color space converter.

The ADV7844 implements a patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7844 to track and decode poor quality video sources (such

as VCRs) and noisy sources (such as tuner outputs, VCR

players, and camcorders). Frame TBC ensures stable clock

synchronization between the decoder and the downstream

devices.

The CP section contains circuitry to enable the detection of

Macrovision encoded YPbPr signals for 525i, 625i, 525p, and

625p. It is designed to be fully robust when decoding these

types of signals.

VBI extraction of CGMS data is performed by the CP section of

the ADV7844 for interlaced, progressive, and high definition

scanning rates. The data extracted can be read back over the I²C

interface.

The SDP also contains both a luma transient improvement (LTI)

block and a chroma transient improvement (CTI) block. These

increase the edge rate on the luma and chroma transitions,

resulting in a sharper video image.

CP features include:

•

525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other

HDTV formats are supported

The SDP has a Macrovision® detection circuit that allows Type I,

Type II, and Type III Macrovision protection levels. The

decoder is also fully robust to all Macrovision signal inputs.

•

Supports 720p 24 Hz/25 Hz formats

Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation

SDP features include:

•

Support for analog component YPbPr and RGB video

formats with embedded synchronization, composite

synchronization or separate HS and VS

Any-to-any, 3 × 3 CSC matrix that supports YCbCr-to-

RGB and RGB-to- YCbCr, fully programmable or

preprogrammable configurations

Synchronization source polarity detector (SSPD) that

determines the source and polarity of the synchronization

signals that accompany the input video

Macrovision copy protection detection on component

formats (525i, 625i, 525p, and 625p)

Free-run output mode that provides stable timing when no

video input is present or video lock is lost

Arbitrary pixel sampling support for nonstandard video

sources

170 MHz conversion rate, which supports RGB input

resolutions up to 1600 × 1200 at 60 Hz

Automatic or manual clamp-and-gain controls for

graphics modes

Contrast, brightness, hue, and saturation controls

•

Advanced adaptive 3D comb (using either external DDR or

SDR SDRAM memory)

Adaptive 2D five-line comb filters for NTSC and PAL that

give superior chrominance and luminance separation for

composite video

Full automatic detection and autoswitching of all

worldwide standards (PAL, NTSC, and SECAM)

Automatic gain control with white peak mode that

ensures the video is always processed without loss of

the video processing range

•

Proprietary architecture for locking to weak, noisy, and

unstable sources from VCRs and tuners

IF filter block that compensates for high frequency luma

attenuation due to tuner SAW filter

•

LTI and CTI

Vertical and horizontal programmable luma peaking filters

8× oversampling (108 MHz) for CVBS, and S-Video modes

Line-locked clock (LLC) output

Free-run output mode that provides stable timing when no

video input is present or video lock is lost

Rev. B | Page 25 of 32

ADV7844

Data Sheet

•

32-phase ADC DLL that allows optimum pixel clock

sampling

OTHER FEATURES

The ADV7844 has HS, VS, FIELD, and DE output signals with

programmable position, polarity, and width, and two I²C host

port interfaces (control and VBI).

•

Automatic detection of synchronization source and

polarity by SSPD block

Standard identification enabled by STDI block

RGB that can be color space converted to YCbCr and

decimated to a 4:2:2 format for video-centric back-end IC

interfacing

•

The ADV7844 has two programmable interrupt request output

pins, INT1 and INT2. It also features a number of low power

modes and a full power-down mode.

The ADV7844 is provided in a 19 mm × 19 mm, RoHS-compliant

CSP_BGA package, and is specified over the 0°C to +70°C

temperature range.

•

Data enable (DE) output signal supplied for direct

connection to HDMI/DVI Tx IC

For more detailed product information about the ADV7844,

contact your local Analog Devices sales office.

Rev. B | Page 26 of 32

Data Sheet

ADV7844

EXTERNAL MEMORY REQUIREMENTS

The ADV7844 uses external SD RAM for 3D comb and frame

synchronizer. The ADV7844 supports either SDR or DDR

SD RAM.

DOUBLE DATA RATE (DDR)

The ADV7844 can use DDR external memory to

simultaneously provide 3D comb and frame synchronizer

operation.

SINGLE DATA RATE (SDR)

The ADV7844 can use SDR external memory to provide 3D comb

or frame synchronizer operation nonconcurrently.

There is a 128 Mb DDR SDRAM minimum memory requirement.

The required memory architecture is four banks of 2 Mb × 16

(8M16) with a speed grade of 133 MHz at CL 2.5. Using 22 Ω

series termination resistors is recommended for this configuration

There is a 64 Mb SDR SDRAM minimum memory require-

ment. The required memory architecture is four banks of

1 Mb × 16 (4M16) with a speed grade of 133 MHz at CAS

latency (CL) 3. Using 22 Ω series termination resistors is recom-

mended for this configuration.

Recommended DDR memory that is compatible with the

ADV7844 includes the K4H561638J-LCB3 from Samsung, the

MT46V16M16P-6T from Micron Technology, Inc., and the

H5DU1262GTR-E3C from Hynix, Inc.

Recommended SDR memory that is compatible with the

ADV7844 includes Winbond W9864G6PH-7.

Rev. B | Page 27 of 32

ADV7844

Data Sheet

PIXEL INPUT/OUTPUT FORMATTING

The output section of the ADV7844 is highly flexible. The pixel

output bus can support up to 36-bit 4:4:4. The pixel data

supports both single and double data rates modes. In SDR

mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is

possible. In DDR mode, the pixel output port can be configured in

8-/10-/12-bit 4:2:2 modes or 24-/30-/36-bit 4:4:4 modes. Bus

rotation and bus inversion are also supported. All output modes

are controlled via I²C controls.

PIXEL DATA OUTPUT MODES FEATURES

The output pixel port features include the following:

•

8-/10-/12-bit ITU-R BT.656 4:2:2 with embedded time

codes and/or HS, VS, and FIELD output signals

SDR 16-/20-/24-/30-/36 bit with embedded time codes

and/or HS and VS/FIELD pin timing

DDR 8-/10-/12-bit 4:2:2 with embedded time codes and/or

HS, VS, and FIELD output signals

DDR 24-/30-/36 bit 4:4:4 with embedded time codes

and/or HS, VS, and FIELD output signals

Note that DDR modes are supported up to 54 MHz by

characterization.

Rev. B | Page 28 of 32

Data Sheet

ADV7844

REGISTER MAP ARCHITECTURE

The registers of the ADV7844 are controlled via a 2-wire serial

(I²C-compatible) interface. The ADV7844 has 12 maps. The IO

map has a static I²C address. All other map addresses must be

programmed; this ensures no addressing clashes on the system.

Figure 9 shows the register map architecture.

Table 8.

Register Map Name

Default Address

0x40

0x00

Programmable Address

Not programmable

Programmable

Location at Which Address Can Be Programmed

Not applicable

IO Map

CP Map

SDP Map

SDP_IO Map

VDP Map

AVLINK Map

CEC Map

HDMI Map

IO map, Register 0xFD

IO map, Register 0xF1

IO map, Register 0xF2

IO map, Register 0xFE

IO map, Register 0xF3

IO map, Register 0xF4

IO map, Register 0xFB

IO map, Register 0xFA

IO map, Register 0xF9

IO map, Register 0xF8

IO map, Register 0xF5

EDID Map

Repeater Map

AFE, DPLL Map

InfoFrame Map

IO

MAP

CP

MAP

SDP

MAP

SDP_IO

MAP

VDP

MAP

AVLINK

MAP

CEC

MAP

SLAVE

ADDRESS:

0x40

SLAVE

ADDRESS:

PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE

SCL

SDA

SLAVE

ADDRESS:

PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE

HDMI

MAP

EDID

MAP

REPEATER

MAP

AFE, DPLL

MAP

INFOFRAME

MAP

Figure 9. Register Map Architecture

Rev. B | Page 29 of 32

ADV7844

Data Sheet

OUTLINE DIMENSIONS

19.20

A1 BALL

CORNER

19.00 SQ

18.80

22 20 18 16 14 12 10

23 21 19 17 15 13 11

8

6

4

2

A1 BALL

CORNER

9

7

5

3

1

A

C

E

G

J

B

D

F

H

K

M

P

T

17.60

BSC SQ

L

N

R

U

W

0.80

BSC

V

Y

AA

AB

AC

TOP VIEW

DETAIL A

BOTTOM VIEW

DETAIL A

1.50

1.36

1.21

1.11

1.01

0.91

0.65

NOM

0.35 NOM

0.30 MIN

0.35

NOM

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2.

Figure 10. 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-425-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Notes Temperature Range

Package Description

Package Option

2, 3

ADV7844KBCZ-5

EVAL-ADV7844EB1Z

0°C to +70°C

425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Front-End Evaluation Board

BC-425-1

3, 4, 5

¹Z = RoHS-Compliant Part.

²Speed grade: 5 = 170 MHz.

³This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to

purchase any components with internal HDCP keys.

⁴An ATV motherboard is also required to process the ADV7844 digital outputs and achieve video output. An ATV video output board is optional to evaluate

performance through an HDMI transmitter and video encoder.

⁵Front-end board for the ATV video evaluation platform, fitted with ADV7844KBCZ-5 decoder.

Rev. B | Page 30 of 32

Data Sheet

NOTES

ADV7844

Rev. B | Page 31 of 32

ADV7844

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).

HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and

other countries.

registered trademarks are the property of their respective owners.

D08850-0-4/12(B)

Rev. B | Page 32 of 32


型号：	ADV7844_12
厂家：	ADI
描述：	Quad HDMI Fast Switching Receiver
文件：	总32页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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