ADV7802BSTZ-80_技术文档

12-Bit, SDTV/HDTV 3D Comb Filter,

Video Decoder, and Graphics Digitizer

ADV7802

Data Sheet

DDR/SDR SDRAM

INTERFACE

FEATURES

ADDRESS (14)

4 noise shaped video (NSV) 12-bit ADCs

True 12-bit high dynamic range processing

12-channel analog input mux

36-bit digital YCrCb/RGB output

12-bit deep color processing

Analog monitor output

NTSC/PAL/SECAM color standards support

NTSC/PAL 3D comb filter

3D digital noise reduction (DNR)

Advanced time-base correction (TBC) with frame

synchronization

DATA (16)

CLK

ADV7802

CONTROL (9)

ANALOG INPUT INTERFACE

12

DDR/SDR

SDRAM

INTERFACE

Y

GR RGB

YPrPb

CLAMP

ADC

Cb

Cr

STANDARD

DEFINITION

PROCESSOR

(SDP)

SCART

CVBS

S-VIDEO

CLAMP

DAC

ADC_CLK

CORE_CLK

DIGITAL INPUT

INTERFACE

HS_IN1

VS_IN1

SOG

SYNC CP

SDP

PLL

ANA

DIG

HS

XTAL

Interlaced-to-progressive conversion for 525i and 625i

Advanced VBI data slicer, including teletext, CC, and V-chip

IF compensation filter

VS

ADC, CORE, MEMORY

CLK GENERATION

FLD

DE

CORE_CLK

DDS FOR SDP LINE-LOCKED

CLK GENERATION

COMPONENT

PROCESSOR

(CP)

CP

SDP

DAC

SCART fast blank support including slow switch detect

Programmable internal antialias filters

Weak, poor time-base, and nonstandard signal support

Vertical peaking, horizontal peaking, CTI, LTI

Simultaneous interlaced and progressive parallel output for

525i/525p and 625i/625p

525p/625p component progressive scan support

720p/1080i/1080p component HDTV support

Digitizes RGB graphics with maximum pixel clock rate of

135 MHz (ADV7802BSTZ-150 model only)

24-bit digital input port supports data from DVI/HDMI Rx IC

Any-to-any, advanced 3 × 3 color space conversion matrix

Flexible output pixel interface supporting 8-/10-/12-/16-/

20-/24-/30-/36-bit SDR/DDR 4:2:2/4:4:4 data formats

Programmable interrupt request output pin

LLC

2

I C CONFIGURATION

ANALOG

DIGITAL

Figure 1. ADV7802 Block Diagram

GENERAL DESCRIPTION

The ADV7802¹is a high quality, single-chip, multiformat 3D comb

filter, video decoder, and graphics digitizer. This multiformat 3D

comb filter decoder supports the conversion of PAL, NTSC, and

SECAM standards in the form of a composite or an S-video into

a digital ITU-R BT.656 format. The ADV7802 also supports the

decoding of a component RGB/YPrPb video signal into a digital

YCrCb or RGB pixel output stream.

The support for component video includes standards such as 525i,

625i, 525p, 625p, 720p, 1080i, 1080p, and many other HD and

SMPTE standards. Graphics digitization is supported by the

ADV7802; it is capable of digitizing RGB graphics signals from

VGA to SXGA rates and converting them into a digital RGB or

YCrCb pixel output stream. SCART and overlay functionality are

enabled by the ability of the ADV7802 to simultaneously process

CVBS and standard definition RGB signals.

APPLICATIONS

AV receivers

LCD HDTVs

PDP HDTVs

CRT HDTVs

HDTV STBs with PVR

DVD recorders with progressive scan input support

Projectors

The ADV7802 contains two main processing sections. The first

section is the standard definition processor (SDP), which

processes all PAL, NTSC, SECAM, and component (up to

525p/625p) signal types. The second section is the component

processor (CP), which processes YPrPb and RGB component

formats, including RGB graphics.

1

Protected by U.S. Patent Number 4,907,093 and other intellectual

property rights.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7802* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

REFERENCE MATERIALS

Informational

• Advantiv™ Advanced TV Solutions

Technical Articles

EVALUATION KITS

• ADV7802 Evaluation Board

• Optimizing standard-definition video on high-definition

displays

DOCUMENTATION

DESIGN RESOURCES

• ADV7802 Material Declaration

• PCN-PDN Information

Application Notes

• AN-1050: A Method for Compressing I²C Scripts for the

ADV74xx/ADV75xx/ADV76xx/ADV78xx

• AN-1180: Optimizing Video Platforms for Automated

Post-Production Self-Tests

• Quality And Reliability

• Symbols and Footprints

• AN-1260: Crystal Design Considerations for Video

Decoders, HDMI Receivers, and Transceivers

DISCUSSIONS

View all ADV7802 EngineerZone Discussions.

Data Sheet

• ADV7802: 12-Bit, SDTV/HDTV 3D Comb Filter,Video

Decoder, and Graphics Digitizer Data Sheet

SAMPLE AND BUY

Visit the product page to see pricing options.

TOOLS AND SIMULATIONS

• ADV7802 IBIS Model

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

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ADV7802

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 14

Key Features ................................................................................ 14

Analog Front End....................................................................... 14

Standard Definition Processor ................................................. 14

VBI Data Processor.................................................................... 15

Component Processor ............................................................... 15

Additional Features.................................................................... 16

Single Data Rate (SDR).............................................................. 16

Double Data Rate (DDR) .......................................................... 16

Recommended External Loop Filter Components.................... 17

Typical Connection Diagrams...................................................... 18

Pixel Input/Output Formatting .................................................... 21

Pixel Data Output Modes Highlights ...................................... 21

Digital Video Input Port Highlights ........................................ 21

Outline Dimensions....................................................................... 34

Ordering Guide .......................................................................... 34

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Electrical Characteristics............................................................. 4

Video Specifications..................................................................... 6

Timing Characteristics ................................................................ 7

Timing Diagrams.......................................................................... 8

Analog Specifications................................................................... 9

Absolute Maximum Ratings.......................................................... 10

Package Thermal Performance................................................. 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

REVISION HISTORY

8/11—Revision D: Initial Version

Rev. D | Page 2 of 36

Data Sheet

ADV7802

FUNCTIONAL BLOCK DIAGRAM

0 2 0 4 - 6 5 0 6

R

T T E A M R

F D O N A O F F T I U T P O U

X

M U

X

T U M P U I N

Figure 2.

Rev. D | Page 3 of 36

ADV7802

Data Sheet

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR),

DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. T_A= 0°C to 85°C, unless

otherwise noted.

Table 1.

Parameter¹

Symbol

Test Conditions

Min

Typ

Max

Unit

STATIC PERFORMANCE^{2, 3}

Resolution (Each ADC)

Integral Nonlinearity⁴

N

INL

12

Bits

LSB

BSL at 27 MHz (at a 12-bit level)

BSL at 54 MHz (at a 12-bit level)

BSL at 74 MHz (at an 11-bit level)

BSL at 110 MHz (at a 10-bit level)

BSL at 150 MHz (at an 8-bit level)

At 27 MHz (at a 12-bit level)

At 54 MHz (at a 12-bit level)

At 74 MHz (at an 11-bit level)

At 110 MHz (at a 10-bit level)

At 150 MHz (at an 8-bit level)

−1.0/+1.5

−1.5/+2.0

−1.4/+1.2

−0.8/+2.0

−2.0/+2.0

−0.6/+0.7

−0.6/+0.8

−0.9/+0.75

−0.5/+1.0

−0.7/+1.5

Differential Nonlinearity⁴

DNL

POWER REQUIREMENTS⁵

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

Analog Power Supply

Memory Interface Power Supply

DVDD

DVDDIO

PVDD

AVDD

DVDDIO_SDRAM

1.75

3.0

1.71

3.15

2.35

3.2

1.8

3.3

1.8

3.3

2.5

3.3

236

103

236

319

180

214

6

15

27

48

13

10

11

99

1.85

3.6

1.89

3.45

2.65

3.4

V

DDR

SDR

Digital Core Supply Current

I_DVDD

CVBS input sampling at 54 MHz

Graphics RGB sampling at 78 MHz

SCART RGB FB sampling at 54 MHz

525p input sampling at 54 MHz

Graphics RGB sampling at 135 MHz

1080p sampling at 148.5 MHz

CVBS input sampling at 54 MHz

Graphics RGB sampling at 78 MHz

Graphics RGB sampling at 135 MHz

1080p sampling at 148.5 MHz

CVBS input sampling at 54 MHz

Graphics RGB sampling at 78 MHz

Graphics RGB sampling at 135 MHz

1080p sampling at 148.5 MHz

CVBS input sampling at 54 MHz

SCART RGB FB sampling at 54 MHz

Graphics RGB sampling at 78 MHz

Graphics RGB sampling at 135 MHz

1080p sampling at 148.5 MHz

CVBS input sampling at 54 MHz

mA

ms

Digital I/O Supply Current

PLL Supply Current

I_DVDDIO

I_PVDD

Analog Supply Current

I_AVDD

269

263

286

288

17

Memory Interface Supply Current

Power-Down Current

Power-Up Time

I_VDDRAM

I_PWRDN

t_PWRUP

8

20

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Current

V_IH

V_IL

I_IN

2

V

µA

pF

0.8

10

15

Input Capacitance

C_IN

Rev. D | Page 4 of 36

Data Sheet

ADV7802

Parameter¹

Symbol

Test Conditions

Min

Typ

Max

Unit

DIGITAL OUTPUTS

Output High Voltage⁶

Output Low Voltage⁶

High Impedance Leakage Current

Output Capacitance

V_OH

V_OL

I_SOURCE= 0.4 mA

I_SINK= 3.2 mA

2.4

0.4

10

V

I_LEAK

C_OUT

μA

pF

20

¹Temperature range T_MINto T_MAX

.

²All ADC linearity tests performed with part configured for component video input.

³All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%.

⁴Maximum INL and DNL specifications obtained with part configured for component video input.

⁵Guaranteed by characterization.

⁶V_OHand V_OLlevels obtained using default drive strength.

Rev. D | Page 5 of 36

ADV7802

Data Sheet

VIDEO SPECIFICATIONS

AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.4 V to 2.6 V (DDR),

DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V, T_A= 0°C to 85°C, unless otherwise noted.

Table 2.

Parameter¹

Symbol

Test Conditions

Min

Typ

Max

Unit

NONLINEAR SPECIFICATIONS

Differential Phase

Differential Gain

Luma Nonlinearity

NOISE SPECIFICATIONS

SNR Unweighted

DP

DG

LNL

CVBS input (modulated five-step)

0.45

0.7

Degrees

%

Luma ramp

Luma flat field

63

64

60

dB

Analog Front-End Crosstalk

LOCK TIME SPECIFICATIONS (SDP)

Horizontal Lock Range

Vertical Lock Range

5

%

Hz

40

70

Subcarrier Lock Range, f_SC

Color Lock-In Time

0.8

60

kHz

Lines

%

Sync Depth Range²

20

1

200

Color Burst Range

%

Vertical Lock Time

Horizontal Lock Time

300

100

ms

Lines

CHROMA SPECIFICATIONS (SDP)

Chroma Amplitude Error

Chroma Phase Error

0.4

0.3

0.2

%

Degrees

%

Chroma Luma Intermodulation

¹Guaranteed by characterization.

²Nominal sync depth is 300 mV at 100% sync depth range.

Rev. D | Page 6 of 36

Data Sheet

ADV7802

TIMING CHARACTERISTICS

AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.4 V to 2.6 V (DDR),

DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V, T_A= 0°C to 85°C, unless otherwise noted.

Table 3.

Parameter¹

Symbol

Test Conditions

Min

Typ

Max

Unit

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency

Crystal Frequency Stability

Horizontal Sync Input Frequency

LLC Frequency Range

28.63636

MHz

ppm

kHz

50

90

150

14.8

12.825

MHz

I²C PORT

SCLK Frequency

400

kHz

µs

ns

µs

SCLK Minimum Pulse Width High

SCLK Minimum Pulse Width Low

Hold Time (Start Condition)

Setup Time (Start Condition)

SDA Setup Time

SCLK and SDA Rise Time

SCLK and SDA Fall Time

Setup Time (Stop Condition)

FAST I²C PORT²

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

0.6

1.3

0.6

100

300

0.6

SCLK Frequency

3.4

MHz

ns

SCLK Minimum Pulse Width High

SCLK Minimum Pulse Width Low

Hold Time (Start Condition)

Setup Time (Start Condition)

SDA Setup Time

SCLK and SDA Rise Time

SCLK and SDA Fall Time

Setup Time (Stop Condition)

RESET FEATURE

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

60

160

10

80

160

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC Mark Space Ratio

t₉, t₁₀

45:55

55:45

% duty cycle

PIXEL PORT DATA AND CONTROL OUTPUTS³

Data Output Transition Time, SDR

t₁₁

t₁₂

t₁₃

t₁₄

Negative clock edge to start of

valid data

End of valid data to negative

clock edge

Negative clock edge to start of

valid data

End of valid data to negative

clock edge

4.5

0

ns

Data Output Transition Time, SDR

Data Output Transition Time, SDR (CP Core)

2.5

0.2

DATA AND CONTROL INPUTS⁴

Input Setup Time (Digital Input Port)

t₁₇

t₁₈

HS_IN1, VS_IN1, HS_IN2, VS_IN2

DE_IN, data inputs

HS_IN1, VS_IN1, HS_IN2, VS_IN2

DE_IN, data inputs

9.5

2

−4

0.8

ns

Input Hold Time (Digital Input Port)

¹Guaranteed by characterization.

²With a bus line load less than 100 pF.

³Timing figures obtained using default drive strength value.

⁴TTL input values are 0 V to 3 V, with rise/fall times ≥ 3 ns, measured between the 10% and 90% points.

Rev. D | Page 7 of 36

ADV7802

Data Sheet

TIMING DIAGRAMS

t₃

t₅

t₃

SDA1/SDA2

t₆

t₁

SCLK1/SCLK2

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₉

t₁₀

LLC

t₁₁

t₁₂

P0 TO P53, VS_OUT,

HS_OUT, FLD_DE_OUT

Figure 4. Pixel Port and Control SDR Output Timing (SD Core)

t₉

t₁₀

LLC

t₁₃

t₁₄

P0 TO P53, VS_OUT,

HS_OUT, FLD_DE_OUT

Figure 5. Pixel Port and Control SDR Output Timing (CP Core)

CLKIN

t₁₈

HS_IN1,

VS_IN1,

HS_IN2,

VS_IN2,

DE_IN

CONTROL

INPUTS

P30 TO P39,

P40 TO P43,

P44 TO P53

t₁₇

Figure 6. Digital Input Port and Control Input Timing

Rev. D | Page 8 of 36

Data Sheet

ADV7802

ANALOG SPECIFICATIONS

AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.4 V to 2.6 V (DDR),

DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V, T_A= 0°C to 85°C, unless otherwise noted. Recommended analog

input video signal range is 0.5 V to 1.6 V, typically 1 V p-p. Recommended external clamp capacitor value is 0.1 μF.

Table 4.

Parameter^{1, 2}

Test Conditions

Min

Typ

Max

Unit

CLAMP CIRCUITRY

Input Impedance³

Input Impedance of Pin 90 (FB)

CML

Clamps switched off

10

20

2.0

MΩ

kΩ

V

ADC Full-Scale Level

ADC Zero-Scale Level

ADC Dynamic Range

Clamp Level (When Locked)

CML + 0.8

CML − 0.8

1.6

V

mA

µA

CVBS input

CML − 0.292

CML − 0.3

CML − 0.292

CML − 0

CML − 0.3

CML − 0

CML − 0.3

0.75

SCART RGB input (R, G, B signals)

S-Video input (Y signal)

S-Video input (C signal)

Component input (Y signal)

Component input (Pr, Pb signals)

PC RGB input (R, G, B signals)

SDP only

Large Clamp Source Current

Large Clamp Sink Current

Fine Clamp Source Current

Fine Clamp Sink Current

0.9

17

¹The minimum/maximum specifications are guaranteed over 0°C to 85°C.

²Guaranteed by characterization.

³Except Pin 90 (FB).

Rev. D | Page 9 of 36

ADV7802

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the part, the user is

advised to turn off any unused ADCs.

Parameter

Rating

4.0 V

2.2 V

4.0 V

2.7 V

AVDD to AGND

DVDD to DGND

The junction temperature must always stay below the

maximum junction temperature (T_{J MAX}) of 125°C. The

following equation shows how to calculate the junction

temperature:

PVDD to AGND

DVDDIO to DGND

DVDDIO_SDRAM to

DGND_SDRAM (DDR)

DVDDIO_SDRAM to

DGND_SDRAM (SDR)

4.0 V

T_J= T_{A MAX}+ (θ_JA× W_MAX

where:

_{A MAX}= 85°C.

θ_JA= 21.0330°C/W.

W_MAX= ((AVDD × I_AVDD) + (DVDD × I_DVDD) + (DVDDIO ×

I_DVDDIO) + (PVDD × I_PVDD) + (DVDDIO_SDRAM ×

)

DVDDIO to AVDD

−0.3 V to +0.3 V

T

DVDDIO to DVDD

−0.3 V to +2 V

DVDDIO_SDRAM to DVDD (DDR)

DVDDIO_SDRAM to DVDD (SDR)

AVDD to PVDD

−0.3 V to +2.5 V

−0.3 V to +3.3 V

−0.3 V to +2 V

AVDD to DVDD

−0.3 V to +2 V

DVDDIO_SDRAM)).

DVDDIO to DVDDIO_SDRAM (DDR)

DVDDIO to DVDDIO_SDRAM (SDR)

AVDD to DVDDIO_SDRAM (DDR)

AVDD to DVDDIO_SDRAM (SDR)

Digital Inputs Voltage to DGND

DVDDIO_SDRAM Inputs to

DGND_SDRAM

−0.3 V to +2 V

THERMAL RESISTANCE

−0.3 V to +3.3 V

−0.3 V to +2.5 V

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

−0.3 V to +1.8 V

DGND − 0.3 V to DVDDIO + 0.3 V

DGND_SDRAM − 0.3 V to

DVDDIO_SDRAM + 0.3 V

AGND − 0.3 V to AVDD + 0.3 V

DVDDIO − 0.3 V to DVDDIO + 3.6 V

125°C

Table 6. Thermal Resistance

Package Type

1

2

θ_JA

θ_JC

Unit

Analog Inputs to AGND

SCLK/SDA Data Pins to DVDDIO

Maximum Junction Temperature

176-Lead LQFP

21

7

°C/W

¹4-layer PCB with solid ground plane.

²4-layer PCB with solid ground plane (still air).

(T_{J MAX}

)

Storage Temperature Range

−65°C to +150°C

260°C

Infrared Reflow Soldering (20 sec)

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. D | Page 10 of 36

Data Sheet

ADV7802

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

P13

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

P48

P49

P50

P51

P52

P53

DE_IN

VS_IN1

VS_IN2

INT

SCLK

SDA

ALSB

HS_IN2

HS_IN1

FUNCT1

AOUT

AIN6

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P0

DVDDIO

DGND

LLC

CS/HS_OUT

SFL/SYNC_OUT

FLD_DE_OUT

VS_OUT

DGND

AIN12

AIN5

AIN11

AIN4

ADV7802

TOP VIEW

(Not to Scale)

DVDD

AIN10

CAPC2

CAPC1

CAPY1

BIAS

AVDD

AGND

CML

REFOUT

AVDD

AGND

AIN3

AIN9

AIN2

AIN8

AIN1

AIN7

SOG

SOY

FB

SDRAM_A11

SDRAM_A9

SDRAM_A8

SDRAM_A7

SDRAM_A6

SDRAM_A5

SDRAM_A4

SDRAM_A3

SDRAM_A2

SDRAM_A1

SDRAM_A0

DGND

98

97

DVDD

96

DVDDIO_SDRAM

DGND_SDRAM

SDRAM_A10

SDRAM_BA1

SDRAM_BA0

SDRAM_CS

SDRAM_RAS

SDRAM_CAS

95

94

93

92

91

90

89

AGND

Figure 7. Pin Configuration

Rev. D | Page 11 of 36

ADV7802

Data Sheet

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type¹Description

1 to 14, 155 to 158, 161 to

169, 172 to 174

P0 to P29

O

Video Pixel Output Port. See Figure 7 for details on pin mapping.

15, 79, 143, 170

16, 22, 35, 59, 77, 82, 138,

144, 160, 171, 176

DVDDIO

DGND

P

GND

Digital Input/Output Supply Voltage (3.3 V).

Digital Ground.

17

18

LLC

CS/HS_OUT

O

Line-Locked Output Clock for the Pixel Data.

Horizontal Synchronization or Composite Synchronization Signal. This signal

can be selected while in SDP mode.

19

SFL/SYNC_OUT

FLD_DE_OUT

O

Subcarrier Frequency Lock. This pin contains a serial output stream, which

can be used to lock the subcarrier frequency when this decoder is connected

to any digital video encoder from Analog Devices, Inc. SYNC_OUT is the

sliced synchronization output signal available only in CP mode.

Field Synchronization Output Signal (All Interlaced Video Modes). This pin

also can be enabled as a data enable signal (DE) to allow direct connection to

an HDMI™/DVI Tx IC.

20

O

21

VS_OUT

DVDD

SDRAM_A0 to

SDRAM_A11

O

P

O

Vertical Synchronization Output Signal (SDP and CP Modes).

Digital Core Supply Voltage (1.8 V).

Address Outputs. Interface to external RAM address lines. See Figure 7 for

details on pin mapping.

23, 36, 60, 76, 137, 159, 175

24 to 34, 39

37, 47, 61

38, 48, 62

40, 41

DVDDIO_SDRAM

DGND_SDRAM

SDRAM_BA1 to

SDRAM_BA0

P

GND

O

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

External Memory Interface Digital GND.

Bank Address Outputs. Interface to external RAM bank address lines.

42

SDRAM_CS

SDRAM_RAS

SDRAM_CAS

SDRAM_WE

O

Chip Select. SDRAM_CS enables and disables the command decoder on

the RAM.

Row Address Select Command Signal. SDRAM_RAS, SDRAM_CAS,

SDRAM_WE, and SDRAM_CS define the command to the RAM.

43

44

Column Address Select Command Signal. SDRAM_RAS, SDRAM_CAS,

SDRAM_WE, and SDRAM_CS define the command to the RAM.

45

Write Enable Output Command Signal. SDRAM_RAS, SDRAM_CAS,

SDRAM_WE, and SDRAM_CS define the command to the RAM.

46, 72

SDRAM_LDM,

SDRAM_UDM

Data Mask Output. Data is masked when DM is high, for writing data to the

external RAM. LDM corresponds to the data on SDRAM_DQ0 to

SDRAM_DQ7, and UDM corresponds to the data on SDRAM_DQ8 to

SDRAM_DQ15.

49

SDRAM_LDQS

I/O

Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This

is an output with read data and an input with write data. It is edge aligned

with write data and centered in read data. SDRAM_ LDQS corresponds to the

data on SDRAM_DQ0 to SDRAM_DQ7.

Data Bus. Interface to external RAM 16-bit data bus. See Figure 7 for details

on pin mapping.

50 to 57, 63 to 70

SDRAM_DQ0 to

SDRAM_DQ15

58

71

SDRAM_VREF

SDRAM_UDQS

P

I/O

1.25 V reference for the DDR SDRAM interface or 1.65 V for SDR.

Upper Data Strobe Pin. Data strobe pins for the RAM interface. This is an

output with read data and an input with write data. It is edge aligned with

write data and centered in read data. SDRAM_UDQS corresponds to the data

on SDRAM_DQ8 to SDRAM_DQ16.

73, 74

SDRAM_CK,

SDRAM_CK

O

Differential Clock Output. All address and control output signals to the RAM

should be sampled on the positive edge of SDRAM_CK and on the negative

edge of SDRAM_CK.

75

78

SDRAM_CKE

CLKIN

O

I

Clock Enable. This pin is used as an enable to the clock signals of the

external RAM.

Clock Input Signal. Used in 24-bit digital input mode (for example, processing

24-bit RGB data from a DVI/HDMI Rx IC and also in digital CVBS input mode).

80

81

XTAL

XTAL1

I

O

Crystal Input. Input pin for 28.63636 MHz crystal.

Crystal Output. This pin should be connected to the 28.63636 MHz crystal.

Rev. D | Page 12 of 36

Data Sheet

ADV7802

Pin No.

Mnemonic

Type¹Description

83

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is

required to reset the ADV7802 circuitry.

84, 87

85, 89, 99, 100, 104

86, 88

PVDD

AGND

ELPF1, ELPF2

P

GND

I

PLL Supply Voltage (1.8 V).

Analog Ground.

External Loop Filter. The recommend external loop filter must be connected

to each ELPF pin (see Figure 8).

90

FB

I

SCART Fast Blank Input.

91

92

SOY

SOG

AIN1 to AIN12

AVDD

REFOUT

CML

I

P

O

Sync On Luma Input. Used in embedded synchronization mode.

Sync On Green Input. Used in embedded synchronization mode.

Analog Video Input Channels. See Figure 7 for details on pin mapping.

Analog Supply Voltage (3.3 V).

Internal Voltage Reference Output.

Common-Mode Level Pin Used for the Internal ADCs.

93 to 98, 110 to 115

101, 105

102

103

106

BIAS

External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ)

between the pin and ground.

107

108, 109

116

117

118

CAPY1

CAPC1, CAPC2

AOUT

FUNCT1

HS_IN1

I

O

I

ADC Capacitor Network.

Analog Monitor Output.

SCART Function Select Input.

Horizontal Synchronization Input Signal. Used in CP mode for 5-wire

timing mode.

119

120

HS_IN2

I/O

I

Horizontal Synchronization Input Signal. Used in 24-bit digital input mode

port mode (for example, processing 24-bit RGB data from an HDMI Rx IC).

HS_IN2 in conjunction with VS_IN2 can be configured as a fast I²C interface

for teletext data extraction. HS_IN2 is used as the I²C port serial clock input.

ALSB selects the I²C address for the ADV7802 control. ALSB set to Logic 0

configures the address for a write to the input/output port of 0x40. ALSB

set to Logic 1 configures the address for a write to the input/output

port of 0x42.

I²C Port Serial Data Input/Output Pin.

I²C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).

Interrupt Output. This pin can be active low or active high. When SDP/CP

status bits change, this pin triggers. The set of events that triggers an

interrupt is under user control.

ALSB

121

122

123

SDA

SCLK

INT

I/O

I

O

124

VS_IN2

I/O

Vertical Synchronization Input Signal. Used in 24-bit digital input port mode

(for example, processing 24-bit RGB data from an DVI/HDMI Rx IC). VS_IN2 in

conjunction with HS_IN2 can be configured as a fast I²C interface for teletext

data extraction. VS_IN2 is used as the I²C port serial data input/output pins.

125

126

VS_IN1

I

Vertical Synchronization Input Signal. Used in CP mode for 5-wire

timing mode.

Data Enable Input Signal. Used in 24-bit digital input port mode (for example,

processing 24-bit RGB data from an DVI/HDMI Rx IC).

DE_IN

I

127 to 136, 139 to 142, 145

to 154

P30 to P53

I/O

Video Pixel Input/Output Port. See Figure 7 for details on pin mapping.

¹GND = ground, I = input, I/O = input/output, O = output, P = power.

Rev. D | Page 13 of 36

ADV7802

Data Sheet

THEORY OF OPERATION

KEY FEATURES

Analog front-end features include

•

Four 150 MHz, NSV, 12-bit ADCs that enable true 12-bit

video decoding

The ADV7802 is a high quality, single-chip, multiformat 3D

comb filter video decoder and graphics digitizer. Key features

of the device include

12-channel analog input mux that enables multiple source

connections without the requirement of an external mux

•

Four noise shaped video (NSV®) 12-bit ADCs

NTSC/PAL/SECAM video decoder

Four current and voltage clamp control loops that ensure

that any dc offsets are removed from the video signal

Adaptive 3D comb filtering

SCART functionality and SD RGB overlay on CVBS

controlled by fast blank input

3D digital noise reduction

Advanced frame time-base correction (TBC)

Composite, S-Video, YPrPb/RGB SCART support

YPrPb component HD and RGB graphics input support

•

SCART source switching detection through FUNCT1 input

Four programmable antialias filters on standard definition

video signals and enhance definition

•

CVBS monitor output

36-bit digital YPrPb/RGB output supporting 12-bit

deep color

STANDARD DEFINITION PROCESSOR

ANALOG FRONT END

The standard definition processor (SDP) is capable of decoding

a large selection of baseband video signals in composite, S-Video,

and YUV formats. The video standards supported by the SDP

include PAL, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J,

NTSC 4.43, and SECAM. The ADV7802 can automatically

detect the video standard and process it accordingly. The

ADV7802 can process video up to 525p/625p formats.

The ADV7802 analog front end comprises four 12-bit NSV

ADCs that digitize the analog video signal before applying it

to the SDP or CP.

The front end includes a 12-channel input mux that enables

multiple video signals to be applied to the ADV7802 without

the requirement of an external mux. Current and voltage clamps

are positioned in front of each ADC to ensure that the video

signal remains within the range of the converter.

The SDP has a 3D temporal comb filter and a five-line super

adaptive 2D comb filter that gives superior chrominance and

luminance separation when decoding a composite video signal.

This highly adaptive filter automatically adjusts its processing

mode according to the video standard and signal quality with

no user intervention required. The SDP has an IF filter block

that compensates for attenuation in the high frequency chroma

spectrum due to a tuner SAW filter. The SDP has specific lumi-

nance and chrominance parameter controls for brightness,

contrast, saturation, and hue.

The ADCs are configured to run up to 4× oversampling mode

when decoding composite and S-Video inputs or components

up to 525i and 625i. For 525p and 625p, 2× oversampling is

available. All other video standards are 1× oversampled. In

oversampling the video signals, a reduction in the cost and

complexity of external antialiasing filters can be obtained with

the benefit of an increased signal-to-noise ratio (SNR).

Optional internal antialiasing filters with programmable

bandwidth are positioned in front of each ADC. These filters

can be used to band-limit standard definition (SD) video

signals, removing spurious, out-of-band noise.

The ADV7802 implements a patented adaptive digital line

length tracking (ADLLT) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7802 to track and decode poor quality video sources (such

as VCRs) and noisy sources (such as tuner outputs, VCR

players, and camcorders). Frame TBC ensures stable clock

synchronization between the decoder and the downstream

devices.

The ADV7802 can support simultaneous processing of

CVBS and RGB standard definition signals to enable SCART

compatibility and overlay functionality. A combination of

CVBS and RGB inputs can be mixed, and the output is under

the control of I²C registers and the fast blank pin.

The SDP also contains both a luma transient improvement

(LTI) and a chroma transient improvement (CTI) processor.

This processor increases the edge rate on the luma and chroma

transitions, resulting in a sharper video image.

Rev. D | Page 14 of 36

Data Sheet

ADV7802

The SDP has a Macrovision® detection circuit, which allows

Type I, Type II, and Type III Macrovision protection levels. The

decoder is also fully robust to all Macrovision signal inputs.

VBI DATA PROCESSOR

The VBI data processor (VDP) of the ADV7802 is capable of

slicing multiple vertical blanking interval data standards on SD

video and component video. The VDP decodes the VBI data on

the incoming CVBS/YC or YUV data processed by the SDP core.

It can also decode VBI data on the luma channel of YUV data

processed through the CP core.

SDP features include

•

Advanced adaptive 3D comb with concurrent 3D noise

reduction (using external DDR SDRAM memory)

•

Adaptive 2D five-line comb filters for NTSC and PAL that

give superior chrominance and luminance separation for

composite video

The VDP can process a variety of VBI data standards, such as

•

Teletext

Video programming system (VPS)

Vertical interval time codes (VITC)

Closed captioning (CC) and extended data service (EDS)

Wide screen signaling (WSS)

•

Full automatic detection and autoswitching of all

worldwide standards (PAL, NTSC, and SECAM)

Automatic gain control with white peak mode that

ensures that the video is always processed without loss of

the video processing range

Copy generation management system (CGMS, CGMS

Type B)

•

Proprietary architecture for locking to weak, noisy, and

unstable sources from VCRs and tuners

•

Gemstar® 1×/2× electronic program guide compatible

IF filter block that compensates for high frequency luma

attenuation due to tuner SAW filter

Extended data service (SDS); the data extracted can be read

back over a fast I²C interface

•

LTI and CTI

COMPONENT PROCESSOR

Vertical and horizontal programmable luma peaking filters

The component processor (CP) is capable of decoding and digi-

tizing a wide range of component video formats in any color

space. The CP can accept video data from the analog front

end or from the HDMI receiver. Component video standards

supported by the CP include 525i, 625i, 525p, 625p, 720p, 1080i,

1080p, and VGA (up to SXGA at 75 Hz), and many other

standards.

True full 12-bit deep color processing path from front to

back end in 4:4:4/4:2:2 RGB/YCrCb formats

•

4× oversampling (54 MHz) for CVBS, S-Video, and

YUV modes

•

Line-locked clock output (LLC)

Free run output mode that provides stable timing when no

video input is present

A fully programmable any-to-any, 3 × 3 color space conversion

(CSC) matrix is placed before the CP. This enables YPrPb-to-

RGB and RGB-to-YCrCb conversions of video data coming

from the analog front end or from the HDMI receiver. Many

other standards of color space can be implemented using the

color space converter.

•

Internal color bar test pattern

Advanced TBC with frame synchronization, which ensures

nominal clock and data for nonstandard input

•

Interlace-to-progressive conversion for 525i and 625i

formats, enabling direct drive of HDMI Tx devices

The CP of the ADV7802 contains an automatic gain control

(AGC) block. The AGC is followed by a clamp circuit that

ensures that the video signal is clamped to the correct blanking

level. Automatic adjustments within the CP include gain

(contrast) and offset (brightness). Manual adjustment controls

are also supported. In cases where no embedded synchroni-

zation is preset, the video gain can be set manually.

Color controls that include hue, brightness, saturation,

and contrast

•

Differential gain (DG), typically 0.45%

Differential phase (DP), typically 0.45°

Rev. D | Page 15 of 36

ADV7802

Data Sheet

The CP contains circuitry to enable the detection of Macrovision

encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is

designed to be fully robust to these types of signals.

ADDITIONAL FEATURES

The ADV7802 also includes

•

HS, VS, FIELD, and DE output signals with programmable

position, polarity, and width

CP features include

•

525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other

HDTV formats supported

INT

•

Programmable interrupt request output pin (

signals SDP/CP status changes

) that

•

Automatic adjustments including gain (contrast) and

offset (brightness); manual adjustment controls are also

supported

•

Two I²C host port interface (control and VBI) support

Integrated programmable antialiasing filters

176-lead, 26 mm × 26 mm, RoHS-compliant LQFP

•

Support for analog component YPrPb and RGB video

formats with embedded synchronization or with separate

HS, VS, or CS

For more detailed product information about the ADV7802,

contact a local Analog Devices sales representative.

Any-to-any, 3 × 3 color space conversion matrix that

supports YCrCb-to-RGB and RGB-to-YCrCb, fully

programmable or preprogrammable configurations

SINGLE DATA RATE (SDR)

The ADV7802 uses SDR external memory¹for 3D comb, frame

synchronizer operation, or 3D-DNR nonconcurrent operation.

Synchronization source polarity detector (SSPD) that

determines the source and polarity of the synchronization

signals that accompany the input video

•

64 Mb SDR SDRAM minimum memory requirement.

The memory architecture required is four banks of

1 Mb × 16.

•

Macrovision copy protection detection on component

formats (525i, 625i, 525p, and 625p)

•

Speed grade of 133 MHz at CAS latency (CL) 3 is required.

22 Ω series termination resistors are recommended for this

configuration.

Free run output mode that provides stable timing when no

video input is present

•

Recommended memory that is compatible with the

ADV7802 includes the MT48LC4M16A2 from Micron.

Arbitrary pixel sampling support for nonstandard

video sources

DOUBLE DATA RATE (DDR)

135 MHz graphics processing, supporting RGB input

resolutions up to 1280 × 1024 at 75 Hz

The ADV7802 uses DDR external memory¹for simultaneous

3D comb, frame synchronizer, and 3D-DNR operation.

Automatic or manual clamp-and-gain controls for

graphics modes

•

128 Mb DDR SDRAM minimum memory requirement.

•

Contrast, brightness, hue, and saturation controls

The memory architecture required is four banks of

2 Mb × 16.

32-phase DLL that allows optimum pixel clock sampling

•

Speed grade of 133 MHz at CAS latency (CL) 2.5 is required.

Automatic detection of synchronization source and

polarity by SSPD block

Termination resistors not recommended for this

configuration.

•

Standard identification enabled by STDI block

•

Recommended memory that is compatible with the

ADV7802 includes K4H281638B-TCB0 from Samsung,

the MT46V8M16-TGP-75 from Micron, and the

HYB25D128160CE-6 from Infineon.

RGB that can be color space converted to YCrCb and

decimated to a 4:2:2 format for videocentric back-end IC

interfacing

•

Data enable (DE) output signal supplied for direct

connection to HDMI/DVI Tx IC

¹When external memory is not connected, IO Map Register 0x29[4] should be

set high directly after reset.

Arbitrary pixel sampling support for nonstandard video

sources

Rev. D | Page 16 of 36

Data Sheet

ADV7802

RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS

The external loop filter components for the ELPF pins should be placed as close as possible to the respective pins. Figure 8 shows the

recommended component values.

PIN 86 (ELPF1)

PIN 88 (ELPF2)

1.69kΩ

10nF

160Ω

39nF

82nF

820nF

PVDD = 1.8V

Figure 8. ELPF Components

Rev. D | Page 17 of 36

ADV7802

Data Sheet

TYPICAL CONNECTION DIAGRAMS

ADV7802

Figure 9. Typical Connection Diagram (External DDR Memory)

Rev. D | Page 18 of 36

Data Sheet

ADV7802

Figure 10. Typical Connection Diagram (External SDR Memory)

Rev. D | Page 19 of 36

ADV7802

Data Sheet

U2

ADV7802

Figure 11. Typical Connection Diagram (No External Memory)

Rev. D | Page 20 of 36

Data Sheet

ADV7802

PIXEL INPUT/OUTPUT FORMATTING

There are several modes in which the ADV7802 pixel port

can be configured. These modes are under the I²C control of

OP_FORMAT_SEL[5:0].

•

DDR 12-/24-/30-/36-bit 4:4:4 RGB for all standards

48-bit 4:4:4 RGB dual-pin mode

Simultaneous output modes 16-/20-/24-bit YCrCb and

8-/10-/12-bit 4:2:2 YCrCb up to 525i/525p and 625i/625p

PIXEL DATA OUTPUT MODES HIGHLIGHTS

The ADV7802 has a flexible pixel port, which can be configured

in a variety of formats to accommodate downstream ICs. See

Table 8 and Table 9 for more information on each mode. The

output pixel port features include

DIGITAL VIDEO INPUT PORT HIGHLIGHTS

The ADV7802 contains a 24-bit digital input port. The main

features are as follows:

•

Support for 24-bit RGB input data from the DVI/HDMI

Rx IC, pass-through, or output converted to 4:2:2 YCrCb

•

8-/10-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded

time codes and/or HS_OUT, VS_OUT, and FLD_DE_OUT

pin timing

•

Support for 24-bit 4:4:4, 16-/20-bit 4:2:2 525i, 625i, 525p,

625p, 720p, 1080i, 1080p, and VGA to SXGA at 75 Hz

input data from the DVI/HDMI Rx IC chip, pass-through,

or output converted to 4:2:2 YCrCb

•

16-/20-/24-bit YCrCb with embedded time codes and/or

HS_OUT, VS_OUT, and FLD_DE_OUT pin timing

24-/30-/36-/48-bit YCrCb/RGB with embedded time codes

and/or HS_OUT, VS_OUT, and FLD_DE_OUT pin timing

•

Dedicated synchronization and pixel port inputs

DDR 8-/10-/12-bit 4:2:2 YCrCb for all standards

Rev. D | Page 21 of 36

ADV7802

Data Sheet

Table 8. SDR Pixel Port Output Modes^{1, 2}

OP_FORMAT_SEL

[5:0]

0x00

8-Bit

0x01

0x02

0x03

0x04

0x05

0x06

0x07

SDR

ITU-656

Mode 1

10-Bit SDR

ITU-656

Mode 1

12-Bit SDR

ITU-656

Mode 1

12-Bit SDR

ITU-656

Mode 2

12-Bit SDR

ITU-656

Mode 3

16-Bit SDR

ITU-656 4:2:2

Mode 1

20-Bit SDR

ITU-656 4:2:2

Mode 1

24-Bit SDR

ITU-656 4:2:2

Mode 1

Pixel Output

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

Y7, Cb7,

Cr7

Y6, Cb6,

Cr6

Y5, Cb5,

Cr5

Y4, Cb4,

Cr4

Y3, Cb3,

Cr3

Y2, Cb2,

Cr2

Y1, Cb1,

Cr1

Y0, Cb0,

Cr0

Y9, Cb9, Cr9 Y11, Cb11,

Cr11

Y8, Cb8, Cr8 Y10, Cb10,

Cr10

Y11, Cb11,

Cr11

Y10, Cb10,

Cr10

Y11, Cb11,

Cr11

Y10, Cb10,

Cr10

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y11

Y10

Y9

P28

P27

P26

P25

P24

P23

P22

Y7, Cb7, Cr7 Y9, Cb9, Cr9

Y6, Cb6, Cr6 Y8, Cb8, Cr8

Y5, Cb5, Cr5 Y7, Cb7, Cr7

Y4, Cb4, Cr4 Y6, Cb6, Cr6

Y3, Cb3, Cr3 Y5, Cb5, Cr5

Y2, Cb2, Cr2 Y4, Cb4, Cr4

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Y6, Cb6, Cr6

Y5, Cb5, Cr5

Y4, Cb4, Cr4

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Y6, Cb6, Cr6

Y5, Cb5, Cr5

Y4, Cb4, Cr4

Y8

Y7

Y6

Y5

Y4

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

Z

Y1, Cb1, Cr1 Y3, Cb3, Cr3

Y0, Cb0, Cr0 Y2, Cb2, Cr2

Z

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Z

Y1

Y0

Y3

Y2

Z

Y1, Cb1, Cr1

Y0, Cb0, Cr0

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

Z

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

Z

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Z

Rev. D | Page 22 of 36

Data Sheet

ADV7802

OP_FORMAT_SEL

[5:0]

0x00

8-Bit

0x01

0x02

0x03

0x04

0x05

0x06

0x07

SDR

ITU-656

Mode 1

10-Bit SDR

ITU-656

Mode 1

12-Bit SDR

ITU-656

Mode 1

12-Bit SDR

ITU-656

Mode 2

12-Bit SDR

ITU-656

Mode 3

16-Bit SDR

ITU-656 4:2:2

Mode 1

20-Bit SDR

ITU-656 4:2:2

Mode 1

24-Bit SDR

ITU-656 4:2:2

Mode 1

Pixel Output

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

Z

Y1

Y0

Z

Cb1, Cr1

Cb0, Cr0

Z

Y1, Cb1, Cr1

Y0, Cb0, Cr0

Z

¹It is recommended to print this table (located on this page and the following two pages) and read as one horizontal expanded table.

²Blank cells are not populated areas.

Rev. D | Page 23 of 36

ADV7802

Data Sheet

OP_FORMAT_SEL

[5:0]

0x08

0x09

0x0A

0x2C

0x2D

0x2E

0x0B

0x0C

0x0D

24-Bit

SDR

4:4:4

24-Bit

SDR

4:4:4

30-Bit

SDR

4:4:4

24-Bit SDR

ITU-656 4:2:2

Mode 2

24-Bit SDR

ITU-656 4:2:2

Mode 3

24-Bit SDR

4:4:4

Mode 2

24-Bit SDR

4:4:4

Mode 1

36-Bit SDR

4:4:4

Mode 1

36-Bit SDR

4:4:4

Mode 2

Mode 3

Mode 1

Pixel Output

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

Mode 1

G1

G0

Z

G3

G2

G1

G0

Z

B1

B0

Z

R1

R0

Z

B3

B2

B1

B0

Z

R3

R2

R1

R0

Z

Y11

Y10

Y9

Y8

Y7

Y6

Y5

Y4

Y11

Y10

Y9

Y8

Y7

Y6

Y5

Y4

G7

G6

G5

G4

G3

G2

G1

G0

Z

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

R7

R6

R5

R4

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B7

B6

B5

B4

B3

B2

B1

B0

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G9

G8

G7

G6

G5

G4

G3

G2

G1

G0

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

G11

G10

G9

G8

G7

G6

G5

G4

G3

G2

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

G11

G10

G9

G8

G7

G6

G5

G4

Z

Y3

Y2

Z

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Z

B7

B6

B5

B4

B3

B2

B1

B0

Z

B11

B10

B9

B8

B7

B6

B5

B4

Z

Rev. D | Page 24 of 36

Data Sheet

ADV7802

OP_FORMAT_SEL

[5:0]

0x08

0x09

0x0A

0x2C

0x2D

0x2E

0x0B

0x0C

0x0D

24-Bit

SDR

4:4:4

24-Bit

SDR

4:4:4

30-Bit

SDR

4:4:4

24-Bit SDR

ITU-656 4:2:2

Mode 2

24-Bit SDR

ITU-656 4:2:2

Mode 3

24-Bit SDR

4:4:4

Mode 2

24-Bit SDR

4:4:4

Mode 1

36-Bit SDR

4:4:4

Mode 1

36-Bit SDR

4:4:4

Mode 2

Pixel Output

Mode 1

Mode 3

Mode 1

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

Z

Y3

Y1

Y0

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

Z

R7

R6

R5

R4

R3

R2

R1

R0

Z

R3

R2

R1

R0

Z

B3

B2

B1

B0

Z

G3

G2

G1

G0

Z

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R11

R10

R9

R8

R7

R6

R5

R4

Z

Cb1, Cr1

Cb0, Cr0

Z

Y1

Y0

Z

Rev. D | Page 25 of 36

ADV7802

Data Sheet

OP_FORMAT_SEL

[5:0]

0x28

0x29

0x2A

0x2B

0x0E

0x0F

16-Bit and 8-Bit

SDR 4:2:2 Mode 1

Parallel Output

20-Bit and 10-Bit

SDR 4:2:2 Mode 1

Parallel Output

24-Bit and 12-Bit

SDR 4:2:2 Mode 1

Parallel Output

24-Bit and 12-Bit

SDR 4:2:2 Mode 2

Parallel Output

48-Bit Dual

Pin Mode 0

Pixel Output

48-Bit Dual Pin Mode 1

Clock Rise

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

Z

Clock Rise

Clock Fall

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

Main Y1

Main Y0

Z

Main Y3

Main Y2

Main Y1

Main Y0

Z

Main Cb1, Cr1

Main Cb0, Cr0

Main Cb3, Cr3

Main Cb2, Cr2

Z

Main Cb1, Cr1

Main Cb0, Cr0

Z

Aux Y3, Cb3, Cr3

Aux Y2, Cb2, Cr2

Aux Y1, Cb1, Cr1

Aux Y0, Cb0, Cr0

Z

Aux Y1, Cb1, Cr1

Aux Y0, Cb0, Cr0

Z

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Y1

Main Y0

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Y11

Main Y10

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Cb11, Cr11

Main Cb10, Cr10

Main Cb9, Cr9

Main Cb8, Cr8

Main Cb7, Cr7

Main Cb6, Cr6

Main Cb5, Cr5

Main Cb4, Cr4

Main Cb3, Cr3

Main Cb2, Cr2

Main Y11

Main Y10

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Z

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

Z

Main Y1

Main Y0

Z

Main Cb7, Cr7

Main Cb6, Cr6

Main Cb5, Cr5

Main Cb4, Cr4

Main Cb3, Cr3

Main Cb2, Cr2

Main Cb1, Cr1

Main Cb0, Cr0

Z

Main Cb9, Cr9

Main Cb8, Cr8

Main Cb7, Cr7

Main Cb6, Cr6

Main Cb5, Cr5

Main Cb4, Cr4

Main Cb3, Cr3

Main Cb2, Cr2

Main Cb1, Cr1

Main Cb0, Cr0

Main Cb11, Cr11

Main Cb10, Cr10

Main Cb9, Cr9

Main Cb8, Cr8

Main Cb7, Cr7

Main Cb6, Cr6

Main Cb5, Cr5

Main Cb4, Cr4

Z

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

Z

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

Z

Rev. D | Page 26 of 36

Data Sheet

ADV7802

OP_FORMAT_SEL

[5:0]

0x28

0x29

0x2A

0x2B

0x0E

0x0F

16-Bit and 8-Bit

SDR 4:2:2 Mode 1

Parallel Output

20-Bit and 10-Bit

SDR 4:2:2 Mode 1

Parallel Output

24-Bit and 12-Bit

SDR 4:2:2 Mode 1

Parallel Output

24-Bit and 12-Bit

SDR 4:2:2 Mode 2

Parallel Output

48-Bit Dual

Pin Mode 0

Pixel Output

48-Bit Dual Pin Mode 1

P9

Aux Y7, Cb7, Cr7

Aux Y9, Cb9, Cr9

Aux Y11, Cb11,

Cr11

Aux Y11, Cb11, Cr11 R7-0

R7-0

P8

Aux Y6, Cb6, Cr6

Aux Y8, Cb8, Cr8

Aux Y10, Cb10,

Cr10

Aux Y10, Cb10, Cr10 R6-0

R6-0

P7

P6

P5

P4

P3

P2

P1

P0

Aux Y5, Cb5, Cr5

Aux Y4, Cb4, Cr4

Aux Y3, Cb3, Cr3

Aux Y2, Cb2, Cr2

Aux Y1, Cb1, Cr1

Aux Y0, Cb0, Cr0

Z

Aux Y7, Cb7, Cr7

Aux Y6, Cb6, Cr6

Aux Y5, Cb5, Cr5

Aux Y4, Cb4, Cr4

Aux Y3, Cb3, Cr3

Aux Y2, Cb2, Cr2

Aux Y1, Cb1, Cr1

Aux Y0, Cb0, Cr0

Aux Y9, Cb9, Cr9

Aux Y8, Cb8, Cr8

Aux Y7, Cb7, Cr7

Aux Y6, Cb6, Cr6

Aux Y5, Cb5, Cr5

Aux Y4, Cb4, Cr4

Aux Y3, Cb3, Cr3

Aux Y2, Cb2, Cr2

Aux Y9, Cb9, Cr9

Aux Y8, Cb8, Cr8

Aux Y7, Cb7, Cr7

Aux Y6, Cb6, Cr6

Aux Y5, Cb5, Cr5

Aux Y4, Cb4, Cr4

Z

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

Z

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

Z

Rev. D | Page 27 of 36

ADV7802

Data Sheet

Table 9. DDR Pixel Port Output Modes^{1, 2}

OP_FORMAT_SEL

[5:0]

0x10

0x11

0x12

0x13

0x14

12-Bit DDR YCrCb

4:2:2 Mode 1

12-Bit DDR YCrCb

4:2:2 Mode 2

12-Bit DDR YCrCb

4:2:2 Mode 3

8-Bit DDR ITU-656

10-Bit DDR ITU-656

Pixel Output

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

Clock Rise Clock Fall

Clock Rise Clock Fall Clock Rise

Clock Fall Clock Rise Clock Fall

Clock Rise

Clock Fall

Cb7, Cr7

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Z

Cb9, Cr9

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Z

Cb11, Cr11 Y11

Cb10, Cr10 Y10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Z

Y11

Y10

Y9

Y8

Y7

Y6

Y5

Y4

Z

Cb11, Cr11 Y11

Cb10, Cr10 Y10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

Z

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Z

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Z

Cb0, Cr0

Cb2, Cr2

Z

Cb2, Cr2

Z

Cb1, Cr1

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

Z

Y3

Y2

Y1

Y0

Z

Cb0, Cr0

Z

Rev. D | Page 28 of 36

Data Sheet

ADV7802

OP_FORMAT_SEL

[5:0]

0x10

0x11

0x12

0x13

0x14

12-Bit DDR YCrCb

4:2:2 Mode 1

12-Bit DDR YCrCb

4:2:2 Mode 2

12-Bit DDR YCrCb

4:2:2 Mode 3

8-Bit DDR ITU-656

10-Bit DDR ITU-656

Pixel Output

Clock Rise Clock Fall

Clock Rise Clock Fall Clock Rise

Clock Fall Clock Rise Clock Fall

Clock Rise

Clock Fall

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

Z

Y1

Y0

Z

Cb1, Cr1

Cb0, Cr0

Z

¹It is recommended to print this table (located on this page and the following three pages) and read as one horizontal expanded table.

²Blank cells are not populated areas.

Rev. D | Page 29 of 36

ADV7802

Data Sheet

OP_FORMAT_SEL

[5:0]

0x15

0x1A

0x1B

0x1C

36-Bit DDR RGB (CLK/2) Mode 1

12-Bit DDR RGB 4:4:4

24-Bit DDR RGB (CLK/2)

30-Bit DDR RGB (CLK/2)

Pixel Output

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

P9

Clock Rise

Clock Fall

Clock Rise

Clock Fall

Clock Rise

Clock Fall

Clock Rise

G1-0

G0-0

Z

B1-0

B0-0

Z

R1-0

R0-0

Z

Clock Fall

G1-1

G0-1

Z

B1-1

B0-1

Z

R1-1

R0-1

Z

B7

B6

B5

B4

B3

B2

B1

B0

Z

R3

R2

R1

R0

G7

G6

G5

G4

Z

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

Z

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

Z

G9-0

G8-0

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

B9-0

B8-0

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

R9-0

R8-0

R7-0

R6-0

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

G9-1

G8-1

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

B9-1

B8-1

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

R9-1

R8-1

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

G11-0

G10-0

G9-0

G8-0

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

B11-0

B10-0

B9-0

B8-0

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

R11-0

R10-0

R9-0

R8-0

R7-0

R6-0

R5-0

R4-0

R3-0

R2-0

G11-1

G10-1

G9-1

G8-1

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

B11-1

B10-1

B9-1

B8-1

B7-1

B6-1

B5-1

B4-1

B3-0

B2-1

R11-1

R10-1

R9-1

R8-1

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

Z

G3

G2

G1

G0

Z

R7

R6

R5

R4

Z

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

Z

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

Z

R7-0

R6-0

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

Z

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

Z

P8

P7

P6

P5

P4

P3

P2

P1

P0

Z

Rev. D | Page 30 of 36

Data Sheet

ADV7802

OP_FORMAT_SEL

[5:0]

0x1D

0x38

0x39

0x3A

16-Bit and 8-Bit DDR 4:2:2

36-Bit DDR RGB (CLK/2) Mode 1 Parallel Output

20-Bit and 10-Bit DDR 4:2:2

24-Bit and 12-Bit DDR 4:2:2

Mode 2

(CLK/2)

Mode 1 Parallel Output (CLK/2)

Pixel Output

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

P9

Clock Rise Clock Fall

Clock Rise

Clock Fall

Clock Rise

Clock Fall

Clock Rise

Main Y1

Main Y0

Z

Main Cb1

Main Cb0

Z

Aux Cb1, Cr1

Aux Cb0, Cr0

Z

Clock Fall

Main Y1

Main Y0

Z

Main Cr1

Main Cr0

Z

Aux Cr0

Z

G3-0

G2-0

G1-0

G0-0

Z

G3-1

G2-1

G1-1

G0-1

Z

B3-0

B2-0

B1-0

B0-0

Z

B3-1

B2-1

B1-1

B0-1

Z

R3-0

R2-0

R1-0

R0-0

Z

R3-1

R2-1

R1-1

R0-1

Z

G11-0

G10-0

G9-0

G8-0

G7-0

G6-0

G5-0

G4-0

Z

G11-1

G10-1

G9-1

G8-1

G7-1

G6-1

G5-1

G4-1

Z

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Y1

Main Y0

Z

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Y1

Main Y0

Z

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Y1

Main Y0

Main Cr9

Main Cr8

Main Cr7

Main Cr6

Main Cr5

Main Cr4

Main Cr3

Main Cr2

Main Cr1

Main Cr0

Aux Y9

Main Y11

Main Y10

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Cb11

Main Cb10

Main Cb9

Main Cb8

Main Cb7

Main Cb6

Main Cb5

Main Cb4

Main Cb3

Main Cb2

Aux Cb11, Cr11

Aux Cb10, Cr10

Aux Cb9, Cr9

Aux Cb8, Cr8

Aux Cb7, Cr7

Aux Cb6, Cr6

Aux Cb5, Cr5

Aux Cb4, Cr4

Aux Cb3, Cr3

Aux Cb2, Cr2

Main Y11

Main Y10

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Main Y3

Main Y2

Main Cr11

Main Cr10

Main Cr9

Main Cr8

Main Cr7

Main Cr6

Main Cr5

Main Cr4

Main Cr3

Main Cr2

Aux Y11

Aux Y10

Aux Y9

Aux Y8

Aux Y7

Aux Y6

Aux Y5

Aux Y4

Aux Y3

Aux Y2

Main Y3

Main Y2

Main Y1

Main Y0

Z

B11-0

B10-0

B9-0

B8-0

B7-0

B6-0

B5-0

B4-0

Z

B11-1

B10-1

B9-1

B8-1

B7-1

B6-1

B5-1

B4-1

Z

Main Cb7

Main Cb6

Main Cb5

Main Cb4

Main Cb3

Main Cb2

Main Cb1

Main Cb0

Z

Main Cr7

Main Cr6

Main Cr5

Main Cr4

Main Cr3

Main Cr2

Main Cr1

Main Cr0

Z

Main Cb9

Main Cb8

Main Cb7

Main Cb6

Main Cb5

Main Cb4

Main Cb3

Main Cb2

Main Cb1

Main Cb0

Aux Cb9, Cr9

Aux Cb8, Cr8

Aux Cb7, Cr7

Aux Cb6, Cr6

Aux Cb5, Cr5

Aux Cb4, Cr4

Aux Cb3, Cr3

Aux Cb2, Cr2

Aux Cb1, Cr1

Aux Cb0, Cr0

Z

R11-0

R10-0

R9-0

R8-0

R7-0

R6-0

R5-0

R4-0

Z

R11-1

R10-1

R9-1

R8-1

R7-1

R6-1

R5-1

R4-1

Z

Aux Cb7, Cr7 Aux Y7

Aux Cb6, Cr6 Aux Y6

Aux Cb5, Cr5 Aux Y5

Aux Cb4, Cr4 Aux Y4

Aux Cb3, Cr3 Aux Y3

Aux Cb2, Cr2 Aux Y2

Aux Cb1, Cr1 Aux Y1

Aux Cb0, Cr0 Aux Y0

P8

P7

P6

P5

P4

P3

P2

P1

Aux Y8

Aux Y7

Aux Y6

Aux Y5

Aux Y4

Aux Y3

Aux Y2

Aux Y1

Z

P0

Z

Aux Y0

Rev. D | Page 31 of 36

ADV7802

Data Sheet

OP_FORMAT_SEL

[5:0]

0x3B

0x3C

0x3D

0x3E

24-Bit and 12-Bit DDR 4:2:2 Mode 2

Parallel Output (CLK/2)

24-Bit DDR 4:2:2 RGB

24-Bit DDR 4:2:2 RGB (CLK/2) (CLK/2) Mode 1

24-Bit DDR 4:2:2 RGB

(CLK/2) Mode 2

Pixel Output

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

P9

Clock Rise

Main Y3

Main Y2

Main Y1

Main Y0

Z

Main Cb3

Main Cb2

Main Cb1

Main Cb0

Z

Aux Cb3, Cr3

Aux Cb2, Cr2

Aux Cb1, Cr1

Aux Cb0, Cr0

Z

Clock Fall

Main Y3

Main Y2

Main Y1

Main Y0

Z

Main Cr3

Main Cr2

Main Cr1

Main Cr0

Z

Aux Y3

Aux Y2

Aux Y1

Aux Y0

Z

Clock Rise

Clock Fall

Clock Rise

Clock Fall

Clock Rise

Clock Fall

Main Y11

Main Y10

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Z

Main Y11

Main Y10

Main Y9

Main Y8

Main Y7

Main Y6

Main Y5

Main Y4

Z

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

R7-0

R6-0

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

Z

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

Z

R7-0

R6-0

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

Z

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

Z

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

R7-0

R6-0

R5-0

R4-0

R3-0

R2-0

R1-0

R7-0

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

Z

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R7-1

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

Z

Main Cb11

Main Cb10

Main Cb9

Main Cb8

Main Cb7

Main Cb6

Main Cb5

Main Cb4

Z

Main Cr11

Main Cr10

Main Cr9

Main Cr8

Main Cr7

Main Cr6

Main Cr5

Main Cr4

Z

Aux Cb11, Cr11

Aux Cb10, Cr10

Aux Cb9, Cr9

Aux Cb8, Cr8

Aux Cb7, Cr7

Aux Cb6, Cr6

Aux Cb5, Cr5

Aux Cb4, Cr4

Z

Aux Y11

Aux Y10

Aux Y9

Aux Y8

Aux Y7

Aux Y6

Aux Y5

Aux Y4

Z

P8

P7

P6

P5

P4

P3

P2

P1

Z

P0

Z

Rev. D | Page 32 of 36

Data Sheet

ADV7802

Table 10. Pixel Port Input Modes

IP_DATA_SEL[5:0]

0x00

0x01

0x04

0x06

0x07

Pixel Input

24-Bit 4:4:4 Input 20-Bit 4:2:2 Input 16-Bit 4:2:2 Input 10-Bit 4:2:2 Input 8-Bit 4:2:2 Input

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

G7

Y9

Y8

Y7

Y6

Y7

Y6

Y5

Y4

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Y6, Cb6, Cr6

Y7, Cb7, Cr7

Y6, Cb6, Cr6

Y5,Cb5, Cr5

Y4, Cb4, Cr4

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

R7

R6

R5

R4

R3

R2

R1

R0

Y5

Y4

Y3

Y2

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Y1

Y0

Z

Cb1, Cr1

Cb0, Cr0

Z

Y3

Y2

Y1

Y0

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Y5,Cb5, Cr5

Y4, Cb4, Cr4

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

Z

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

Z

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

Z

Rev. D | Page 33 of 36

ADV7802

Data Sheet

OUTLINE DIMENSIONS

26.20

26.00 SQ

25.80

0.75

0.60

0.45

1.60

MAX

133

132

176

1

PIN 1

24.20

24.00 SQ

23.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.15

0.05

89

44

45

SEATING

PLANE

0.08 MAX

COPLANARITY

88

VIEW A

0.27

0.22

0.17

0.50

BSC

VIEW A

ROTATED 90° CCW

LEAD PITCH

COMPLIANT TO JEDEC STANDARDS MS-026-BGA

Figure 12. 176-Lead Low Profile Quad Flat Package [LQFP]

(ST-176)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

ADV7802BSTZ-80

ADV7802BSTZ-150

EVAL-ADV7802EB1Z

0°C to +85°C

176-Lead Low Profile Quad Flat Package [LQFP]

Evaluation Board (with External DDR SD Memory)

ST-176

¹Z = RoHS Compliant Part.

Rev. D | Page 34 of 36

Data Sheet

NOTES

ADV7802

Rev. D | Page 35 of 36

ADV7802

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D06654-0-8/11(D)

Rev. D | Page 36 of 36


型号：	ADV7802BSTZ-80
厂家：	ADI
描述：	12-Bit, SDTV/HDTV 3D Comb Filter, Video Decoder, and Graphics Digitizer 商用集成电路电视
文件：	总37页 (文件大小：728K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7802BSTZ-80 [ADI]

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