ADV7842KBCZ-5_技术文档

Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz

Video and Graphics Digitizer and 3D Comb Filter Decoder

ADV7842

Vertical peaking and horizontal peaking filters

Robust synchronization extraction for poor video source

Advanced VBI data slicer

FEATURES

Dual HDMI® 1.4a fast switching receiver

HDMI support

3D TV support

General

Highly flexible 36-bit pixel output interface

Internal EDID RAM for HDMI and graphics

Dual STDI (standard identification) function support

Any-to-any, 3 × 3 color space conversion (CSC) matrix

2 programmable interrupt request output pins

Simultaneous analog processing and HDMI monitoring

Content type bits

CEC 1.4-compatible

Extended colorimetry

256-ball, 17 mm × 17 mm BGA package

HDMI 225 MHz receiver

Xpressview fast switching of HDMI ports

3D video format support including frame packing 1080p

24 Hz, 720p 50 Hz, 720p 60 Hz

Full colorimetry support including sYCC601, Adobe RGB,

Adobe YCC 601

36-/30-bit Deep Color and 24-bit color support

HDCP 1.4 support with internal HDCP keys

Adaptive HDMI equalizer

Integrated CEC controller

HDMI repeater support

5 V detect and hot plug assert for each HDMI port

HDMI audio support including HBR and DSD

Advanced audio mute feature

APPLICATIONS

Advanced TVs

PDP HDTVs, LCD TVs (HDTV ready)

LCD/DLP® rear projection HDTVs

CRT HDTVs, LCoS™ HDTVs

AVR video receivers

LCD/DLP front projectors

HDTV STBs with PVR

Projectors

FUNCTIONAL BLOCK DIAGRAM

SDRAM

Flexible digital audio output interfaces

Supports up to 5 S/PDIF outputs

SCART

CVBS

48

CVBS

Supports up to 4 I²S outputs

SCART RGB

+ CVBS

ADC

HS/VS

Video and graphics digitizer

Four 170 MHz, 12-bit ADCs

12-channel analog input mux

525i-/625i-component analog input

525p-/625p-component progressive scan support

720p-/1080i-/1080p-component HDTV support

Low refresh rates (24 Hz/25 Hz/30 Hz) support for

720p/1080p

SDP

CVBS

3D YC

S-VIDEO

SCART

SCART G

SCART B

SCART R

CVBS

FIELD/DE

CLK

HS/VS

YC

DATA

FIELD/DE

SD/PS

YPbPr

CLK

HS/VS

CP

Y/G

Pb/B

Pr/R

YPbPr

525p/625p

720p/1080i

1080p/

FIELD/DE

36-BIT

YCbCr/RGB

HD YPbPr

GRAPHICS

RGB

CLK

DATA

UXGA

RGB

Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA)

SCART fast blank support

3D video decoder

NTSC/PAL/SECAM color standards support

NTSC/PAL 2D/3D motion detecting comb filter

Advanced time-base correction (TBC) with frame

synchronization

Interlaced-to-progressive conversion for 525i and 625i

IF compensation filters

36

2

I S

HDMI 1

HDMI 2

4

TMDS

AUDIO

OUTPUT

DDC

S/PDIF

DSD

DEEP

COLOR

HDMI Rx

5

TMDS

DDC

HBR

MCLK

SCLK

FAST

SWITCH

SCLK

HDCP

KEYS

TO AUDIO

PROCESSOR

ADV7842

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

ADV7842

TABLE OF CONTENTS

Features .............................................................................................. 1

Power-Up Sequence ................................................................... 12

Power-Down Sequence.............................................................. 12

Pin Configuration and Function Descriptions........................... 13

Functional Overview...................................................................... 20

HDMI Receiver........................................................................... 20

Analog Front End....................................................................... 20

Standard Definition Processor ................................................. 21

Component Processor ............................................................... 21

Other Features ............................................................................ 22

External Memory Requirements.................................................. 23

Single Data Rate (SDR).............................................................. 23

Double Data Rate (DDR) .......................................................... 23

Pixel Input/Output Formatting .................................................... 24

Pixel Data Output Modes Features .......................................... 24

Register Map Architecture ............................................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications..................................................................................... 5

Electrical Characteristics............................................................. 5

Power Specifications .................................................................... 6

Analog Specifications................................................................... 8

Video Specifications..................................................................... 8

Timing Characteristics ................................................................ 9

Timing Diagrams........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

Package Thermal Performance................................................. 11

ESD Caution................................................................................ 11

Power Supply Sequencing.............................................................. 12

REVISION HISTORY

1/11—Rev. SpA to Rev. B

Updated Revision Number................................................Universal

Updated Publication Code ............................................................ 28

10/10—Rev. Sp0 to Rev. SpA

Changes to Product Title and Features Section............................ 1

Changes to Note 1, Table 1.......................................................................5

Added Note 1, Table 5...............................................................................9

Changes to Pin No. C11 Description, Table 7 ....................................14

Changes to Pin No. N11 Description, Table 7 and Pin No. P11

Description, Table 7.................................................................................18

6/10—Revision Sp0: Initial Version

Rev. B | Page 2 of 28

ADV7842

GENERAL DESCRIPTION

The ADV7842 is a high quality, single-chip, 2:1 multiplexed

HDMI™ receiver and graphics digitizer with an integrated

multiformat video decoder.

The multiformat 3D comb filter decoder supports the conversion

of PAL, NTSC, and SECAM standards in the form of a composite

or an S-Video input signal into a digital ITU-R BT.656 format.

SCART and overlay functionality are enabled by the ability of the

ADV7842 to process CVBS and standard definition RGB signals

simultaneously.

The ADV7842 incorporates a dual input HDMI 1.4-compatible

receiver that supports all HDTV formats up to 1080p and

display resolutions up to UXGA (1600 × 1200 at 60 Hz).

The ADV7842 contains one main component processor (CP)

that processes YPbPr and RGB component formats, including

RGB graphics. The CP also processes the video signals from the

HDMI receiver. The ADV7842 can operate in dual HDMI and

analog input mode, thus allowing for fast switching between the

ADCs and HDMI.

The ADV7842 incorporates Xpressview™ fast switching on both

input HDMI ports. Using the Analog Devices, Inc., hardware-

based HDCP engine that minimizes software overhead,

Xpressview technology allows fast switching between any

HDMI input ports in less than 1 second.

The ADV7842 supports all mandatory HDMI 1.4 3D TV formats

in addition to all HDTV formats up to 1080p, 36-bit Deep Color.

The ADV7842 supports the decoding of a component RGB/

YPbPr video signal into a digital YCbCr or RGB pixel output

stream. The support for component video includes 525i, 625i,

525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as

many other SMPTE and HD standards.

The ADV7842 also integrates an HDMI v1.4 CEC controller

that supports the capability discovery and control (CDC)

feature.

The ADV7842 offers a flexible audio output port for the audio

data decoded from the HDMI stream. HDMI audio formats,

including super audio CD (SACD) via DSD and HBR are

supported.

The ADV7842 supports graphics digitization. The ADV7842 is

capable of digitizing RGB graphics signals from VGA to UXGA

rates and converting them into a digital RGB or YCbCr pixel

output stream. Internal EDID is available for one graphic port.

Each HDMI port has dedicated 5 V detect and hot plug assert

pins. The HDMI receiver also includes an integrated equalizer

that ensures robust operation of the interface with cable lengths

up to 30 meters. The HDMI receiver has advanced audio

functionality, such as a mute controller, that prevents audible

extraneous noise in the audio output.

Fabricated in an advanced CMOS process, the ADV7842 is

provided in a 17 mm × 17 mm, 256-ball, BGA, surface-mount,

RoHS-compliant package and is specified over the −10°C to

+70°C temperature range.

Rev. B | Page 3 of 28

ADV7842

DETAILED FUNCTIONAL BLOCK DIAGRAM

0 0 2

0

R

T T A E M

T U F O T R P

I O D O U A U

R

T T A E M

T U F O T R P O E O I U D V

U X M

U X M +

D E C O I D E H D M C K O + B L

N G C T H I I W S T A F S

Figure 2. Detailed Functional Block Diagram

Rev. B | Page 4 of 28

ADV7842

SPECIFICATIONS

AVDD = 1.8 V 5%, CVDD = 1.8 V 5%, DVDD = 1.8 V 5%, PVDD = 1.8 V 5%, DVDDIO = 3.3 V 5%, TVDD = 3.3 V 5%,

VDD_SDRAM = 3.2 V to 3.4 V (SDR), VDD_SDRAM = 2.35 V to 2.65 V (DDR). T_MINto T_MAX= −10°C to +70°C, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each ADC)

Integral Nonlinearity

N

INL

12

Bits

LSB

27 MHz (at a 12-bit level)

54 MHz (at a 12-bit level)

74.25 MHz (at a 12-bit level)

108 MHz (at a 11-bit level)

170 MHz (at a 9-bit level)

27 MHz (at a 12-bit level)

54 MHz (at a 12-bit level)

75 MHz (at a 12-bit level)

108 MHz (at a 11-bit level)

170 MHz (at a 9-bit level)

−3.0 to +8.0

−4.0 to +7.0

−3.5 to +8.0

−0.7 to +1.5

−0.7 to +0.8

−0.6 to +0.5

Differential Nonlinearity

DNL

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

V_IH

V_IL

V_IH

V_IL

I_IN

XTALN and XTALP pins

Other digital inputs

RESET pin

1.2

2

V

µA

pF

0.4

0.8

60

10

Input Current

EP_MISO pin

SPDIF_IN pin

TEST4 pin

TEST6 pin

Other digital inputs

Input Capacitance

DIGITAL INPUTS (5 V TOLERANT)¹

Input High Voltage

Input Low Voltage

Input Current

C_IN

V_IH

V_IL

I_IN

2.6

V

µA

0.8

+82

−82

2.4

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

High Impedance Leakage Current

Output Capacitance

V_OH

V_OL

I_LEAK

C_OUT

V

µA

pF

0.4

20

10

¹The following pins are 5 V tolerant: HS_IN1/TRI5, HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, RXA_5V, RXB_5V, DDCA_SCL, DDCA_SDA, DDCB_SCL, and DDCB_SDA.

Rev. B | Page 5 of 28

ADV7842

POWER SPECIFICATIONS

Table 2.

Parameter

Symbol

Min Typ Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

Digital Core Power Supply

Digital I/O Power Supply

SDRAM Power Supply

VDD

1.75 1.8

3.14 3.3

1.85

3.46

3.4

2.65

1.89

3.46

1.89

V

DVDDIO

VDD_SDRAM

PVDD

AVDD

TVDD

3.2

3.3

SDR memory

DDR memory

2.35 2.5

1.71 1.8

3.14 3.3

1.71 1.8

PLL Power Supply

Analog Power Supply

Terminator Power Supply

Comparator Power Supply

CURRENT CONSUMPTION^{1, 2, 3}

Digital Core Supply Current

CVDD

I_VDD

155

148

285

220

196

343

mA

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with both background ports enabled

163

216

176

273

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color in simultaneous mode with

both background ports enabled

194

332

230

378

mA

CVBS processing

CVBS processing in simultaneous mode with both

background ports enabled

57

197

72

224

mA

SD 576i component processing

SD 576i component processing in simultaneous mode with

both background ports enabled

270

404

289

435

mA

SCART processing

SCART processing in simultaneous mode with both

background ports enabled

Digital I/O Supply Current

I_DVDDIO

51

41

45

109

129

117

mA

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with both background ports enabled

27

22

32

150

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color in simultaneous mode with

both background ports enabled

9

10

11

mA

CVBS processing

CVBS processing in simultaneous mode with both

background ports enabled

8

11

mA

SD 576i component processing

SD 576i component processing in simultaneous mode with

both background ports enabled

10

11

12

mA

SCART processing

SCART processing in simultaneous mode with both

background ports enabled

Rev. B | Page 6 of 28

ADV7842

Parameter

PLL Supply Current

Symbol

I_PVDD

Min Typ Max

Unit

mA

Test Conditions/Comments

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with both background ports enabled

28

25

30

27

28

35

36

38

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color in simultaneous mode with

both background ports enabled

34

35

37

mA

CVBS processing

CVBS processing in simultaneous mode with both

background ports enabled

22

24

mA

SD 576i component processing

SD 576i component processing in simultaneous mode with

both background ports enabled

34

35

37

mA

SCART processing

SCART processing in simultaneous mode with both

background ports enabled

Analog Supply Current

I_AVDD

279

281

285

295

297

301

mA

Analog 1080p sampling at 148 MHz

RGB graphics sampling at 162 MHz

RGB graphics sampling at 162 MHz in simultaneous mode

with both background ports enabled

0.1

0.3

mA

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color in simultaneous mode with

both background ports enabled

85

86

89

91

mA

CVBS processing

CVBS processing in simultaneous mode with both

background ports enabled

267

270

281

285

mA

SD 576i component processing

SD 576i component processing in simultaneous mode with

both background ports enabled

283

286

294

301

mA

SCART processing

SCART processing in simultaneous mode with both

background ports enabled

Terminator Supply Current⁴

Comparator Supply Current

I_TVDD

I_CVDD

85

95

mA

One port connected

Two ports connected

HDMI 1080p: 12-bit Deep Color

HDMI 1080p: 12-bit Deep Color in simultaneous mode with

both background ports enabled

120

220

135

130

250

Memory Interface Supply

Current

I_{VDD_SDRAM}

28

35

mA

CVBS input sampling at 54 MHz

Power-Down Currents⁵

I_DVDDIO

I_{VDD_SDRAM}

I_VDD

I_AVDD

I_CVDD

I_TVDD

I_PVDD

t_PWRUP

0.1

2.6

10

0.1

0.5

1.1

1.7

mA

ms

Power-Up Time

25

¹All maximum current values are guaranteed by characterization to assist in power supply design.

²Typical current consumption values are recorded with nominal voltage supply levels, SMPTE bar video pattern, and at room temperature.

³Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature.

⁴Termination power supply includes TVDD current consumed off chip.

⁵Power-down mode entered by setting Bit POWER_DOWN high.

Rev. B | Page 7 of 28

ADV7842

ANALOG SPECIFICATIONS

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLAMP CIRCUITRY¹

Input Impedance

Analog (AIN1 − AIN12)

ADC Midscale (CML)

ADC Full-Scale Level

ADC Zero-Scale Level

ADC Dynamic Range

Clamp Level (When Locked)

Clamps switched off

10

MΩ

0.91

V

mA

μA

CML + 0.55

CML − 0.55

1.1

CML − 0.12

CML

Component input, Y signal

Component input, Pr signal

Component input, Pb signal

PC RGB input (R, G, B signals)

CVBS input

SCART RGB input (R, G, B signals)

S-Video input (Y Signal)

S-Video input (C Signal)

SDP only

CML

CML − 0.12

CML − 0.205

CML

0.3

0.4

9

8

Large Clamp Source Current

Large Clamp Sink Current

Fine Clamp Source Current

Fine Clamp Sink Current

SDP only

¹Specified for external clamp capacitor of 100 nF.

VIDEO SPECIFICATIONS

Table 4.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

NONLINEAR SPECIFICATIONS

Differential Phase

Differential Gain

DP

DG

LNL

CVBS input (modulated five-step)

Measured at 27 MHz LLC

Luma ramp

0.6

0.8

0.9

Degrees

%

Luma Nonlinearity

NOISE SPECIFICATIONS

SNR Unweighted

63

64

60

dB

SNR Unweighted

Luma flat field

Analog Front-End Crosstalk

LOCK TIME SPECIFICATIONS (SDP)

Horizontal Lock Range

Vertical Lock Range

Subcarrier Lock Range

Color Lock-In Time

5

%

Hz

kHz

Lines

%

40

70

f_SC

0.8

60

Sync Depth Range¹

Color Burst Range

20

1

200

%

Vertical Lock Time

300

100

ms

Lines

Horizontal Lock Time

CHROMA SPECIFICATIONS (SDP)

Chroma Amplitude Error

Chroma Phase Error

Chroma Luma Intermodulation

0.9

0.3

%

Degrees

%

¹Nominal synchronization depth is 300 mV at 100% of the synchronization depth range.

Rev. B | Page 8 of 28

ADV7842

TIMING CHARACTERISTICS

Data and I²C Timing Characteristic

Table 5.

Parameter¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Crystal Frequency, XTAL

Crystal Frequency Stability

Horizontal Sync Input Frequency

LLC Frequency Range

I²C PORTS

28.63636

MHz

ppm

kHz

50

110

170

10

12.825

MHz

SCL Frequency

400

kHz

ns

µs

ns

µs

SCL Minimum Pulse Width High

SCL Minimum Pulse Width Low

Start Condition Hold Time

Start Condition Setup Time

SDA Setup Time

SCL and SDA Rise Time

SCL and SDA Fall Time

Stop Condition Setup Time

TTX I²C PORTS

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

600

1.3

600

100

1000

300

0.6

SCL Frequency

3.4

MHz

ns

SCL Minimum Pulse Width High

SCL Minimum Pulse Width Low

Start Condition Hold Time

Start Condition Setup Time

SDA Setup Time

SCL and SDA Rise Time

SCL and SDA Fall Time

Stop Condition Setup Time

RESET FEATURE

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

60

160

10

80

160

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC Mark-Space Ratio

DATA AND CONTROL OUTPUTS²

t₉:t₁₀

45:55

55:45

% duty cycle

Data Output Transition Time SDR (SDP) t₁₁

Data Output Transition Time SDR (SDP) t₁₂

End of valid data to negative clock edge

Negative clock edge to start of valid data

End of valid data to negative clock edge

Negative clock edge to start of valid data

2.9

0.2

1.5

0.1

4.6

0.6

2.2

0.3

ns

Data Output Transition Time SDR (CP)

I²S PORT, MASTER MODE

t₁₃

t₁₄

SCLK Mark-Space Ratio

t₁₅:t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

45:55

55:45

10

5

% duty cycle

LRCLK Data Transition Time

I2Sx Data Transition Time

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

ns

I2Sx Data Transition Time

5

¹Guaranteed by characterization.

²With the DLL block on output clock bypassed.

Rev. B | Page 9 of 28

ADV7842

TIMING DIAGRAMS

t₃

t₅

t₃

SDA

SCL

t₆

t₁

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₉

t₁₀

LLC

t₁₁

t₁₂

P0 TO P35, HS/CS,

VS/FIELD, FIELD/DE

Figure 4. Pixel Port and Control SDR Output Timing (SDP)

t₉

t₁₀

LLC

t₁₃

t₁₄

P0 TO P35, VS/FIELD,

HS/CS, FIELD/DE

Figure 5. Pixel Port and Control SDR Output Timing (CP)

t₁₅

SCLK

t₁₆

t₁₇

LRCLK

t₁₈

t₁₉

I2Sx

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

t₂₀

t₁₉

I2Sx

2

MSB

I S MODE

MSB – 1

t₂₀

t₁₉

I2Sx

RIGHT-JUSTIFIED

MODE

MSB

LSB

t₂₀

NOTES

1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3 ENDING PIN NAMES.

2. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN.

3. I2Sx ARE SIGNALS ACCESSIBLE VIA AP1 TO AP4 PINS.

Figure 6. I²S Timing

Rev. B | Page 10 of 28

ADV7842

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter

PACKAGE THERMAL PERFORMANCE

Rating

To reduce power consumption when using the ADV7842, the

user is advised to turn off unused sections of the part.

AVDD to GND

VDD to GND

2.2 V

PVDD to GND

DVDDIO to GND

VDD_SDRAM to GND

CVDD to GND

TVDD to GND

AVDD to PVDD

AVDD to VDD

TVDD to CVDD

DVDDIO to VDD_SDRAM

VDD_SDRAM to AVDD

VDD_SDRAM to VDD

Digital Inputs Voltage to GND

Digital Outputs Voltage to GND

5 V Tolerant Digital Inputs to GND¹

Analog Inputs to GND

XTALN and XTALP to GND

Maximum Junction Temperature

2.2 V

4.0 V

2.2 V

Due to PCB metal variation, and therefore variation in PCB

heat conductivity, the value of θ may differ for various PCBs.

JA

The most efficient measurement solution is obtained using the

package surface temperature to estimate the die temperature

because this eliminates the variance associated with the _JAθvalue.

4.0 V

−0.3 V to +0.3 V

−0.3 V to +2.2 V

−0.3 V to +3.3 V

−0.3 V to +2 V

−0.3 V to DVDDIO + 0.3 V

5.5 V

The maximum junction temperature (T_{J MAX}) of 125°C must not be

exceeded. The following equation calculates the junction tempera-

ture using the measured package surface temperature and applies

only when no heat sink is used on the device under test (DUT):

T_J= T_S+

(

Ψ _JT×W_TOTAL

)

where:

T_Sis the package surface temperature (°C).

_JT= 0.5°C/W for the 256-ball BGA.

_TOTAL= (PVDD × I_PVDD) + (0.4 × TVDD × I_TVDD) +

Ψ

−0.3 V to AVDD + 0.3 V

−0.3 V to PVDD + 0.3 V

125°C

W

(CVDD × I_CVDD) + (AVDD × I_AVDD) + (VDD × I_VDD) +

(A × DVDDIO × I_DVDDIO) + (VDD_SDRAM × I_{VDD_SDRAM}

(T_{J MAX}

)

Storage Temperature Range

Infrared Reflow Soldering (20 sec)

−65°C to +150°C

260°C

where:

0.4 reflects the 40% of TVDD power that is dissipated on the

part itself.

A = 0.5 when the output pixel clock is >74 MHz.

A = 0.75 when the output pixel clock is ≤74 MHz.

¹The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI5,

HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, DDCA_SCL, DDCA_SDA, DDCB_SCL

and DDCB_SDA.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. B | Page 11 of 28

ADV7842

POWER SUPPLY SEQUENCING

POWER-UP SEQUENCE

Notes

Reset should be held low while the supplies are being powered up.

The recommended power-up sequence of the ADV7842 is as

follows:

•

3.3 V supplies should be powered up first.

2.5 V supply should be powered after the 3.3 V supplies are

established but before the 1.8 V supplies.

1. 3.3 V supplies

2. 2.5 V supply (applies only if using DDR memory)

3. 1.8 V supplies

•

1.8 V supplies should be powered up last.

3.3V SUPPLIES

3.3V

The ADV7842 can alternatively be powered up by simulta-

neously asserting all supplies.

2.5V

In this case, care must be taken to ensure that a lower rated supply

does not go above a higher rated supply level, because the supplies

are being established.

2.5V SUPPLIES (IF ANY)

1.8V SUPPLIES

1.8V

POWER-DOWN SEQUENCE

The ADV7842 supplies can be deasserted simultaneously as

long as a higher rated supply does not go below a lower rated

supply.

3.3V SUPPLIES

POWER-UP

2.5V SUPPLIES 1.8V SUPPLIES

POWER-UP POWER-UP

Figure 7. Recommended Power-Up Sequence

Rev. B | Page 12 of 28

ADV7842

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

C

D

E

GND

P3

P1

P0

TVDD

RXB_2–

RXB_1–

RXB_0– RXB_C–

RXB_0+ RXB_C+

GND

RXA_2– RXA_1–

RXA_2+ RXA_1+

RXA_0–

RXA_C–

TVDD

GND

A

B

C

D

E

P5

P7

P4

P6

P2

SYNC_OUT

TVDD

GND

RXB_2+

HPA_B

CEC

RXB_1+

HPA_A

GND

RXA_0+ RXA_C+

TVDD

GND

XTALP

XTALN

PVDD

REFN

TRI3

TEST8

VS/FIELD HS/CS

EP_MISO FIELD/DE

EP_CS EP_MOSI

RXB_5V RXA_5V PWRDN1

CVDD

AVDD

CVDD

P9

P8

DDCB_SDA DDCB_SCL DDCA_SDA DDCA_SCL RTERM

VGA_SCL VGA_SDA PVDD

GND

P12

P14

P10

P11

P13

GND

CVDD

GND

HS_IN2/TRI7 VS_IN2/TRI8

REFP

TRI4

AIN9

EP_SCK TTX_SCL DVDDIO

GND

AIN12

AIN10

AIN11

F

G

H

J

F

G

H

J

TTX_SDA

MCLK

DVDDIO

GND

SYNC4

AIN8

P16

P18

P15

P17

AP0

AP5

AP4

DVDDIO

GND

VDD

GND

AVDD

TRI1

AIN6

TRI2

AIN4

AIN7

SYNC3

GND

SCLK

SYNC2

P20

P22

P19

P21

AP3

SCL

AP1

AP2

DVDDIO

VDD

GND

AVDD

AIN5

VS_IN1/TRI6

HS_IN1/TRI5

AIN2

AIN1

AIN3

K

L

K

L

AOUT

SYNC1

M

N

P

M

N

P

GND

LLC

P25

P27

P23

P24

P26

P28

SDA

INT2

INT1

TEST4

AVLINK

P32

DVDDIO VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM

GND

RESET

TEST6

SDRAM_A8 SDRAM_A4 SDRAM_A0 SDRAM_CS SDRAM_LDQS SDRAM_DQ4 SDRAM_DQ15 SDRAM_DQ11 SDRAM_CK SDRAM_CKE

TEST5

P30

TEST7 SDRAM_A11 SDRAM_A7 SDRAM_A3 SDRAM_A10 SDRAM_RAS SDRAM_DQ7 SDRAM_DQ3 SDRAM_VREF SDRAM_DQ12 SDRAM_UDQS SDRAM_CK

P34

SDRAM_A9 SDRAM_A6 SDRAM_A2 SDRAM_BA1 SDRAM_CAS SDRAM_DQ6 SDRAM_DQ2 SDRAM_DQ0 SDRAM_DQ13 SDRAM_DQ9

SDRAM_DQ8

R

T

R

T

GND

1

P29

2

P31

3

P33

4

P35

5

GND

6

SDRAM_A5 SDRAM_A1 SDRAM_BA0 SDRAM_WE SDRAM_DQ5

GND

12

SDRAM_DQ1 SDRAM_DQ14 SDRAM_DQ10

GND

16

7

8

9

10

11

13

14

15

Figure 8. Pin Configuration (Top View)

Rev. B | Page 13 of 28

ADV7842

Table 7. Pin Function Descriptions

Pin No. Mnemonic

Type

Description

A1

GND

Ground

Ground.

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

P3

P1

P0

Digital video output

Power

HDMI input

Ground

HDMI input

Power

Video Pixel Output Port.

Terminator Supply Voltage (3.3 V).

TVDD

RXB_2−

RXB_1−

RXB_0−

RXB_C−

GND

RXA_2−

RXA_1−

RXA_0−

RXA_C−

TVDD

GND

Digital Input Channel 2 Complement of Port B in the HDMI Interface.

Digital Input Channel 1 Complement of Port B in the HDMI Interface.

Digital Input Channel 0 Complement of Port B in the HDMI Interface.

Digital Input Clock Complement of Port B in the HDMI Interface.

Ground.

Digital Input Channel 2 Complement of Port A in the HDMI Interface.

Digital Input Channel 1 Complement of Port A in the HDMI Interface.

Digital Input Channel 0 Complement of Port A in the HDMI Interface.

Digital Input Clock Complement of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Ground.

Video Pixel Output Port.

Sliced Synchronization Output

Terminator Supply Voltage (3.3 V).

Digital Input Channel 2 True of Port B in the HDMI Interface.

Digital Input Channel 1 True of Port B in the HDMI Interface.

Digital Input Channel 0 True of Port B in the HDMI Interface.

Digital Input Clock True of Port B in the HDMI Interface.

Ground.

Digital Input Channel 2 True of Port A in the HDMI Interface.

Digital Input Channel 1 True of Port A in the HDMI Interface.

Digital Input Channel 0 True of Port A in the HDMI Interface.

Digital Input Clock True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Ground

P5

P4

P2

Digital video output

Miscellaneous digital

Power

HDMI input

Ground

HDMI input

Power

SYNC_OUT

TVDD

RXB_2+

RXB_1+

RXB_0+

RXB_C+

GND

RXA_2+

RXA_1+

RXA_0+

RXA_C+

TVDD

XTALP

Miscellaneous analog

Input pin for 28.63636 MHz crystal or external 1.8V, 28.63636 MHz Clock Oscillator

Source to Clock the ADV7842.

C1

C2

C3

P7

P6

VS/FIELD

Digital video output

Video Pixel Output Port.

Vertical Synchronization/Field Synchronization. VS is a vertical synchronization output

signal in the CP and HDMI processor. FIELD is a field synchronization output signal in

all interlaced video modes. VS or FIELD can be configured for this pin.

C4

HS/CS

Digital video output

Horizontal Synchronization/Composite Synchronization. HS is a horizontal

synchronization output signal in the CP and HDMI processor. CS (composite

synchronization) signal is a single signal containing both horizontal and vertical

synchronization pulses. HS or CS can be configured for this pin.

C5

C6

C7

C8

C9

C10

GND

Ground

Ground.

HPA_B

HPA_A

RXB_5V

RXA_5V

PWRDN1

Miscellaneous digital

HDMI input

Miscellaneous digital

Hot Plug Assert Signal Output for HDMI Port B.

Hot Plug Assert Signal Output for HDMI Port A.

5 V Detect Pin for Port B in the HDMI Interface.

5 V Detect Pin for Port A in the HDMI Interface.

Controls the Power-Up of the ADV7842. Should be connected to a digital 3.3 V I/O

supply to power up the ADV7842.

C11

C12

C13

C14

TEST8

CVDD

Test pin

Power

Tie this pin to ground via 4.7 kΩ resistor.

Comparator Supply Voltage (1.8 V).

Rev. B | Page 14 of 28

ADV7842

Pin No. Mnemonic

Type

Description

C15

C16

D1

D2

D3

GND

XTALN

P9

P8

EP_MISO

FIELD/DE

Ground

Ground.

Miscellaneous analog

Digital video output

Digital input

Input Pin for 28.63636 MHz Crystal.

Video Pixel Output Port.

SPI Master In/Slave Out for External EDID Interface.

Data Enable (DE). DE is a signal that indicates active pixel data.

D4

Miscellaneous digital

Field Synchronization Output Signal in All Interlaced Video Modes (FIELD).

DE or FIELD can be configured for this pin.

D5

GND

Ground

Ground.

D6

D7

D8

D9

D10

D11

CEC

Digital input/output

Digital input

Digital input/output

Digital input

Consumer Electronic Control Channel.

DDCB_SDA

DDCB_SCL

DDCA_SDA

DDCA_SCL

RTERM

HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant.

HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant.

HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.

Sets Internal Termination Resistance. A 500 Ω resistor between this pin and GND

should be used.

Miscellaneous analog

D12

D13

D14

D15

D16

E1

CVDD

VGA_SCL

VGA_SDA

PVDD

GND

Power

Comparator Supply Voltage (1.8 V).

DDC Port Serial Clock Input for VGA

DDC Port Serial Data Input/Output for VGA

PLL Supply Voltage (1.8 V).

Ground.

Miscellaneous digital

Power

Ground

E2

E3

P10

Digital video output

Digital output

Ground

Video Pixel Output Port.

SPI Chip Select for External EDID Interface.

SPI Master Out/Slave In for External EDID Interface.

Ground.

EP_CS

EP_MOSI

GND

E4

E5

E6

GND

Ground

Ground.

E7

GND

Ground

Ground.

E8

GND

Ground

Ground.

E9

GND

Ground

Ground.

E10

E11

E12

E13

GND

Ground

Power

Miscellaneous analog

Ground.

CVDD

HS_IN2/TRI7

Comparator Supply Voltage (1.8 V).

HS on Graphics Port 2 (HS_IN2). The HS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-terminal Connector (TRI7). (Selection available

via the I²C.)

E14

VS_IN2/TRI8

Miscellaneous analog

VS on Graphics Port 2 (VS_IN2). The VS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI8). (Selection available

via the I²C.)

E15

E16

F1

F2

F3

REFP

REFN

P12

P11

EP_SCK

TTX_SCL

Miscellaneous analog

Digital video output

Digital output

Internal Voltage Reference Output.

Video Pixel Output Port.

SPI Clock for External EDID Interface.

F4

Miscellaneous digital

Fast I²C Interface for Teletext Data Extraction. TTX_SCL is used as the I²C port serial

clock input.

F5

F6

F7

F8

DVDDIO

GND

AVDD

Power

Digital I/O Supply Voltage (3.3 V).

Ground.

Analog Supply Voltage (1.8 V).

Ground

Power

F9

F10

F11

F12

Rev. B | Page 15 of 28

ADV7842

Pin No. Mnemonic

Type

Description

F13

F14

F15

AIN12

AIN11

TRI4

Analog video input

Miscellaneous analog

Analog Video Input Channel.

Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the

I²C.)

F16

TRI3

Miscellaneous analog

Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the

I²C.)

G1

G2

G3

P14

P13

TTX_SDA

Digital video output

Miscellaneous digital

Video Pixel Output Port.

Fast I²C Interface for Teletext Data Extraction. TTX_SDA is used as the I²C port serial

data input/output pins.

G4

G5

G6

MCLK

DVDDIO

GND

Miscellaneous

Power

Ground

Audio Master Clock Output.

Digital I/O Supply Voltage (3.3 V).

Ground.

G7

GND

Ground

Ground.

G8

GND

Ground

Ground.

G9

GND

Ground

Ground.

G10

G11

G12

G13

G14

GND

AVDD

AIN10

SYNC4

Ground

Power

Analog video input

Miscellaneous analog

Ground.

Analog Supply Voltage (1.8 V).

Analog Video Input Channel.

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

G15

G16

H1

H2

H3

H4

H5

H6

H7

AIN9

AIN8

P16

P15

AP0

Analog video input

Digital video output

Miscellaneous

Power

Ground

Power

Miscellaneous analog

Analog video input

Miscellaneous analog

Analog Video Input Channel.

Video Pixel Output Port.

Audio Output Pin.

Digital I/O Supply Voltage (3.3 V).

Ground.

Analog Supply Voltage (1.8 V).

AP5

DVDDIO

GND

AVDD

TRI1

H8

H9

H10

H11

H12

H13

H14

H15

H16

Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via I²C.)

Analog Video Input Channel.

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

TRI2

AIN7

SYNC3

J1

J2

J3

J4

J5

J6

J7

J8

P18

P17

SCLK

AP4

DVDDIO

GND

VDD

GND

AVDD

AIN6

Digital video output

Miscellaneous digital

Miscellaneous

Power

Ground

Power

Ground

Power

Analog video input

Video Pixel Output Port.

Audio Serial Clock Output.

Audio Output Pin.

Digital I/O Supply Voltage (3.3 V).

Ground.

Digital Core Supply Voltage (1.8 V).

Ground.

Analog Supply Voltage (1.8 V).

Analog Video Input Channel.

J9

J10

J11

J12

J13

Rev. B | Page 16 of 28

ADV7842

Pin No. Mnemonic

Type

Description

J14

J15

AIN4

SYNC2

Analog video input

Miscellaneous analog

Analog Video Input Channel.

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

J16

K1

K2

K3

K4

K5

K6

K7

K8

GND

P20

P19

AP3

AP1

DVDDIO

VDD

GND

AVDD

AIN5

VS_IN1/TRI6

Ground

Ground.

Digital video output

Miscellaneous

Power

Ground

Power

Analog video input

Miscellaneous analog

Video Pixel Output Port.

Audio Output Pin.

Digital I/O Supply Voltage (3.3 V).

Digital Core Supply Voltage (1.8 V).

Ground.

Analog Supply Voltage (1.8 V).

Analog Video Input Channel.

K9

K10

K11

K12

K13

K14

VS on Graphics Port 1 (VS_IN1). The VS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI6). (Selection available

via the I²C.)

K15

K16

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

L12

L13

AIN2

AIN3

P22

P21

SCL

Analog video input

Digital video output

Miscellaneous digital

Miscellaneous

Power

Ground

Power

Analog monitor

output

Analog Video Input Channel.

Video Pixel Output Port.

I²C Port Serial Clock Input. SCL is the clock line for the control port.

AP2

Audio Output Pin.

DVDDIO

VDD

GND

AVDD

AOUT

Digital I/O Supply Voltage (3.3 V).

Digital Core Supply Voltage (1.8 V).

Ground.

Analog Supply Voltage (1.8 V).

Analog Monitor Output.

L14

HS_IN1/TRI5

Miscellaneous analog

HS on Graphics Port 1 (HS_IN1). The HS input signal is used for 5-wire timing mode.

Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI5). (Selection available

via the I²C.)

L15

L16

AIN1

SYNC1

Analog video input

Miscellaneous analog

Analog Video Input Channel.

This is a synchronization on green or luma input (SOG/SOY) used in embedded

synchronization mode. User configurable.

M1

M2

M3

M4

GND

P23

SDA

INT1

Ground

Ground.

Video Pixel Output Port.

I²C Port Serial Data Input/Output Pin. SDA is the data line for the control port.

Interrupt. This pin can be active low or active high. When status bits change, this pin is

triggered. The events that trigger an interrupt are under user control.

Digital video output

Miscellaneous digital

M5

M6

M7

M8

M9

M10

M11

DVDDIO

Power

Ground

Digital I/O Supply Voltage (3.3 V).

VDD_SDRAM

GND

External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V).

Ground.

Rev. B | Page 17 of 28

ADV7842

Pin No. Mnemonic

Type

Description

M12

M13

M14

M15

M16

N1

GND

LLC

Ground

Ground.

Ground

Ground.

Digital video output

Miscellaneous digital

Line-Locked Output Clock for the Pixel Data.

Video Pixel Output Port.

Interrupt. This pin can be active low or active high. When status bits change, this pin is

triggered. The events that trigger an interrupt are under user control.

N2

N3

P24

INT2

N4

N5

TEST4

RESET

Test

Connect this pin to ground.

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required

to reset the ADV7842 circuitry.

Miscellaneous digital

N6

N7

N8

N9

N10

TEST6

Test

Float this pin.

SDRAM_A8

SDRAM_A4

SDRAM_A0

SDRAM_CS

SDRAM interface

Address Output. Interface to external RAM address lines.

Chip Select. SDRAM_CS enables and disables the command decoder on the RAM. One

of four command signals to the external SDRAM.

N11

SDRAM_LDQS SDRAM interface

Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input

when reading data from external memory and an output when writing data to external

memory. It is edge aligned with data when reading from external memory and centered

with data when writing to external memory. SDRAM_LDQS corresponds to the data on

SDRAM_DQ7 to SDRAM_DQ0.

N12

N13

N14

N15

SDRAM_DQ4

SDRAM_DQ15 SDRAM interface

SDRAM_DQ11 SDRAM interface

SDRAM interface

Data Bus. Interface to external RAM 16-bit data bus.

Differential Clock Output. All address and control output signals to the RAM should be

sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK.

SDRAM_CK

SDRAM interface

N16

P1

P2

SDRAM_CKE

P25

P26

SDRAM interface

Digital video output

Test

Clock Enable. This pin acts as an enable to the clock signals of the external RAM.

Video Pixel Output Port.

P3

TEST5

Connect this pin to ground.

P4

P5

AVLINK

TEST7

Digital input/output

Test

Digital SCART Control Channel.

Float this pin.

P6

P7

P8

P9

SDRAM_A11

SDRAM_A7

SDRAM_A3

SDRAM_A10

SDRAM_RAS

SDRAM interface

Address Output. Interface to external RAM address lines.

Row Address Select Command Signal. One of four command signals to the external

SDRAM.

P10

P11

P12

P13

P14

P15

SDRAM_DQ7

SDRAM_DQ3

SDRAM_VREF

SDRAM_DQ12 SDRAM interface

SDRAM_UDQS SDRAM interface

SDRAM interface

Data Bus. Interface to external RAM 16-bit data bus.

1.25 V Reference for DDR SDRAM Interface or 1.65 V for SDR SDRAM Interface.

Data Bus. Interface to external RAM 16-bit data bus.

Upper Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input

when reading data from external memory and an output when writing data to external

memory. It is edge aligned with data when reading from external memory and centered

with data when writing to external memory. SDRAM_UDQS corresponds to the data

on SDRAM_DQ15 to SDRAM_DQ8.

P16

SDRAM_CK

SDRAM interface

Differential Clock Output. All address and control output signals to the RAM should be

sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK.

R1

R2

R3

R4

P27

P28

P30

P32

Digital video output

Video Pixel Output Port.

Rev. B | Page 18 of 28

ADV7842

Pin No. Mnemonic

Type

Description

R5

R6

R7

R8

R9

R10

P34

Digital video output

SDRAM interface

Video Pixel Output Port.

SDRAM_A9

SDRAM_A6

SDRAM_A2

SDRAM_BA1

SDRAM_CAS

Address Output. Interface to external RAM address lines.

Bank Address Output. Interface to external RAM bank address lines.

Column Address Select Command Signal. One of four command signals to the

external SDRAM.

R11

R12

R13

R14

R15

R16

T1

SDRAM_DQ6

SDRAM_DQ2

SDRAM_DQ0

SDRAM interface

Data Bus. Interface to external RAM 16-bit data bus.

Ground.

SDRAM_DQ13 SDRAM interface

SDRAM_DQ9

SDRAM_DQ8

GND

SDRAM interface

Ground

T2

T3

T4

T5

P29

P31

P33

P35

Digital video output

Ground

Video Pixel Output Port.

T6

GND

Ground.

T7

T8

T9

T10

SDRAM_A5

SDRAM_A1

SDRAM_BA0

SDRAM_WE

SDRAM interface

Address Output. Interface to external RAM address lines.

Bank Address Output. Interface to external RAM bank address lines.

Write Enable Output Command Signal. One of four command signals to the external

SDRAM.

T11

T12

T13

T14

T15

T16

SDRAM_DQ5

GND

SDRAM_DQ1

SDRAM_DQ14 SDRAM interface

SDRAM_DQ10 SDRAM interface

GND

SDRAM interface

Ground

SDRAM interface

Data Bus. Interface to external RAM 16-bit data bus.

Ground.

Data Bus. Interface to external RAM 16-bit data bus.

Ground.

Ground

Rev. B | Page 19 of 28

ADV7842

FUNCTIONAL OVERVIEW

HDMI RECEIVER

ANALOG FRONT END

The ADV7842 analog front end comprises four 170 MHz, 12-bit

ADCs that digitize the analog video signal before applying it to

the standard definition processor (SDP) or component

processor (CP). The analog front end uses differential channels

to each ADC to ensure high performance in a mixed-signal

application. The front end also includes a 12-channel input mux

that enables multiple video signals to be applied to the

ADV7842 without the requirement of an external mux.

The ADV7842 front end incorporates a 2:1 multiplexed HDMI

1.4 receiver with Xpressview fast switching technology and

support for HDMI 1.4 features such as 3D TV. Building on the

feature set of Analog Device existing HDMI devices, the ADV7842

also offers support for all HD TV formats up to 12-bit, 1080p

Deep Color and all display resolutions up to UXGA (1600 ×

1200 at 60 Hz). Xpressview fast switching technology, using

Analog Devices hardware-based HDCP engine that minimizes

software overhead, allows switching between the two input

ports in less than 1 second.

Current and voltage clamp control loops ensure that any DC

offsets are removed from the video signal. The clamps are

positioned in front of each ADC to ensure that the video signal

remains within the range of the converter.

With the inclusion of HDCP 1.4, the ADV7842 can receive

encrypted video content. The HDMI interface of the ADV7842

allows for authentication of a video receiver, decryption of

encoded data at the receiver, and renewal of that authentication

during transmission, as specified by the HDCP 1.4 protocol.

Repeater support is also offered by the ADV7842.

The ADCs are configured to run up to 8× oversampling mode

when decoding composite or S-Video inputs. For component

525i, 625i, 525p, and 625p sources, 4× oversampling is performed.

All other video standards are 1× oversampled. Oversampling

the video signals reduces the cost and complexity of external

antialiasing filters with the benefit of an increased signal-to-

noise ratio (SNR).

The HDMI receiver incorporates active equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. It is capable of

equalizing for cable lengths up to 30 meters to achieve robust

receiver performance at even the highest HDMI data rates.

Optional internal antialiasing filters with programmable

bandwidth are positioned in front of each ADC. These filters

can be used to band limit video signals, removing spurious, out-

of-band noise.

The HDMI receiver offers advanced audio functionality. It

supports multichannel I²S audio for up to eight channels. It also

supports a 6-DSD channel interface with each channel carrying

an over-sampled 1-bit representation of the audio signal as

delivered on SACD. The ADV7842 can also receive HBR audio

packet streams and outputs them through the HBR interface in

an SPDIF format conforming to the IEC60958 standard.

The ADV7842 can support the simultaneous processing of

CVBS and RGB standard definition signals to enable SCART

compatibility and overlay functionality. A combination of

CVBS and RGB inputs can be mixed with the output under the

control of I²C registers.

Analog front-end features include:

The receiver contains an audio mute controller that can detect a

variety of conditions that may result in audible extraneous noise

in the audio output. On detection of these conditions, the audio

signal can be ramped to mute to prevent audio clicks or pops.

•

Four 170 MHz, NSV, 12-bit ADCs that enable true 12-bit

video decoding

12-channel analog input mux that enables multiple source

connections without the requirement of an external mux

Four current and voltage clamp control loops that ensure

any dc offsets are removed from the video signal

SCART functionality and SD RGB overlay on CVBS

controlled by fast blank input

HDMI receiver features include:

•

2:1 multiplexed HDMI receiver

HDMI 1.4, 3D format support, DVI 1.0

225 MHz HDMI receiver

Integrated equalizer

High-bandwidth Digital Content Protection (HDCP 1.4)

also on background ports

•

SCART source switching detection through TRI1-TRI8 input

Four programmable antialiasing filters

•

Internal HDCP keys

36-/30-bit Deep Color support

PCM, HBR, DSD audio packet support

Repeater support

Internal E-EDID RAM

Hot plug assert output pin for each HDMI port

CEC controller

Rev. B | Page 20 of 28

ADV7842



Internal color bar test pattern

STANDARD DEFINITION PROCESSOR

Advanced TBC with frame synchronization, which ensures

nominal clock and data for nonstandard input

Interlace-to-progressive conversion for 525i and 625i

formats, enabling direct drive of HDMI Tx devices

Color controls that include hue, brightness, saturation, and

contrast

The SDP is capable of decoding a large selection of baseband

video signals in composite and S-Video formats. The video

standards supported by the SDP include PAL, PAL 60, PAL M,

PAL N, PAL NC, NTSC M/J, NTSC 4.43, and SECAM. The

ADV7842 can automatically detect the video standard and

process it accordingly.



The SDP has a 3D temporal comb filter and a five-line adaptive

2D comb filter that gives superior chrominance and luminance

separation when decoding a composite video signal. This highly

adaptive filter automatically adjusts its processing mode according

to the video standard and signal quality with no user intervention

required. The SDP has an IF filter block that compensates for

attenuation in the high frequency chroma spectrum due to a tuner

SAW filter. The SDP has specific luminance and chrominance

parameter controls for brightness, contrast, saturation, and hue.

COMPONENT PROCESSOR

The CP section of the ADV7842 is capable of decoding and

digitizing a wide range of component video formats in any color

space. Component video standards supported by the CP are

525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to

UXGA at 60 Hz, and other standards.

The any-to-any, 3 × 3 CSC matrix is placed between the analog

front end and the CP section. This enables YPbPr to RGB and

RGB to YCbCr conversions. Many other standards of color

space can be implemented using the color space converter.

The ADV7842 implements a patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7842 to track and decode poor quality video sources (such

as VCRs) and noisy sources (such as tuner outputs, VCR

players, and camcorders). Frame TBC ensures stable clock

synchronization between the decoder and the downstream

devices.

The CP section contains circuitry to enable the detection of

Macrovision encoded YPbPr signals for 525i, 625i, 525p, and

625p. It is designed to be fully robust when decoding these

types of signals. VBI extraction of CGMS data is performed by the

CP section of the ADV7842 for interlaced, progressive, and high

definition scanning rates. The data extracted can be read back over

the I²C interface.

The SDP also contains both a luma transient improvement (LTI)

block and a chroma transient improvement (CTI) block. These

increase the edge rate on the luma and chroma transitions,

resulting in a sharper video image. The SDP has a Macrovision®

detection circuit that allows Type I, Type II, and Type III

Macrovision protection levels. The decoder is also fully robust

to all Macrovision signal inputs.

CP features include:



525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other

HDTV formats are supported



Supports 720p 24 Hz/25 Hz formats

Manual adjustments, including gain (contrast),

offset (brightness), hue, and saturation

SDP features include:



Support for analog component YPbPr and RGB video

formats with embedded synchronization, composite

synchronization or separate HS and VS

Any-to-any, 3 × 3 CSC matrix that supports YCbCr-to-

RGB and RGB-to-YCbCr, fully programmable or

preprogrammable configurations

Synchronization source polarity detector (SSPD) that

determines the source and polarity of the synchronization

signals that accompany the input video

Macrovision copy protection detection on component

formats (525i, 625i, 525p, and 625p)

Free-run output mode that provides stable timing when no

video input is present or video lock is lost

Arbitrary pixel sampling support for nonstandard video

sources

170 MHz conversion rate, which supports RGB input

resolutions up to 1600 × 1200 at 60 Hz

Standard identification enabled by STDI block

RGB that can be color space converted to YCbCr and

decimated to a 4:2:2 format for video-centric back-end IC

interfacing



Advanced adaptive 3D comb (using either external DDR or

SDR SDRAM memory)



Adaptive 2D five-line comb filters for NTSC and PAL that

give superior chrominance and luminance separation for

composite video



Full automatic detection and autoswitching of all

worldwide standards (PAL, NTSC, and SECAM)

Automatic gain control with white peak mode that ensures

the video is always processed without loss of the video

processing range



Proprietary architecture for locking to weak, noisy, and

unstable sources from VCRs and tuners

IF filter block that compensates for high frequency luma

attenuation due to tuner SAW filter



LTI and CTI

Vertical and horizontal programmable luma peaking filters

8× oversampling (108 MHz) for CVBS, and S-Video modes

Line-locked clock (LLC) output

Free run output mode that provides stable timing when no

video input is present or video lock is lost



Rev. B | Page 21 of 28

ADV7842



Data enable (DE) output signal supplied for direct

connection to HDMI/DVI Tx IC

OTHER FEATURES

The ADV7842 has HS, VS, FIELD, and DE output signals with

programmable position, polarity, and width, and two I²C host

port interfaces (control and VBI). The ADV7842 has two

programmable interrupt request output pins, INT1 and INT2.

It also features a number of low power modes and a full power-

down mode. The ADV7842 is provided in a 17 mm × 17 mm,

RoHS-compliant BGA package, and is specified over the

−10°C to +70°C temperature range.



32-phase DLL that allows optimum pixel clock sampling

Automatic detection of synchronization source and

polarity by SSPD block

Contrast, brightness, hue, and saturation controls

Automatic or manual clamp-and-gain controls for graphics

modes



For more detailed product information about the ADV7842,

contact your local Analog Devices sales office.

Rev. B | Page 22 of 28

ADV7842

EXTERNAL MEMORY REQUIREMENTS

The ADV7842 uses external SDRAM for 3D comb and frame

synchronizer. The ADV7842 supports either SDR or DDR

SD RAM.

DOUBLE DATA RATE (DDR)

The ADV7842 can use DDR external memory to

simultaneously provide 3D comb and frame synchronizer

operation.

SINGLE DATA RATE (SDR)

The ADV7842 can use SDR external memory to provide 3D comb

or frame synchronizer operation nonconcurrently.

There is a 128 Mb DDR SDRAM minimum memory requirement.

The required memory architecture is four banks of 2 Mb × 16

(8M16) with a speed grade of 133 MHz at CL 2.5. Using 22 Ω series

termination resistors is recommended for this configuration

There is a 64 Mb SDR SDRAM minimum memory require-

ment. The required memory architecture is four banks of

1 Mb × 16 (4M16) with a speed grade of 133 MHz at CAS

latency (CL) 3. Using 22 Ω series termination resistors is recom-

mended for this configuration.

Recommended DDR memory that is compatible with the

ADV7842 includes the K4H561638J-LCB3 from Samsung, the

MT46V16M16P-6T from Micron Technology, Inc. and the

H5DU1262GTR-E3C from Hynix Inc.

Recommended SDR memory that is compatible with the

ADV7842 includes Winbond W9864G6PH-7.

Rev. B | Page 23 of 28

ADV7842

PIXEL INPUT/OUTPUT FORMATTING

The output section of the ADV7842 is highly flexible. The pixel

output bus can support up to 36-bit 4:4:4. The pixel data

supports both single and double data rates modes. In SDR

mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is

possible. In DDR mode, the pixel output port can be configured in

8-/10-/12-bit 4:2:2 modes or 24-/30-/36-bit 4:4:4 modes. Bus

rotation and bus inversion are also supported. All output modes

are controlled via I²C controls.

PIXEL DATA OUTPUT MODES FEATURES

The output pixel port features include the following:

•

8-/10-/12-bit ITU-R BT.656 4:2:2 with embedded time

codes and/or HS, VS, and FIELD output signals

SDR 16-/20-/24-/30-/36 bit with embedded time codes

and/or HS/CS and VS/FIELD pin timing

DDR 8-/10-/12-bit 4:2:2 with embedded time codes and/or

HS, VS, and FIELD output signals

DDR 24-/30-/36 bit 4:4:4 with embedded time codes

and/or HS, VS, and FIELD output signals

Note that DDR modes are supported up to 54 MHz by

characterization.

Rev. B | Page 24 of 28

ADV7842

REGISTER MAP ARCHITECTURE

map addresses must be programmed; this ensures no

addressing clashes on the system. Figure 9 shows the register

map architecture.

The registers of the ADV7842 are controlled via a 2-wire

serial (I²C-compatible) interface. The ADV7842 has

12 maps. The IO map has a static I²C address. All other

Table 8.

Register Map Name

Default Address

0x40

0x00

Programmable Address

Location at Which Address Can Be Programmed

Not applicable

IO Map

CP Map

SDP Map

SDP_IO Map

VDP Map

AVLINK Map

CEC Map

HDMI Map

EDID Map

Repeater Map

AFE, DPLL Map

InfoFrame Map

Not programmable

Programmable

IO map, Register 0xFD

IO map, Register 0xF1

IO map, Register 0xF2

IO map, Register 0xFE

IO map, Register 0xF3

IO map, Register 0xF4

IO map, Register 0xFB

IO map, Register 0xFA

IO map, Register 0xF9

IO map, Register 0xF8

IO map, Register 0xF5

IO

MAP

CP

MAP

SDP

MAP

SDP_IO

MAP

VDP

MAP

AVLINK

MAP

CEC

MAP

SLAVE

ADDRESS:

0x40

SLAVE

ADDRESS:

PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE

SCL

SDA

SLAVE

ADDRESS:

PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE PROGRAMMABLE

HDMI

MAP

EDID

MAP

REPEATER

MAP

AFE, DPLL

MAP

INFOFRAME

MAP

Figure 9. Register Map Architecture

Rev. B | Page 25 of 28

ADV7842

OUTLINE DIMENSIONS

A1 BALL

CORNER

17.20

17.00 SQ

16.80

16 14 12 10

15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

G

H

J

BALL A1

CORNER

15.00

BSC SQ

K

L

M

N

P

R

T

1.00

BSC

TOP VIEW

DETAIL A

BOTTOM VIEW

DETAIL A

1.10 MAX

0.25 MIN

1.70 MAX

0.30 MIN

0.70

0.60

0.50

COPLANARITY

0.20

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-192-AAF-1

Figure 10. 256-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-256-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Notes Temperature Range

Package Description

Package Option

BC-256-3

2, 3

ADV7842KBCZ-5

ADV7842KBCZ-5P

EVAL-ADV7842EB1Z

EVAL-ADV7842EB2Z

−10°C to +70°C

256-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Front-End Evaluation Board

2, 4, 5

3, 6, 7

5, 6, 8

Front-End Evaluation Board

¹Z = RoHS Compliant Part.

²Speed grade: 5 = 170 MHz.

³This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to

purchase any components with internal HDCP keys.

⁴HDCP functionality: P = no HDCP functionality (professional version).

⁵Professional version for non-HDCP encrypted applications. Purchaser is not required to be an HDCP adopter.

⁶An ATV motherboard is also required to process the ADV7842 digital outputs and achieve video output. An ATV video output board is optional to evaluate

performance through an HDMI transmitter and video encoder.

⁷Front-end board for the ATV video evaluation platform, fitted with ADV7842KBCZ-5 decoder.

⁸Front-end board for the ATV video evaluation platform, fitted with ADV7842KBCZ-5P decoder.

Rev. B | Page 26 of 28

ADV7842

NOTES

Rev. B | Page 27 of 28

ADV7842

NOTES

I²C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).

HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other

countries.

registered trademarks are the property of their respective owners.

D08849-0-1/11(B)

Rev. B | Page 28 of 28


型号：	ADV7842KBCZ-5
厂家：	ADI
描述：	Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics igitizer and 3D Comb Filter Decoder 双HDMI快速切换接收器，具有12位， 170 MHz的视频和图形igitizer和3D梳状滤波解码器解码器消费电路商用集成电路
文件：	总28页 (文件大小：406K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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