M5M5W816WG-55HI [RENESAS]
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM; 8388608 - BIT （ 524288 - WORD 16位） CMOS静态RAM
| 型号： | M5M5W816WG-55HI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FEATURES
DESCRIPTION
The M5M5W816 is a family of low v oltage 8-Mbit static RAMs
organized as 524288-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.18µm CMOS technology .
- Single 2.7~3.6V power supply
- Small stand-by current: 0.1µA (2V, ty p.)
- No clocks, No ref resh
The M5M5W816 is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectiv es.
- Data retention supply v oltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1#, S2, BC1# and BC2#
- Common Data I/O
M5M5W816WG is packaged in a CSP (chip scale package),
with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It giv es the best solution f or a
compaction of mounting area as well as f lexibility of wiring pattern
of printed circuit boards.
- Three-state outputs: OR-tie capability
- OE prev ents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 48ball 7.5mm x 8.5mm CSP
Activ e
(µA)
Stand-by current
Version,
Power
Access time
max.
current
Icc1
*(3.0V, ty p.)
Ratings (max.@ Vcc=3.6V)
* Ty pical(3.0V)
25°C 40°C 25°C 40°C 70°C 85°C
Part name
Operating
Supply
temperature
30mA
(10MHz)
5mA
M5M5W816WG -55HI
M5M5W816WG -70HI
M5M5W816WG -85HI
55ns
70ns
85ns
I-version
-40 ~ +85°C
0.5
1.0
5.0
8.0 20
40
2.7 ~ 3.6V
(1MHz)
* Typical parameter indicates the value for the center
of distribution, and is not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
A0
BC1#
DQ16
DQ14
GND
A1
A2
S2
OE#
A
B
C
D
E
F
A3
A5
A4
DQ1
S1#
BC2#
DQ15
DQ13
DQ12
DQ10
Pin
Function
A6
A7
DQ3
VCC
GND
DQ2
A0 ~ A18 Address input
DQ1 ~ DQ16
S1#
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
A17
DQ4
DQ5
NC or
GND
S2
VCC
A16
A15
A13
W#
DQ11
A14
A12
A9
DQ7
DQ6
DQ8
N.C.
OE#
BC1#
BC2#
Vcc
DQ9
A18
N.C.
A8
W#
G
H
A10
A11
GND
Ground supply
Outline : 48F7Q
NC : No Connection
*Don't connect E3 ball to voltage level more than 0V.
1
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
When setting BC1# and BC2# at a high lev el or S1# at a high
The M5M5W816WG is organized as 524288-words by 16-bit.
These dev ices operate on a single +2.7~3.6V power supply ,
and are directly TTL compatible to both input and output. Its
fully static circuit needs no clocks and no refresh, and
makes it useful.
lev el or S2 at a low lev el, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1#,
BC2# and S1#, S2.
The power supply current is reduced as low as 0.1µA(25°C,
ty pical), and the memory data can be held at +2.0V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S1#, S2 , W# and
OE#. Each mode is summarized in the function table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S1# and the high lev el S2. The address(A0~A18) must
be set up bef ore the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting W# at a high lev el
and OE# at a low lev el while BC1# and/or BC2# and S1# and
S2 are in an activ e state(S1#=L,S2=H).
When setting BC1# at the high lev el and other pins are in
an activ e stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-byte
are in a selectable mode and upper-by te are in a non-
selectable mode.
FUNCTION TABLE
S2
OE#
BC1# BC2#
S1#
W#
DQ1~8 DQ9~16
Icc
Mode
Non selection
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Standby
Standby
Standby
Standby
Activ e
H
L
H
X
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
L
H
H
H
L
X
X
X
H
H
H
H
L
L
L
L
L
X
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
X
L
H
X
L
Non selection
Non selection
Non selection
H
X
H
H
H
H
H
H
H
H
H
High-Z
Write
Read
Din
Dout High-Z Activ e
High-Z High-Z Activ e
High-Z Din
High-Z Dout
High-Z High-Z Activ e
Activ e
Activ e
Write
Read
H
X
L
Din
Din
Activ e
Activ e
Write
Read
L
L
Dout
Dout
L
H
High-Z High-Z Activ e
(note1) "H" and "L" in this table mean VIH and VIL, respectiv ely .
(note2) "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
524288 WORDS
x 16 BITS
A17
A18
-
DQ
9
CLOCK
GENERATOR
S1#
DQ
16
S2
BC1#
BC2#
W#
Vcc
GND
OE #
2
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Units
Conditions
Ratings
V
Supply v oltage
Input v oltage
With respect to GND
With respect to GND
With respect to GND
-0.3* ~ +4.6
cc
VI
-0.3* ~ Vcc + 0.3 (max. 4.6V)
V
Output v oltage
Power dissipation
VO
Pd
0 ~ Vcc
700
25°C
Ta=
mW
°C
Operating
Ta
- 40 ~ +85
temperature
Storage temperature
Tstg
°C
- 65 ~ +150
* -3.0V in case of AC (Pulse width < 30ns)
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Limits
Ty p
Symbol
Parameter
Conditions
Units
Min
Max
Vcc+0.2V
0.6
High-lev el input v oltage
Low-lev el input v oltage
High-lev el output v oltage
Low-lev el output v oltage
Input leakage current
2.2
-0.2 *
2.4
VIH
VIL
VOH
VOL
II
V
IOH= -0.5mA
IOL=2mA
0.4
±1
VI =0 ~ Vcc
µA
BC1# and BC2# =VIH or S1# =VIH or S2=VIL or OE# =VIH, VI/O=0 ~ Vcc
Output leakage current
IO
±1
BC1# and BC2# < 0.2V, S1# < 0.2V, S2 > Vcc-0.2V
f= 10MHz
-
-
-
-
30
5
50
15
50
15
Activ e supply current
( AC,MOS lev el )
other inputs < 0.2V or
Output - open (duty 100%)
> Vcc-0.2V
Icc1
Icc2
f= 1MHz
f= 10MHz
f= 1MHz
mA
BC1# and BC2#=VIL , S1#=VIL ,S2=VIH
other pins =VIH or VIL
Output - open (duty 100%)
30
5
Activ e supply current
( AC,TTL lev el )
(1)
S1# > Vcc - 0.2V,
~ +25°C
~ +40°C
0.5
-
-
5
8
S2 > Vcc - 0.2V,
other inputs = 0 ~ Vcc
1.0
(2)
(3)
S2 < 0.2V,
other inputs = 0 ~ Vcc
Stand by supply current
( AC,MOS lev el )
Icc3
µA
~ +70°C
~ +85°C
-
-
-
-
-
20
40
2
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
other inputs = 0 ~ Vcc
BC1# and BC2# =VIH or S1# =VIH or S2 =VIL
Other inputs= 0 ~ Vcc
Stand by supply current
( AC,TTL lev el )
mA
-
Icc4
Note 1: Direction for current flowing into IC is indicated as positive (no mark).
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and is not 100% tested.
* -1.0V in case of AC (Pulse width < 30ns)
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
CAPACITANCE
Limits
Ty p
Symbol
Conditions
Parameter
Units
pF
Min
Max
10
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
CI
CO
10
3
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
1TTL
Supply v oltage
2.7~3.6V
Input pulse
VIH=2.4V, VIL=0.4V
DQ
Input rise time and f all time
5ns
CL
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Reference lev el
Output loads
VOH=VOL=1.5V
Fig.1,CL=30pF
Including scope and
jig capacitance
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
70HI
55HI
85HI
Units
Parameter
Read cy cle time
Symbol
Max
Max
Max
Min
55
Min
70
Min
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
ta(A)
ta(S1)
ta(S2)
Address access time
55
55
55
55
55
30
20
20
20
20
20
70
70
70
70
70
35
25
25
25
25
25
85
85
85
85
85
45
30
30
30
30
30
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time after S1# high
Output disable time after S2 low
Output disable time after BC1# high
Output disable time after BC2# high
Output disable time after OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC1# low
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
10
10
5
10
10
5
10
10
5
Output enable time af ter BC2# low
Output enable time af ter OE# low
Data v alid time after address
5
5
5
ns
ns
5
10
5
10
5
10
(3) WRITE CYCLE
Limits
Units
70HI
85HI
55HI
Symbol
Parameter
Max
Max
Min
Min
Max
Min
55
45
0
50
50
50
50
50
30
0
ns
ns
ns
ns
ns
Write cy cle time
Write pulse width
70
55
0
65
65
65
65
65
35
0
85
60
0
70
70
70
70
70
45
0
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time from W# low
Output disable time from OE# high
Output enable time f rom W# high
ns
ns
ns
ns
ns
ns
ns
ns
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
0
0
0
25
25
30
30
20
20
5
5
5
5
5
5
ns
ns
Output enable time f rom OE# low
4
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~18
tv (A)
ta(A)
ta(BC1)or
ta(BC2)
BC1#,BC2#
(Note3)
(Note3)
tdis (BC1) or tdis (BC1)
ta(S1)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
tdis (S1)
ta(S2)
tdis (S2)
ta (OE)
OE#
(Note3)
(Note3)
ten (OE)
tdis (OE)
W# = "H" lev el
DQ1~16
ten (BC1)
ten (BC2)
VALID DATA
ten (S1)
ten (S2)
Write cycle
( W# control mode )
tCW
A0~18
tsu (BC1) or tsu(BC2)
BC1#,BC2#
(Note3)
(Note3)
tsu (S1)
tsu (S2)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
OE#
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
W#
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ1~16
tsu (D) th (D)
5
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
tCW
A0~18
tsu (BC1) or
tsu (BC2)
trec (W)
tsu (A)
BC1#,BC2#
S1#
(Note3)
(Note3)
(Note3)
(Note3)
S2
(Note5)
W#
(Note4)
tsu (D)
(Note3)
(Note3)
th (D)
DATA IN
STABLE
DQ1~16
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S1# low, S2 high overlaps BC1# and/or BC2# low and W# low.
Note 5: When the falling edge of W# is simultaneously or prior to the falling edge of BC1# and/or BC2# or the falling edge of S1#
or rising edge of S2, the outputs are maintained in the high impedance state.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
6
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S1# control mode)
tCW
A0~18
BC1#,BC2#
(Note3)
(Note3)
trec (W)
tsu (S1)
tsu (A)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
Write cycle (S2 control mode)
tCW
A0~18
BC1#,BC2#
(Note3)
(Note3)
trec (W)
tsu (S2)
tsu (A)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
7
2002.04.18
Ver. 6.0
MITSUBISHI LSIs
M5M5W816WG - 55HI, 70HI, 85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Vcc (PD)
VI (BC)
Parameter
Test conditions
Units
V
Ty p
Min
2.0
2.2
Max
Power down supply voltage
2.2V < Vcc(PD)
Byte control input BC1# &
BC2#
V
2.0V < Vcc(PD) < 2.2V
Vcc(PD)
Vcc(PD)
0.1
2.2V < Vcc(PD)
2.2
VI (S1)
VI (S2)
Chip select input S1#
Chip select input S2
2.0V < Vcc(PD) < 2.2V
V
0.2
1.5
3
Vcc=2.0V
~ +25°C
~ +40°C
-
-
-
-
(1)
(2)
(3)
S1# > Vcc - 0.2V,
other inputs = 0 ~ Vcc
S2 < 0.2V,
0.2
Power down
supply current
Icc (PD)
other inputs = 0 ~ Vcc
µA
-
-
15
30
~ +70°C
~ +85°C
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
other inputs = 0 ~ Vcc
Note 7: Typical parameter of Icc(PD) indicates the value for the
center of distribution, and is not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Symbol
Parameter
Units
Test conditions
Ty p
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
ns
ms
5
Power down recov ery time
(3) TIMING DIAGRAM
BC# control mode
Vcc
On the BC# control mode, the lev el of S1# and S2 must be f ixed at S1#, S2 > Vcc-0.2V or S2 < 0.2V.
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
BC1#
BC2#
BC1# , BC2# > Vcc-0.2V
S1# control mode
Vcc
On the S1# control mode, the lev el of S2 must be fixed at S2 > Vcc-0.2V or S2 < 0.2V.
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
S1# > Vcc-0.2V
S1#
S2 control mode
Vcc
2.7V
2.7V
S2
trec (PD)
tsu (PD)
0.2V
0.2V
S2 < 0.2V
8
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相关型号：
M5M5W816WG-55HI#BT
512KX16 STANDARD SRAM, 55ns, PBGA48, 7.50 X 8.50 MM, 0.75 MM PITCH, ROHS COMPLIANT, CSP-48
RENESAS
M5M5W817KT-70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
RENESAS
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