M5M5W817KT-70HI [RENESAS]
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM; 8388608 - BIT （ 524288 - WORD 16 - BIT / 10485776 -字×8位）的CMOS静态RAM
| 型号： | M5M5W817KT-70HI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM |
| 文件： | 总11页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5W817KT is a f amily of low v oltage 8Mbit static RAMs
organized as 524288-words by 16-bit / 1048576-words by 8-bit,
- Single 2.7~3.6V power supply
- Small stand-by current: 0.1µA (2.0V, ty p.)
- No clocks, No ref resh
fabricated by
technology .
Mitsubishi's high-performance 0.18µm CMOS
- Data retention supply v oltage =2.0~3.6V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1#, S2, BC1# and BC2#
- Common Data I/O
The M5M5W817KT is suitable f or memory applications where a
simple interfacing , battery operating and battery backup are
the important design objectiv es.
The M5M5W817KT is packaged in a 52pin-µTSOP with the outline
of 10.79mm x 10.49mm, and pin pitch of 0.40mm. It giv es the
best solution f or a compaction of mounting area as well as
flexibility of wiring pattern of printed circuit boards.
The operating temperature range is -40 ~ +85°C
- Three-state outputs: OR-tie capability
- OE prev ents data contention in the I/O bus
- By te f unction (x8 mode) av ailable by By te# & A-1.
- Process technology: 0.18µm CMOS
- Package: 52pin 10.79mm x 10.49mm µTSOP
[0.4mm pin pitch]
Stand-by current
Active
Power
Operating
Access time
max.
current
* Ty pical
Ratings (max.)
Part name
Icc1
Supply
temperature
25ºC 40ºC 25ºC 40ºC 70ºC 85ºC
(3.3V, Ty p.)
30mA
(10MHz)
5mA
-40 ~ +85°C
M5M5W817KT -70HI 2.7 ~ 3.6V
70ns
1.0
1.2
5
8
20
40
(1MHz)
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
PIN CONFIGURATION
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
2
A15
A14
A13
A12
A11
A10
A9
A16
BYTE#
BC2#
3
4
GND
5
BC1#
6
DQ16/A-1
7
DQ8
8
A8
DQ15
Pin
Function
9
NC
S1#
W#
NC
DQ7
A0 ~ A18 Address input
10
11
12
13
DQ14
Data input / output
DQ1 ~ DQ16
DQ6
DQ13
DQ5
Chip select input 1
Chip select input 2
Write control input
S1#
S2
NC
VCC 14
NC
W#
S2
NC
NC
15
16
DQ12
DQ4
OE#
Output enable input
17
18
19
20
21
22
23
24
25
26
DQ11
DQ3
BC1#
BC2#
Lower By te (DQ1 ~ 8)
A18
Upper By te (DQ9 ~ 16)
34
33
32
31
30
29
28
27
DQ10
DQ2
DQ9
DQ1
OE#
A17
A7
A6
A5
A4
A3
A2
A1
BYTE#
Vcc
By te (x8 mode) enable input
Power supply
GND
Ground supply
GND
NC
A0
Outline: 52PTG-A
N C : No Connection
10.49mm
1
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W817KT is organized as 524288-words by 16-
bit / 1048576-words by 8-bit. These dev ices operate on a
single +2.7~3.6V power supply, and are directly TTL
compatible to both input and output. Its f ully static circuit
needs no clocks and no ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S1#, S2 , W#,
OE# and BYTE#. Each mode is summarized in the function
table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S1# and the high lev el S2. The address (A-1~A18 :
By te mode, A0~A18 : Word mode) must be set up before
the write cycle and must be stable during the entire cy cle.
A read operation is executed by setting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S1#and S2 are in an activ e state (S1#=L, S2=H).
When setting BC1# and BC2# at a high lev el or S1# at
a high lev el or S2 at a low lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled.
In this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by
BC1#, BC2# and S1#, S2.
The power supply current is reduced as low as 0.1µA
(25°C, ty pical), and the memory data can be held at +2.0V
power supply, enabling battery back-up operation during
power f ailure or power-down operation in the non-selected
mode.
When setting BYTE# at a low lev el, the f unction will be
in the x8 mede, which is, DQ1-8 are av ailable and DQ9-16
are not av ailable. In the x8 mode, A-1 is used as the
additional address. During the activ e f unction for x8 mode,
BC1# BC2# must be low lev el.
FUNCTION TABLE
S1#
H
X
X
L
S2 BYTE# BC1# BC2# W#
OE#
X
X
X
X
L
Mode
DQ1~8 DQ9~15 DQ16
Icc
H
L
H or L
X
X
H
L
X
X
H
H
H
H
L
X
X
X
L
Non selection High-Z High-Z High-Z
Non selection High-Z High-Z High-Z
Non selection High-Z High-Z High-Z
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
H or L
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
Write
Read
-------
Write
Read
-------
Write
Read
-------
Write
Read
-------
Din
High-Z High-Z
High-Z High-Z
L
H
L
H
H
L
Dout
L
H
L
H
X
L
High-Z High-Z High-Z
L
H
H
H
H
L
High-Z
High-Z
Din
Din
L
H
L
H
H
L
Dout
Dout
L
H
L
X
X
L
High-Z High-Z High-Z
L
H
L
Din
Din
Din
L
H
L
L
H
H
L
Dout
Dout
Dout
L
H
L
L
X
X
L
High-Z High-Z High-Z
L
L
L
L
Din
High-Z
High-Z
A-1
A-1
A-1
L
L
L
L
H
H
Dout
L
L
L
L
H
High-Z High-Z
Note1 : "H" and "L" in this table mean VIH and VIL, respectiv ely .
Note2 : "X" in this table should be "H" or "L".
2
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
BLOCK DIAGRAM
8MS
DQ
1
A0
524288WORDS X
16 BITS
or
DQ
DQ
8
9
1048576WORDS X
8 BITS
A18
S2
S1#
CLOCK
GENERATOR
DQ
A-1
16 /
BC1#
x8/x16
Switching
circuit
BC2#
VCC
GND
BYTE#
W#
OE#
3
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Units
V
Conditions
Ratings
- 0.3* ~ +4.6
- 0.3* ~ Vcc + 0.3 (max. 4.6V)
0 ~ Vcc
V
Supply v oltage
Input v oltage
With respect to GND
With respect to GND
With respect to GND
Ta = 25°C
cc
VI
Output v oltage
VO
Pd
Power dissipation
700
mW
ºC
-40 ~ +85
- 65 ~ +150
Operating temperature
Storage temperature
Ta
Tstg
ºC
<
* -3.0V in case of AC (Pulse width
30ns)
=
DC ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC Vcc=2.7V~3.6V,unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Units
Min
2.2
Ty p
Max
Vcc+0.2V
0.6
High-lev el input v oltage
Low-lev el input v oltage
High-level output voltage
VIH
VIL
VOH
VOL
II
- 0.2 *
2.4
V
IOH= - 0.5mA
IOL= 2.0mA
VI =0 ~ Vcc
0.4
±1
Low-lev el output v oltage
Input leakage current
µA
Output leakage current
BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc
IO
±1
BC1# and BC2# < 0.2V, S1# < 0.2V, S2 >Vcc-0.2V
f= 10MHz
f= 1MHz
f= 10MHz
f= 1MHz
-
-
-
-
30
5
50
15
50
15
Activ e supply current
( AC,MOS lev el )
other inputs
< 0.2V or > Vcc-0.2V
Icc1
Icc2
Output - open (duty 100%)
mA
BC1# and BC2#=VIL , S1#=VIL ,S2=VIH
other pins =VIH or VIL
Output - open (duty 100%)
30
5
Activ e supply current
( AC,TTL lev el )
S1# > Vcc - 0.2V and S2 > Vcc - 0.2V,
(1)
~ +25°C
-
1.0
5
BYTE# > Vcc - 0.2V or < 0.2V,
other inputs = 0 ~ Vcc
S2 < 0.2V,
BYTE# > Vcc - 0.2V or < 0.2V,
other inputs = 0 ~ Vcc
(2)
(3)
~ +40°C
~ +70°C
~ +85°C
-
-
-
1.2
8
Stand by supply current
( AC,MOS lev el )
Icc3
µA
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
BYTE# > Vcc - 0.2V or < 0.2V,
other inputs = 0 ~ Vcc
-
-
20
40
BC1# and BC2# =VIH or S1# =VIH or S2=VIL
BYTE# > Vcc - 0.2V or < 0.2V,
Other inputs= 0 ~ Vcc
Stand by supply current
( AC,TTL lev el )
Icc4
-
-
2.0
mA
<
* -1.0V in case of AC (Pulse width
30ns)
=
Note 3: Direction for current flowing into IC is indicated as positive (no mark)
Note 4: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
CAPACITANCE (Ta=-40~+85ºC Vcc=2.7V~3.6V,unless otherwise noted)
Limits
Symbol
Conditions
Parameter
Units
pF
Ty p
Min
Max
10
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
CI
CO
10
4
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=-40~+85ºC, Vcc=2.7V~3.6V,unless otherwise noted)
(1) TEST CONDITIONS
1TTL
Supply v oltage
2.7~3.6V
DQ
Input pulse
VIH=2.7V, VIL=0.2V
5ns
CL
Including scope and
Input rise time and f all time
Transition is measured ±200mV from
Reference lev el
Output loads
VOH=VOL=1.5V
steady state voltage.(for ten,tdis)
jig capacitance
Fig.1,CL=30pF
Fig.1 Output load
CL=5pF (for ten,tdis)
(2) READ CYCLE
Limits
70HI
Max
Units
ns
Parameter
Symbol
Min
70
Read cy cle time
tCR
ta(A)
70
70
70
70
70
35
25
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select 1 access time
Chip select 2 access time
ta(S1)
ta(S2)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time after S1# high
Output disable time after S2 low
Output disable time after BC1# high
Output disable time after BC2# high
Output disable time after OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC1# low
Output enable time af ter BC2# low
Output enable time af ter OE# low
Data v alid time after address
10
10
5
5
5
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
10
(3) WRITE CYCLE
Limits
70HI
Max
Units
Symbol
Parameter
Min
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time from W# low
Output disable time from OE# high
Output enable time f rom W# high
70
55
ns
ns
tCW
tw(W)
ns
ns
ns
tsu(A)
0
65
65
65
65
65
35
0
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S1)
tsu(S2)
tsu(D)
ns
ns
ns
ns
ns
ns
ns
ns
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
0
25
25
5
5
ns
ns
Output enable time f rom OE# low
5
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
(4) Byte# function
Limits
Ty p
Symbol
Units
Parameter
Test conditions
Min
5
Max
BYTE# set up time
tsu (BYTE)
ms
ms
BYTE# recov ery time
5
trec (BYTE)
(5) TIMING DIAGRAMS
BYTE#
S2
S1#
tsu (BYTE)
trec (BYTE)
BYTE#
Read cycle
A0~18
(Word Mode)
tCR
A-1~18
tv (A)
(Byte Mode)
ta(A)
ta(BC1)or
BC1#,
BC2#
ta(BC2)
(Note5)
(Note5)
tdis (BC1) or tdis (BC2)
ta(S1)
S1#
S2
(Note5)
(Note5)
(Note5)
(Note5)
tdis (S1)
ta(S2)
tdis (S2)
ta (OE)
OE#
(Note5)
(Note5)
ten (OE)
tdis (OE)
W# = "H" lev el
ten (BC1)
ten (BC2)
DQ1~16
(Word Mode)
VALID DATA
ten (S1)
ten (S2)
DQ1~8
(Byte Mode)
6
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle( W# control mode )
tCW
A0~18
(Word Mode)
A-1~18
(Byte Mode)
tsu (BC1) or tsu(BC2)
BC1#,
BC2#
(Note5)
(Note5)
(Note5)
(Note5)
(Note5)
(Note5)
tsu (S1)
tsu (S2)
S1#
S2
OE#
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
W#
ten(OE)
ten (W)
tdis(OE)
DQ1~16
(Word Mode)
DATA IN
STABLE
DQ1~8
(Byte Mode)
tsu (D) th (D)
Write cycle (BC# control mode)
tCW
A0~18
(Word Mode)
A-1~18
(Byte Mode)
tsu (BC1) or
tsu (BC2)
trec (W)
tsu (A)
BC1#,
BC2#
S1#
(Note5)
(Note5)
(Note5)
(Note5)
S2
(Note5)
(Note7)
W#
(Note6)
tsu (D)
(Note5)
DQ1~16
th (D)
(Word Mode)
DATA IN
STABLE
DQ1~8
(Byte Mode)
Note 5: Hatching indicates the state is "don't care".
Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low.
Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the falling edge of
S1# or rising edge of S2, the outputs are maintained in the high impedance state.
Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode.
7
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S1# control mode)
tCW
A0~18
(Word Mode)
A-1~18
(Byte Mode)
BC1#,
BC2#
(Note5)
(Note5)
trec (W)
tsu (S1)
tsu (A)
S1#
S2
(Note5)
(Note5)
(Note5)
(Note5)
(Note7)
W#
(Note6)
tsu (D)
th (D)
DQ1~16
(Word Mode)
DATA IN
STABLE
DQ1~8
(Byte Mode)
Write cycle (S2 control mode)
A0~18
(Word Mode)
tCW
A-1~18
(Byte Mode)
BC1#,
BC2#
(Note5)
(Note5)
(Note5)
trec (W)
tsu (S2)
tsu (A)
S1#
S2
(Note5)
(Note7)
W#
(Note6)
tsu (D)
(Note5)
(Note5)
th (D)
DQ1~16
(Word Mode)
DATA IN
STABLE
DQ1~8
(Byte Mode)
8
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC, Vcc=2.7V~3.6V,unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Units
V
Ty p
Min
2.0
Max
Power down supply voltage
Vcc (PD)
VI (BC)
Byte control input
BC1# & BC2#
2.0
2.0
V
V
VI (S1#)
VI (S2)
Chip select input S1#
Chip select input S2
0.2
Vcc=2.0V
~ +25°C
~ +40°C
-
-
3.0
6.0
0.2
0.4
(1)
S1# > Vcc - 0.2V, BYTE# > Vcc - 0.2V or < 0.2V
other inputs = 0 ~ Vcc
(2)
(3)
S2 < 0.2V , BYTE# > Vcc - 0.2V or < 0.2V
other inputs = 0 ~ Vcc
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
BYTE# > Vcc - 0.2V or < 0.2V
other inputs = 0 ~ Vcc
Power down
supply current
Icc (PD)
µA
~ +70°C
~ +85°C
-
-
-
-
30
60
Note 9: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 2.0V, and not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Symbol
Parameter
Units
Test conditions
Ty p
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
ns
ms
5
Power down recov ery time
(3) TIMING DIAGRAM
BC# control mode
Vcc
note10:On the BC# control mode, the lev el of S1# and S2 must be f ixed
at S1#, S2 > Vcc-0.2V or S2 <0.2V
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
BC1#
BC2#
BC1# , BC2# > Vcc - 0.2V
note11:On the S1# control mode, the lev el of S2 must be f ixed
at S2 > Vcc-0.2V or S2 <0.2V
S1# control mode
Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
S1# > Vcc - 0.2V
S1#
S2 control mode
Vcc
2.7V
2.7V
S2
tsu (PD)
trec (PD)
0.2V
0.2V
S2 < 0.2V
9
MITSUBISHI LSIs
2002.9.3 Ver. 0.0
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products betterand more
reliable, but there isalways the possibility that trouble may occur with them. Trouble with semiconductors may lead
to personal injury, fire or property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's
rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application
examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms
represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric
Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or
errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means,
including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts,
programs, and algorithms, please be sure to evaluate all information as a total system before making a final
decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system
that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product
contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in
part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported
under a license from the Japanese government and cannot be imported into a country other than the approved
destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for
further details on these materials or the products contained therein.
相关型号：
©2020 ICPDF网 联系我们和版权申明