M5M5Y416CWG-55HI [RENESAS]
256KX16 STANDARD SRAM, 55ns, PBGA48, 7 X 8.50 MM, CSP-48;
| 型号： | M5M5Y416CWG-55HI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 256KX16 STANDARD SRAM, 55ns, PBGA48, 7 X 8.50 MM, CSP-48 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
FEATURES
DESCRIPTION
- Single 1.65~2.3V power supply
The M5M5Y416C is a f amily of low v oltage 4-Mbit static RAMs
organized as 262144-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.18µm CMOS technology .
- Small stand-by current: 0.1µA (2.3V, ty p.)
- No clocks, No ref resh
- Data retention supply v oltage =1.3V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1#, S2, BC1# and BC2#
- Common Data I/O
The M5M5Y416C is suitable f or memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectiv es.
M5M5Y416CWG is packaged in a CSP (chip scale package),
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It giv es the best solution f or
a compaction
- Three-state outputs: OR-tie capability
- OE prev ents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 48ball 7.0mm x 8.5mm CSP
of mounting area as well as f lexibility of wiring pattern of printed
circuit boards.
Activ e
Stand-by current (µA)
Version,
Power
Access time
max.
current
Ratings (max.)
* Ty pical
Part name
Operating
Icc1
Supply
25°C 40°C 25°C 40°C 70°C 85°C
(2.3V, max)
temperature
30mA
(10MHz)
3mA
55ns
70ns
M5M5Y416CWG -55HI 1.65 ~ 2.3V
I-version
-40 ~ +85°C
0.1
0.2
1
2
8
15
1.65 ~ 2.3V
M5M5Y416CWG -70HI
(1MHz)
* Typical parameter indicates the value for the center
of distribution at 2.3V, and not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
A0
A
BC1#
A1
A2
S2
OE#
Pin
Function
DQ16
A3
A5
A4
A6
S1#
DQ1
DQ3
BC2#
DQ15
B
C
D
E
F
A0 ~ A17 Address input
DQ1 ~ DQ16
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
DQ14
DQ2
S1#
S2
A17
GND DQ13
A7
VCC
GND
DQ4
DQ5
DQ7
W#
OE
NCor
GND*
VCC
DQ11
DQ9
N C
A16
A15
A13
A10
DQ12
DQ10
BC1#
BC2#
Vcc
A14
A12
A9
DQ6
DQ8
N.C.
N.C.
A8
W#
G
H
GND
Ground supply
A11
Outline: 48FJA
NC: No Connection
*Don't connect E3 ball to v oltage lev el more than 0V
1
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
When setting BC1# and BC2# at a high lev el or S1# at a
The M5M5Y416CWG is organized as 262144-words by
16-bit. These dev ices operate on a single +1.65~2.3V
power supply, and are directly TTL compatible to both
input and output. Its f ully static circuit needs no clocks
and no ref resh, and makes it usef ul.
high lev el or S2 at a low lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by BC1#, BC2# and S1#, S2.
The operation mode are determined by a combination
of the dev ice control inputs BC1# , BC2# , S1# , S2 ,
W# and OE#. Each mode is summarized in the function
table.
The power supply current is reduced as low as 0.1µA(25°C,
Vcc=1.65V, ty pical), and the memory data can be held at
+1.3V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
A write operation is executed whenev er the low lev el
W# ov erlaps with the low lev el BC1# and/or BC2# and
the low lev el S1# and the high lev el S2. The
address(A0~A17) must be set up before the write cycle
and must be stable during the entire cycle.
selected mode.
FUNCTION TABLE
W#
S1# S2
BC1#BC2#
OE#
DQ1~8 DQ9~16
Icc
Mode
Non selection
Non selection
Non selection
Non selection
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Standby
Standby
Standby
Standby
Activ e
H
L
H
X
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
L
H
H
H
L
X
X
X
H
H
H
H
L
L
L
L
L
X
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
X
L
H
X
L
A read operation is executed by setting W at a high
lev el and OE# at a low lev el while BC1# and/or BC2#
and S1# and S2 are in an activ e state(S1=L,S2=H).
When setting BC1# at the high lev el and other pins
are in an activ e stage , upper-byte are in a selectable
mode in which both reading and writing are enabled, and
lower-byte are in a non-selectable mode. And when
setting BC2# at a high lev el and other pins are in an
activ e stage, lower-byte are in a selectable mode and
upper-by te are in a non-selectable mode.
H
X
H
H
H
H
H
H
H
H
H
High-Z
Din
Write
Read
Dout High-Z Activ e
High-Z High-Z Activ e
High-Z Din
High-Z Dout
High-Z High-Z Activ e
Activ e
Activ e
Write
Read
H
X
L
Write
Read
Din
Din
Activ e
Activ e
L
L
Dout
Dout
L
H
High-Z High-Z Activ e
note1: "H" and "L" in this table mean VIH and VIL, respectiv ely .
note2: "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
262144 WORDS
x 16 BITS
A16
A17
-
DQ
9
CLOCK
GENERATOR
S1#
S2
DQ
16
BC1#
BC2#
W#
Vcc
GND
OE#
2
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Units
Conditions
Ratings
V
Supply v oltage
Input v oltage
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
-0.3* ~ +2.7
cc
VI
-0.3* ~ Vcc + 0.3 (max. 2.7V)
V
Output v oltage
Power dissipation
Operating
VO
Pd
0 ~ Vcc
700
mW
I-v ersion
- 40 ~ +85
°C
°C
Ta
temperature
Storage temperature
Tstg
- 65 ~ +150
<
* -0.7V in case of AC (Pulse width 30ns)
=
( Vcc=1.65~ 2.3V, unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Limits
Units
Symbol
Parameter
Conditions
Min
Ty p
Max
0.7xVcc
-0.2 *
1.3
High-lev el input v oltage
Low-lev el input v oltage
High-level output voltage
VIH
VIL
VOH
VOL
II
Vcc+0.2
0.4
V
IOH= -0.1mA
IOL=0.1mA
VI =0 ~ Vcc
Low-lev el output v oltage
Input leakage current
Output leakage current
0.2
±1
±1
30
3
µA
BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc
IO
<
<
BC1# and BC2# 0.2V, S1# 0.2V, S2 Vcc-0.2V
=
=
f= 10MHz
f= 1MHz
f= 10MHz
f= 1MHz
~ +25°C
-
-
-
-
-
18
1.5
18
Activ e supply current
( AC,MOS lev el )
>
<
other inputs 0.2V or
Vcc-0.2V
Icc1
Icc2
=
=
Output - open (duty 100%)
mA
BC1# and BC2#=VIL , S1#=VIL ,S2=VIH
other pins =VIH or VIL
Output - open (duty 100%)
30
3
Activ e supply current
( AC,TTL lev el )
1.5
0.1
>
(1)
S1# Vcc - 0.2V,
=
1
>
S2 Vcc - 0.2V,
=
other inputs = 0 ~ Vcc
-
-
-
~ +40°C
~ +70°C
~ +85°C
0.2
2
(2)
(3)
<
S2 0.2V,
=
Stand by supply current
( AC,MOS lev el )
Icc3
Icc4
µA
other inputs = 0 ~ Vcc
-
-
8
>
BC1# and BC2# Vcc - 0.2V
=
>
<
S1# 0.2V, S2 Vcc - 0.2V
=
=
15
other inputs = 0 ~ Vcc
BC1# and BC2#=VIH or S1#=VIH or S2=VIL
Other inputs= 0 ~ Vcc
Stand by supply current
( AC,TTL lev el )
mA
-
-
0.5
<
* -0.7V in case of AC (Pulse width 30ns)
=
Note 3: Direction for current flowing into IC is indicated as positive (no mark)
Note 4: Typical parameter indicates the value for the center of distribution at 2.3V, and not 100% tested.
(Vcc=1.65 ~ 2.3V, unless otherwise noted)
CAPACITANCE
Limits
Ty p
Symbol
Conditions
Parameter
Units
pF
Min
Max
10
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
CI
CO
10
3
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=1.65 ~ 2.3V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply v oltage
1.65~2.3V
1TTL
DQ
Input pulse
VIH=0.7 x Vcc+0.2V, VIL=0.2V
Input rise time and f all time
5ns
CL
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Reference lev el
Output loads
VOH=VOL=0.9V
Fig.1,CL=30pF
Including scope and
jig capacitance
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
70HI
Min
55HI
Min
Units
Parameter
Symbol
Max
Max
tCR
ta(A)
ta(S1)
ta(S2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cy cle time
Address access time
55
70
55
55
55
55
55
30
20
20
20
20
20
70
70
70
70
70
35
25
25
25
25
25
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time after S1# high
Output disable time after S2 low
Output disable time after BC1# high
Output disable time after BC2# high
Output disable time after OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC#1 low
Output enable time af ter BC2# low
Output enable time af ter OE# low
Data v alid time after address
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
5
5
5
5
5
5
10
10
5
5
5
tV(A)
10
ns
(3) WRITE CYCLE
Limits
Units
55HI
70HI
Symbol
Parameter
Min
55
45
Max
Min
70
55
Max
ns
ns
ns
ns
ns
Write cy cle time
Write pulse width
tCW
tw(W)
tsu(A)
Address setup time
0
0
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time from W# low
Output disable time from OE# high
Output enable time f rom W# high
50
50
50
50
50
25
0
65
65
65
65
65
30
0
ns
ns
ns
ns
ns
ns
ns
ns
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
0
0
20
20
25
25
5
5
5
5
ns
ns
Output enable time f rom OE# low
4
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~17
tv (A)
ta(A)
ta(BC1)or
ta(BC2)
BC1#,BC2#
(Note5)
(Note5)
tdis (BC1) or tdis (BC1)
ta(S1)
S1#
S2
(Note5)
(Note5)
(Note5)
(Note5)
tdis (S1)
ta(S2)
tdis (S2)
ta (OE)
OE#
(Note5)
(Note5)
ten (OE)
tdis (OE)
W# = "H" lev el
DQ1~16
ten (BC1)
ten (BC2)
VALID DATA
ten (S1)
ten (S2)
Write cycle
( W# control mode )
tCW
A0~17
tsu (BC1) or tsu(BC2)
BC1#,BC2#
(Note5)
(Note5)
tsu (S1)
tsu (S2)
S1#
S2
(Note5)
(Note5)
(Note5)
(Note5)
OE#
W#
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ1~16
tsu (D) th (D)
5
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
tCW
A0~17
tsu (BC1) or
tsu (BC2)
trec (W)
tsu (A)
BC1#,BC2#
S1#
(Note5)
(Note5)
(Note5)
(Note5)
S2
(Note7)
W#
(Note6)
tsu (D)
(Note5)
(Note5)
th (D)
DATA IN
STABLE
DQ1~16
Note 5: Hatching indicates the state is "don't care".
Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low.
Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the falling
edge of S1# or rising edge of S2, the outputs are maintained in the high impedance state.
Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S1# control mode)
tCW
A0~17
BC1#,BC2#
(Note5)
(Note5)
trec (W)
tsu (S1)
tsu (A)
S1#
S2
(Note5)
(Note5)
(Note5)
(Note5)
(Note7)
W#
(Note6)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
Write cycle (S2 control mode)
tCW
A0~17
BC1#,BC2#
(Note5)
(Note5)
trec (W)
tsu (S2)
tsu (A)
S1#
S2
(Note5)
(Note5)
(Note5)
(Note5)
(Note7)
W#
(Note6)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
7
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Vcc (PD)
VI (BC)
Parameter
Test conditions
Units
V
Ty p
Min
1.3
Max
Power down supply voltage
Vcc(PD)
Vcc(PD)
Vcc(PD)
Vcc(PD)
0.7xVcc
1.65V
1.3V
Byte control input BC1# &
BC2#
V
1.65V
1.65V
Vcc(PD)
Vcc(PD)
0.7xVcc
1.65V
1.3V
VI (S1)
VI (S2)
Chip select input S1#
Chip select input S2
V
V
0.2
0.7
Vcc=1.65V
0.1
0.2
-
-
-
-
-
~ +25°C
~ +40°C
~ +70°C
~ +85°C
>
(1)
(2)
(3)
S1# Vcc - 0.2V,
=
other inputs = 0 ~ Vcc
1.5
5
Power down
<
S2 0.2V,
=
Icc (PD)
other inputs = 0 ~ Vcc
µA
supply current
>
BC1# and BC2# Vcc - 0.2V
=
>
<
S1# 0.2V, S2 Vcc - 0.2V
=
=
-
10
other inputs = 0 ~ Vcc
Note 9: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 1.65V, and not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Symbol
Parameter
Units
Test conditions
Ty p
Min
0
Max
tsu (PD)
Power down set up time
ns
ms
5
Power down recov ery time
trec (PD)
(3) TIMING DIAGRAM
>
BC# control mode On the BC# control mode, the level of S1# and S2 must be fixed at S1#, S2 Vcc-0.2V or S2 0.2V
=
Vcc
1.65V
1.65V
tsu (PD)
trec (PD)
0.7 x Vcc
0.7 x Vcc
BC1#
BC2#
>
BC1# , BC2# Vcc-0.2V
=
>
S1# control mode On the S1# mode, the level of S2 must be fixed at S2 Vcc-0.2V or S2 0.2V.
=
Vcc
1.65V
1.65V
tsu (PD)
trec (PD)
0.7 x Vcc
0.7 x Vcc
>
S1# Vcc-0.2V
S1#
=
S2 control mode
Vcc
S2
1.65V
1.65V
tsu (PD)
trec (PD)
0.2V
0.2V
S2 0.2V
8
MITSUBISHI LSIs
2002.04.05
Ver. 5.1
M5M5Y416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
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