M5M5Y5636TG-25_技术文档

MITSUBISHI LSIs

2001.June Rev.0.0

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Some parametric limits are subject to change.

M5M5Y5636TG – 25,22,20

Notice: This is not final specification.

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

DESCRIPTION

FUNCTION

The M5M5Y5636TG is a family of 18M bit synchronous SRAMs

organized as 524288-words by 36-bit. It is designed to eliminate

dead bus cycles when turning the bus around between reads and

writes, or writes and reads. Mitsubishi's SRAMs are fabricated

with high performance, low power CMOS technology, providing

greater reliability. M5M5Y5636TG operates on a single 1.8V

power supply and are 1.8V CMOS compatible.

Synchronous circuitry allows for precise cycle control triggered

by a positive edge clock transition.

Synchronous signals include : all Addresses, all Data Inputs,

all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV),

Byte Write Enables (BWa#, BWb#, BWc#, BWd#), Echo Clock

outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#). Write

operations are controlled by the eight Byte Write Enables (BWa#

- BWd#) and Read/Write(W#) inputs. All writes are conducted

with on-chip synchronous self-timed write circuitry.

The Echo Clocks are delayed copies of the RAM clock, CLK.

Echo Clocks are designed to track changes in output driver

delays due to variance in die temperature and supply voltage.

The ZQ pin supplied with selectable impedance drivers, allows

selection between nominal drive strength (ZQ LOW) for multi-

drop bus application and low drive strength (ZQ floating or HIGH)

point-to-point applications.

The sense of two User-Programmable Chip Enable inputs (E2,

E3), whether they function as active LOW or active HIGH inputs,

is determined by the state of the programming inputs, EP2 and

EP3.

The Linear Burst order (LBO#) is DC operated pin. LBO# pin

will allow the choice of either an interleaved burst, or a linear

burst.

FEATURES

• Fully registered inputs and outputs for pipelined operation

• Fast clock speed: 250, 225, and 200 MHz

• Fast access time: 2.6, 2.8, 3.2 ns

• Single 1.8V +150/-100mV power supply VDD

• Separate VDDQ for 1.8V I/O

• Individual byte write (BWa# - BWd#) controls may be tied

LOW

• Single Read/Write control pin (W#)

• Echo Clock outputs track data output drivers

• ZQ mode pin for user-selectable output drive strength

• 2 User programmable chip enable inputs for easy depth

expansion

• Linear or Interleaved Burst Modes

• JTAG boundary scan support

All read, write and deselect cycles are initiated by the ADV

Low input. Subsequent burst address can be internally generated

as controlled by the ADV HIGH input.

APPLICATION

High-end networking products that require high bandwidth, such

as switches and routers.

PACKAGE

Bump

Body Size

14mm X 22mm

Bump Pitch

1mm

M5M5Y5636TG

209(11X19) bump BGA

PART NAME TABLE

Standby Current

(max.)

Active Current

Part Name

Frequency

Access

Cycle

(max.)

400mA

380mA

360mA

M5M5Y5636TG -25

M5M5Y5636TG -22

M5M5Y5636TG -20

250MHz

225MHz

200MHz

2.6ns

2.8ns

3.2ns

4.0ns

4.4ns

5.0ns

20mA

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

BUMP LAYOUT(TOP VIEW)

209 bump BGA

1

2

3

A6

4

E2

5

6

7

8

9

10

11

DQb

DQPb

NC

A

B

C

D

E

F

NC

A7

ADV

W#

A8

E3

A9

NC

DQb

BWc#

NC

A18

NC

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

NC

A16

A2

A17

NC

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

NC

A13

A14

BWb#

NC

BWd#

NC

E1#

MCL

VDD

ZQ

BWa# DQb

NC

VSS

NC

VSS

VDDQ

VSS

DQb

NC

DQPc VDDQ

VDDQ

VSS

VDDQ

VSS

VDDQ

NC

VDDQ

VSS

DQc

VSS

VDDQ

VSS

G

H

J

EP2

EP3

MCH

MCL

MCH

MCL

MCH

MCL

VDD

LBO#

A15

VDDQ

VSS

VDDQ

VSS

NC

VDDQ

CLK

VDDQ

VSS

VDDQ

NC

VDDQ

NC

K

L

CQ2 CQ2#

CQ1# CQ1

NC

VDDQ

VSS

VDDQ

VSS

VDDQ

NC

VDDQ

VSS

VDDQ

VSS

DQa

NC

M

N

P

R

T

NC

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

NC

DQPd

DQd

NC

VDDQ

VSS

VDDQ

NC

VDDQ DQPa

DQd

VSS

NC

U

V

W

NC

A3

A11

NC

A5

A4

A1

A12

A10

NC

TMS

TDI

A0

TDO

TCK

NC

Note1. MCH means “Must Connect High”. MCH should be connected to HIGH.

Note2. MCL means “Must Connect Low”. MCL should be connected to LOW.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

BLOCK DIAGRAM

VDD

VDDQ

A0

A1

19

17

ADDRESS

REGISTER

A2~18

A1

A0

A1'

A0'

D1

D0

Q1

Q0

LINEAR/

INTERLEAVED

BURST

LBO#

CLK

COUNTER

19

WRITE ADDRESS

REGISTER1

WRITE ADDRESS

REGISTER2

ADV

DQa

DQPa

256Kx36

DQb

BYTE a

BWa#

BWb#

BWc#

BWd#

|

WRITE REGISTRY

AND

DQPb

BYTE d

MEMORY

ARRAY

DATA COHERENCY

CONTROL LOGIC

DQc

WRITE

DRIVERS

DQPc

DQd

DQPd

INPUT

36

REGISTER1

REGISTER0

W#

E1#

E2

READ

CQ1

CQ1#

CQ2

LOGIC

CHIP ENABLE

CONTROL

LOGIC

E3

CQ2#

EP2

EP3

ZQ

VSS

Note3. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.

Note4. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION

and timing diagrams for detailed information.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

PIN FUNCTION

Name

Function

Synchronous

Address

Inputs

These inputs are registered and must meet the setup and hold times around the rising edge of

CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal

burst counter if burst is desired.

A0~A18

These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and

must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be

asserted on the same cycle as the address. BWa are associated with addresses and apply to

subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#

controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.

Synchronous

Byte Write

Enables

BWa#, BWb#,

BWc#, BWd#

This signal registers the address, data, chip enables, byte write enables and burst control inputs on

its rising edge.

All synchronous inputs must meet setup and hold times around the clock's rising edge.

CLK

E1#

Clock Input

Synchronous

Chip Enable

This active LOW input is used to enable the device and is sampled only when a new external

address is loaded (ADV is LOW).

These pins are user-programmable chip enable inputs. The sense of the inputs, whether they

function as active LOW or HIGH inputs, is determined by the state of the programming inputs, EP2

and EP3.

Synchronous

Chip Enable

E2, E3

EP2, EP3

ADV

Chip Enable

Program Pin

These pins determine the sense of the user-programmable chip enable inputs, whether they

function as active LOW or active HIGH inputs.

Synchronous

Address

Advance/Load

When HIGH, this input is used to advance the internal burst counter, controlling burst access after

the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new

address to be loaded at CLK rising edge.

CQ1, CQ1#,

CQ2, CQ2#

Echo Clock

Outputs

The Echo Clocks are delayed copies of the main RAM clock, CLK.

Output

Impedance

Control

This pin allows selection between RAM nominal drive strength (ZQ low) for multi-drop bus

applications and low drive strength (ZQ floating or high) point-to-point application.

ZQ

This active input determines the cycle type when ADV is LOW. This is the only means for

determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice

versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations

and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs

occur if all byte write enables are LOW.

Synchronous

Read/Write

W#

DQa,DQPa,DQb,DQPb,

DQc,DQPc,DQd,DQPd

Synchronous

Data I/O

Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is

DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge.

This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is

HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input

leak current to this pin.

Burst Mode

Control

LBO#

VDD

VSS

VDD

Core Power Supply

Ground

VSS

VDDQ

TDI

VDDQ

I/O buffer Power supply

Test Data Input

Test Data Output

Test Clock

TDO

TCK

TMS

MCH

MCL

NC

These pins are used for Boundary Scan Test.

Test Mode Select

Must Connect High

Must Connect Low

No Connect

These pins should be connected to HIGH

These pins should be connected to LOW

These pins are not internally connected and may be connected to ground.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Read Operation

Pipelined Read

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3)

are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low. The address presented to the address inputs

is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access

is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data

is allowed to propagate through the output register and onto the output pins.

CLK

E1#

ADV

W#

BWx#

A

B

C

D

E

ADD

DQ

Q(A)

Q(B)

Q(C)

CQ

Read A

Deselect

Read B

Read C

Read D

Read E

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Write Operation

Double Late Write

Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3) are

active and the write enable input signal (W#) is asserted low.

Double Late Write means that Data In is required on the third rising edge of clock. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

CLK

E1#

ADV

W#

BWx#

A

B

C

D

E

F

ADD

DQ

Q(A)

D(B)

Q(C)

D(D)

CQ

Read A

Write B

Read C

Write D

Read E

Read F

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Special Function

Burst Cycles

The SRAM provides an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write

implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the

counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the

SRAM by driving the ADV pin low, into Load mode.

Burst Read

CLK

E1#

ADV

W#

BWx#

A

B

ADD

DQ

Q(A)

Q(A+1)

Q(A+2)

Q(A+3)

CQ

Burst Read

A+1

Burst Read

A+2

Burst Read

A+3

Burst Read

B+1

Read A

Read B

Burst Write

CLK

E1#

ADV

W#

BWx#

ADD

DQ

A

B

D(A)

D(A+1)

D(A+2)

D(A+3)

CQ

Burst Write

A+1

Burst Write

A+2

Burst Write

A+3

Burst Write

A

Write A

Write B

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

DC OPERATED TRUTH TABLE

Name

Input Status

HIGH or NC

LOW

Operation

Interleaved Burst Sequence

Linear Burst Sequence

LBO#

Note5. LBO# is DC operated pin.

Note6. NC means No Connection.

Note7. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.

BURST SEQUENCE TABLE

(1) Interleaved Burst Sequence (when LBO# = HIGH or NC)

Operation

A18~A2

A1,A0

0 , 1

0 , 0

1 , 1

1 , 0

1 , 1

0 , 0

0 , 1

First access, latch external address

Second access(first burst address)

Third access(second burst address)

Fourth access(third burst address)

A18~A2

0 , 0

0 , 1

1 , 0

1 , 1

1 , 0

0 , 1

0 , 0

latched A18~A2

(2) Linear Burst Sequence (when LBO# = LOW)

Operation

A18~A2

A1,A0

0 , 1

1 , 0

1 , 1

0 , 0

1 , 0

1 , 1

0 , 0

0 , 1

First access, latch external address

Second access(first burst address)

Third access(second burst address)

Fourth access(third burst address)

A18~A2

0 , 0

0 , 1

1 , 0

1 , 1

0 , 0

0 , 1

1 , 0

latched A18~A2

Note8. The burst sequence wraps around to its initial state upon completion.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Echo Clock

The SRAM features Echo Clocks, CQ1,CQ2, CQ1#, and CQ2# that track the performance of the output drivers. The Echo Clocks are

delayed copies of the main RAM clock, CLK. Echo Clocks are designed to track changes in output driver delays due to variance in

die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. The SRAM

provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1# and CQ2#).

It should be noted that deselection of the SRAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of

Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the SRAM via E1# does not deactivate the

Echo Clocks.

Programmable Enable

The SRAM features two user programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active low

or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at HIGH, E2

functions as an active high enable. If EP2 is held to LOW, E2 functions as an active low chip enable input.

Programmability of E2 and E3 allows for banks of depth expansion to be accomplished with no additional logic. By programming the

enable inputs of four SRAMs in binary sequence (00,01,10,11) and driving the enable inputs with two address inputs, four SRAMs can

be made to look like one larger SRAM to the system.

Example Four Bank Depth Schematic

A0~A20

E1#

CK

W#

DQa~DQd

Bank0

Bank1

Bank2

Bank3

A0~A18

A19

A

A0~A18

A19

A

E3

E2#

E1#

A0~A18

A19

A

E3#

E2

A0~A18

A19

A

E3#

E2#

E1#

E3

E2

E1#

A20

E1#

CK

W#

CK

W#

CK

W#

CK

W#

DQ

CQ

DQ

CQ

DQ

CQ

DQ

CQ

Bank Enable Truth Table

EP2

EP3

LOW

HIGH

LOW

HIGH

E2

E3

Bank0

Bank1

Bank2

Bank3

LOW

HIGH

Active Low

Active High

Active Low

Active High

Active Low

Active High

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Echo Clock Control in Two Banks

CLK

ADD

E1#

A

B

C

D

E

F

E2# Bank1

E2 Bank2

DQ

Bank1

Q(A)

Q(C)

CQ

Bank1

CQ Bank1

+ CQ Bank2

CQ

Bank2

DQ

Bank2

Q(B)

Q(D)

Note9. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously

deselected by E2 or E3 being sampled false.

It should be noted that deselection of the SRAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of

Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the SRAM via E1# does not deactivate the

Echo Clocks.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Pipelined Read Bank Switch with E1# Deselect

CLK

ADD

E1#

A

B

C

D

E

E2# Bank1

E2 Bank2

DQ

Bank1

Q(A)

CQ

Bank1

CQ Bank1

+ CQ Bank2

CQ

Bank2

DQ

Bank2

Q(B)

Q(C)

Note10. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously

deselected by E2 or E3 being sampled false.

In some applications it may be appropriate to pause between banks; to deselect both SRAMs with E1# before resuming read

operations. An E1# deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle

in the bank. Although the following drawing illustrates a E1# read pause upon switching from Bank 1 to Bank 2, a write to Bank 2

would have the same effect, causing the SRAM in Bank 2 to issue at least one clock before it is needed.

Output Driver Impedance Control

The ZQ pin of SRAMs supplied with selectable impedance drivers, allows selection between SRAM nominal drive strength

(ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

TRUTH TABLE

E1#

E

(tn)

ADV

(tn)

W#

(tn)

BW#

(tn)

Current

Operation

DQ/CQ

(tn)

DQ/CQ

(tn+1)

DQ/CQ

(tn+2)

CLK

(tn)

L->H

X

H

X

F

X

T

X

L

H

L

X

Bank Deselect

X

Bank Deselect

Bank Deselect (Continue)

Deselect

***

High-Z

***

High-Z

---

High-Z / CQ

Deselect

Deselect (Continue)

High-Z / CQ High-Z / CQ

H

Write

Loads new address

Stores DQx if BWx#=LOW

Dn / CQ

(tn)

L

T

X

L

T

F

T

F

X

***

L->H

Write (Abort)

Loads new address

No data stored

X

High-Z / CQ

Write Continue

Increments address by 1

Stores DQx if BWx#=LOW

Dn-1 / CQ

(tn-1)

Dn / CQ

(tn)

X

H

X

Write

Write Continue (Abort)

Increments address by 1

No data stored

Dn-1 / CQ

(tn-1)

***

High-Z / CQ

Read

Loads new address

Qn / CQ

(tn)

L->H

L

T

X

L

H

X

---

Qn-1 / CQ

(tn-1)

Qn / CQ

(tn)

Read Continue

Increments address by 1

Read

X

H

Note11. If E2=EP2 and E3=EP3 then E=”T” else E=”F”.

Note12. If one or more BWx#=LOW then BW#=”T” else BW#=”F”.

Note13. “H” = input “HIGH”; “L” = input “LOW”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

Note14. “ *** “ = indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.

Note15. “ --- “ = indicates that the DQ input requirement / output state and CQ output state are determined by the next operation.

Note16. DQs are tri-stated in response to Bank Deselect, Deselect and Write commands, one full cycle after the command is sampled.

Note17. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.

Note18. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4)

distinct pieces of data per single external address input. If a fourth (4) Continue operation is initiated, the internal address wraps

back to the initial external (base) address.

WRITE TRUTH TABLE

W#

H

L

BWa#

X

BWb#

BWc# BWd#

Function

X

H

L

X

H

L

X

H

L

Read

L

Write Byte “a”

Write Byte “b”

Write Byte “c”

Write Byte “d”

Write All Bytes

Write Abort / NOP

L

H

L

H

L

H

L

H

Note19. X means "don't care". H means logic HIGH. L means logic LOW.

Note20. All inputs must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

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STATE DIAGRAM

X, F, L, X or X, X, H, X

Bank

Deselect

L, T, L, H

L, T, L, L

H, T, L, X

X, F, L, X

Deselect

L, T, L, H

L, T, L, L

H, T, L, X or X, X, H, X

H, T, L, X

L, T, L, L

L, T, L, H

Read

Write

X, F, L, X

L, T, L, H

X, F, L, X

X, X, H, X

L, T, L, L

L, T, L, H

L, T, L, L

H, T, L, X

X, F, L, X

L, T, L, L

L, T, L, H

H, T, L, X

X, F, L, X

Write

Continue

Write

Continue

X, X, H, X

Key

n

n+1

n+2

n+3

Input Command Code

Clock

f

Transition

Command

f

Current State (n)

Next State (n+1)

Current State

Next State

Current State & Next State Definition for Read/Write Control State Diagram

Note21. The notation “X, X, X, X” controlling the state transitions above indicate the states of inputs E1#, E, ADV, and W# respectively.

Note22. If (E2=EP2 and E3=EP3) then E=”T” else E=”F”.

Note23. “H” = input “HIGH”; “L” = input “LOW”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Power Supply Voltage

I/O Buffer Power Supply Voltage

Input Voltage

Conditions

Ratings

Unit

V

VDD

-0.5*~2.5

VDDQ

VI

-0.5*~2.5

V

With respect to VSS

-0.5~VDDQ+0.5(£2.5V max.) **

V

VO

Output Voltage

-0.5~VDDQ+0.5(£2.5V max.) **

V

PD

Maximum Power Dissipation (VDD)

Operating Temperature

Storage Temperature(bias)

Storage Temperature

780

0~70

mW

°C

TOPR

TSTG(bias)

TSTG

-10~85

-65~150

Note24. * This is -1.0V~3.6V when pulse width£2ns, and -0.5V~2.5V in case of DC.

** This is -1.0V~VDDQ+1.0V(£3.6V max.) when pulse width£2ns, and –0.5V~VDDQ+0.5V in case of DC.

DC ELECTRICAL CHARACTERISTICS

(1) Power Supplies

Limits

Symbol

Parameter

Condition

Unit

Min

1.70

Max

1.95

VDD

Power Supply Voltage

V

VDDQ

I/O Buffer Power Supply Voltage

(2) CMOS I/O DC Input Characteristics

Limits

Symbol

Parameter

Condition

Unit

Min

0.65*VDDQ

-0.3*

Max

VIH

VIL

High-level Input Voltage

Low-level Input Voltage

VDDQ+0.3

0.35*VDDQ

V

Note25. *VIL min is –1.0V and VIH max is VDDQ+1.0V(max. 3.6V) in case of AC (Pulse width £ 2ns).

(3) Input and Output Leakage Characteristics

Limits

Symbol

Parameter

Condition

VI = 0V~VDDQ

Unit

Min

Max

Input Leakage Current

(except EP2, EP3, LBO#, ZQ, MCH, MCL pins)

10

µA

IIL

Input Leakage Current of

EP2, EP3, LBO#, ZQ, MCH, MCL pins

VI = 0V~VDDQ

10

µA

IOL

Output Leakage Current

VI/O = 0V~VDDQ

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(4) Selectable Impedance Output Driver DC Electrical Characteristics

Limits

Symbol

Parameter

Condition

Unit

Min

Max

0.4

VOHL

VOLL

VOHH

VOLH

Low Drive Output High Voltage

Low Drive Output Low Voltage

High Drive Output High Voltage

High Drive Output Low Voltage

IOHL = -4mA

IOLL = 4mA

IOHH = -8mA

IOLH = 8mA

VDDQ-0.4V

V

VDDQ-0.4V

0.4

Note26. ZQ=H; High Impedance output driver setting

Note27. ZQ=L; Low Impedance output driver setting

(5) Operating Currents

Limits

Symbol

Parameter

Condition

Unit

Min

Max

400

380

360

140

110

100

4.0ns cycle (250MHz)

Device selected;

Output open

All other inputs

VI£VIL or VI³ VIH

Power Supply Current

4.4ns cycle (225MHz)

5.0ns cycle (200MHz)

4.0ns cycle (250MHz)

4.4ns cycle (225MHz)

5.0ns cycle (200MHz)

ICC1

mA

: Operating

E1#³ VIH or (E2 or E3 False)

Output open

Power Supply Current

:Chip Disable

ICC2

ICC3

mA

All other inputs

VI£VIL or VI³ VIH

and Bank Deselect

Device deselected; Output open CLK frequency=0Hz

All inputs VI£VSS+0.1V or VI³ VDDQ-0.1V

CMOS Standby Current

(CLK stopped standby mode)

20

CAPACITANCE

Symbol

Limits

Parameter

Condition

Unit

Min

Typ

Max

6

CI

Input Capacitance

VI=GND, VI=25mVrms, f=1MHz

pF

VO=GND, VO=25mVrms, f=1MHz

CO

Input / Output (DQ) Capacitance

8

Note28. This parameter is sampled.

THERMAL RESISTANCE

Limits

Typ

Symbol

Parameter

Condition

Unit

Min

Max

Thermal resistance Junction Ambient

Thermal resistance Junction to Case

TBD

pF

qJA

qJC

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AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted)

(1) MEASUREMENT CONDITION

Input pulse levels ···································V··IH··=·VDDQ, VIL=0V

Input rise and fall times ···························f·a··s·ter than or equal to 1V/ns

Input timing reference levels ·····················V··IH=VIL=VDDQ / 2

Output reference levels ···························V··I·H·=VIL=VDDQ / 2

Output load ···········································F··i·g·.·1··

30pF

(Including wiring and JIG)

Q

ZO=50W

50W

VT=VDDQ / 2

Fig.1 Output load

Input

VDDQ / 2

Waveform

Input

VDDQ / 2

tplh

Waveform

toff

ton

tphl

Vh

Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz))

Vz

Output

Waveform

Output

Waveform

VDDQ / 2

(toff)

(ton)

Vl

0.2(Vz-Vl)

Vz-(0.2(Vz-Vl))

Fig.3 Tri-State measurement

Fig.2 Tdly measurement

Note29.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform.

Input waveform should have a slew rate of faster than or equal to 1V/ns.

Note30.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%

from its initial to final Value VDDQ/2.

Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.

Note31. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%

from its initial Value VDDQ/2 to its final Value.

Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.

Note32.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

(2)TIMING CHARACTERISTICS

Limits

250MHz

-25

225MHz

-22

200MHz

-20

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Max

Clock

tKHKH

tKHKL

tKLKH

Clock Cycle Time

Clock HIGH Time

Clock LOW Time

4.0

1.5

4.4

1.6

5.0

1.8

ns

Output times

tKHQV

tKHQX

Clock HIGH to Output Valid

Clock HIGH to Output Invalid

2.6

2.8

3.2

ns

0.5

0.6

0.7

tKHQX1 Clock HIGH to Output in Low-Z

tKHQZ

tCHCL

tCLCH

tKHCH

tKLCL

tKHCX1

tKHCZ

tCHQV

tCHQX

Clock HIGH to Output in High-Z

Echo Clock HIGH Time

0.5

0.6

0.7

1.25

0.5

1.35

0.5

1.55

0.5

Echo Clock LOW Time

Clock HIGH to Echo Clock HIGH

Clock LOW to Echo Clock LOW

Clock HIGH to Echo Clock Low-Z

Clock HIGH to Echo Clock High-Z

Echo Clock HIGH to Output Valid

Output Invalid to Echo Clock HIGH

2.5

2.7

3.1

0.5

2.5

0.5

2.7

0.5

3.1

0.5

-0.5

Setup Times

tAVKH

Address Valid to Clock HIGH

0.8

1.0

1.2

ns

tadvVKH ADV Valid to Clock HIGH

0.8

1.0

tWVKH

tBxVKH

tEVKH

tDVKH

Write Valid to Clock HIGH

Byte Write Valid to Clock HIGH (BWa#~BWd#)

Enable Valid to Clock HIGH (E1#,E2,E3)

Data In Valid Clock HIGH

Hold Times

tKHAX

Clock HIGH to Address don’t care

0.5

ns

tKHadvX Clock HIGH to ADV don’t care

tKHWX

tKHBxX

tKHEX

tKHDX

Clock HIGH to Write don’t care

Clock HIGH to Byte Write don’t care (BWa#~BWd#)

Clock HIGH to Enable don’t care (E1#,E2,E3)

Clock HIGH to Data In don’t care

Note33. Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted.

Note34. tKHQX1, tKHQZ, tKHCX1, tKHCZ are sampled.

Note35. LBO#, EP2, EP3, ZQ is static and must not change during normal operation.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Timing Parameter Key

tKHKH

CLK

tKHAX

tKHKL

tKHQZ

tKLKH

tAVKH

ADD

C

D

E

tKHQV

tKHQX1

tKHQX

DQ

CQ

QB

tCHQV

tKLCL

tCHQX

tKHCH

tKHCZ

tKHCX1

tCLCH

tCHCL

=CQ High-Z

tKHKH

CLK

tKHAX

tKHKL

tKLKH

tAVKH

ADD

A

B

C

tnVKH

tKHnX

E1#, E2, E3

W#, BWx#,

ADV

tDVKH

tKHDX

DQ

QA

Note36. tnVKH=tEVKH, tWVKH, tBxVKH, tadvVKH, etc. and tKHnX=tKHEX, tKHWX, tKHBxX, tKHadvX, etc.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

JTAG PORT OPERATION

Overview

The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface

standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. Unlike JTAG

implementations that have been common among SRAM vendors for the last several years, this implementation dose offer a form of

EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the "hand coding" that has been required to overcome the test

program compiler errors caused by previous non-compliant implementation. The JTAG Port interfaces with conventional CMOS logic

level signaling.

Disabling the JTAG port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To

assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The

TDO pin should be left unconnected.

JTAG Pin Description

Test Clock (TCK)

The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates

from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven TMS

input will produce the same result as a logic one input level.

Test Data In (TDI)

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins.

the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction

that is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce

the same result as a logic one input level.

Test Data Out (TDO)

The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge of

TCK. This is the output side of the serial registers placed between the TDI and TDO pins.

Note:

This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS

is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.

JTAG Port Registers

Overview

The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and 0s

applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of

TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and

TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is

placed in the Test-Logic-Reset state.

Bypass Register

The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed

through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The

flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The Boundary Scan

Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits

in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the

TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the Capture-RD state and then is placed

between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST

instruction can be used to activate the Boundary Scan Register.

Identification (ID) Register

The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the Capture-DR

state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It describes various

attributes of the SRAM (see page 25). The register is then placed between the TDI and TDO pins when the controller is moved into the

Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins.

TAP Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private)

instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in

prescribed ways. Although the TAP Controller in this device follows the 1149.1 conventions, it is not 1194.1-compliant because one of

the mandatory instructions, EXTEST, is uniquely implemented. The TAP on this device may be used to monitor all input and I/O pads.

This device will not perform INTEST but can perform the preload portion of the SAMPLE/PRELOAD command.

When the TAP controller is placed in the Capture-IR state, the two least significant bits of the instruction register are loaded with 01.

When the TAP controller is moved to the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state the

desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all

instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction

Set for this device is listed in the following table.

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This

occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing

of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the

Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the

Boundary Scan Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the

default state identified in the BSDL file. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to

attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

sample metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for

long enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused for

any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the Shift-DR

state then places the Boundary Scan Register between the TDI and TDO pins.

EXTEST-A

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the Instruction Register is loaded with all logic 0s.

The EXTEST command dose not block or override the SRAM's input pins; therefore, the SRAM's internal state is still determined by its

input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern with the SAMPLE/PRELOAD command. Then the EXTEST

command is used to output the Boundary Scan Register's contents, in parallel, on the SRAM's data output drivers on the falling edge of

TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,

the state of all SRAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are

transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the SRAM's output pins drive

out the value of the Boundary Scan Register location with which each output pin is associated.

The EXTEST implementation in this device dose not, without further user intervention, actually move the contents of the scan chain onto

the SRAM's output pins. Therefore this device is not strictly 1149.1-compliant. To push data from the Boundary Scan Registers, in

parallel, out onto the SRAM's I/O and output pins, the SRAM's main clock (CK) must be pulsed. A single CK transition is sufficient to

transfer the data, but more transitions will do no harm.

IDCODE

The IDCODE instruction cause the ID ROM to be loaded into the ID register when the controller is in the Capture-DR state and places

the ID Register between the TDI and TDO pins in the Shift-DR state. The IDCODE instruction is the default instruction loaded in at

power-up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the Instruction Register, all SRAM outputs are forced to an inactive drive state (High-Z) and the

Boundary Scan Register is placed between the TDI and TDO pins when the TAP Controller is moved to the Shift-DR state.

RFU

These instructions are reserved for future use. Do not use these instructions.

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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

JTAG TAP BLOCK DIAGRAM

Bypass Register

0

Instruction Register

2

1 0

TDI

TDO

Identification Register

31 30 29 . . . . . . . .

2

1 0

Boundary Scan Register

. . . . . . . . . . . . . . . . . .

2

1 0

TMS

TCK

Test Access Port (TAP) Controller

BOUNDARY SCAN ORDER

TBD

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JTAG TAP CONTROLLER STATE DIAGRAM

Test-Logic-Reset

1

0

1

Run-Test/Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

0

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

0

Update-DR

Update-IR

1

0

1

0

TAP CONTROLLER DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted)

Limits

Symbol

Parameter

Condition

Unit

Min

0.65*VDDQ

-0.3 **

VDDQ-0.1

-

Max

VIHT

VILT

VOHT

VOLT

IINT

Test Port Input High Voltage

VDDQ+0.3 **

V

Test Port Input Low Voltage

0.35*VDDQ

Test Port Output High Voltage

Test Port Output Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

IOH=-100µA

IOL=+100µA

-

V

0.1

10

V

-10

µA

IOLT

Output Disable, VOUT=0V~VDDQ

-10

Note37. **Input Undershoot/Overshoot voltage must be –1.0V<Vi<VDDQ+1V(max. 3.6V) with a pulse width not to exceed 20% tTCK.

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TAP CONTROLLER AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted)

(1)MEASUREMENT CONDITION

Input pulse levels ···································V··IH··=·VDDQ, VIL=0V

Input rise and fall times ···························f·a··s·ter than or equal to 1V/ns

Input timing reference levels ····················V··I·H=VIL=VDDQ / 2

Output reference levels ··························V··I·H··=VIL=VDDQ / 2

Output load ···········································F··i·g·.·4··

30pF

Q

(Including wiring and JIG)

50W

VT=VDDQ / 2

ZO=50W

Fig.4 Output load

(2)TIMING CHARACTERISTICS

Limits

Symbol

tTF

tTKC

tTKH

tTKL

tTS

Parameter

Unit

Min

Max

TCK Frequency

20

MHz

ns

TCK Cycle Time

50

20

10

TCK High Pulse Width

TCK Low Pulse Width

TDI, TMS setup time

TDI, TMS hold time

TCK Low to TDO valid

ns

tTH

tTKQ

ns

20

ns

(3) TIMING

tTKC

tTKH

tTKL

TCK

tTS

tTH

TMS

TDI

tTS tTH

tTKQ

TDO

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JTAG TAP INSTRUCTION SET SUMMARY

Instruction

Code

Description

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

This SRAM implements an Clock Assisted EXTEST function. Not 1149.1 Compliant.

Preloads ID Register and places it between TDI and TDO

EXTEST-A

IDCODE

000

001

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Forces all Data and Clock output drivers to High-Z

SAMPLE-Z

RFU

SAMPLE/PRELOAD

RFU

011

100

101

110

111

Do not use this instruction; Reserved for Future Use.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Do not use this instruction; Reserved for Future Use.

RFU

Do not use this instruction; Reserved for Future Use.

BYPASS

Places the BYPASS Register between TDI and TDO.

STRUCTURE OF IDENTIFICATION REGISTER

Device Information

Capacity Function

Revision

JEDEC Vendor Code of MITSUBISHI

VDD

Width

Gen.

Bit No.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

M5M5Y5636

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

Note38. Bit of Device Information “Gen.(Generation)” means

Bit No.

13 12

1^stGeneration

2^ndGeneration

3^rdGeneration

0

1

0

1

0

Note39. Bit of Device Information ”Width” means

Bit No.

X16

X18

X32

X36

X64

X72

16 15 14

0

1

0

1

0

1

0

1

0

1

Note40. Bit of Device Information ”Function” means

Bit No.

Network SRAM

PB

20 19 18 17

0

1

0

1

Note41. Bit of Device Information ”Capacity” means

Bit No.

24 23 22 21

1M or 1.15M

2M or 2.3M

4M or 4.5M

8M or 9M

16M or 18M

32M or 36M

0

1

0

1

0

1

0

1

0

1

0

Note42. Bit of Device Information ”VDD” means

Bit No.

3.3V

2.5V

1.8V

1.5V

27 26 25

0

1

0

1

0

1

25

Advanced Information

M5M5Y5636TG REV.0.0

MITSUBISHI

ELECTRIC

MITSUBISHI LSIs

M5M5Y5636TG – 25,22,20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

PACKAGE OUTLINE

209(11x19) bump Ball Grid Array(BGA) Pin Pitch 1.0mm

Refer to JEDEC Standard MS-028, Variation BC,

which can be seen at:

http://www.jedec.org/download/search/MS-028C.pdf

26

Advanced Information

M5M5Y5636TG REV.0.0

MITSUBISHI

ELECTRIC

MITSUBISHI LSIs

M5M5Y5636TG – 25,22,20

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

REVISION HISTORY

• Jun/06/2001 REV.0.0 First revision

27

Advanced Information

M5M5Y5636TG REV.0.0

MITSUBISHI

ELECTRIC


型号：	M5M5Y5636TG-25
厂家：	Mitsubishi Group
描述：	18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM 18874368 - BIT （ 524288 - WORD 36 - BIT ）网络SRAM 存储内存集成电路静态存储器时钟
文件：	总27页 (文件大小：214K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M5M5Y5636TG-25 [MITSUBISHI]

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