M5M5W816WG-85HI [MITSUBISHI]
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM; 8388608 - BIT ( 524288 - WORD 16位) CMOS静态RAM![M5M5W816WG-85HI](http://pdffile.icpdf.com/pdf1/p00036/img/icpdf/M5M5W816WG-85_190041_icpdf.jpg)
型号: | M5M5W816WG-85HI |
厂家: | ![]() |
描述: | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
文件: | 总10页 (文件大小:104K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
FEATURES
DESCRIPTION
- Single 2.7~3.0V power supply
- Small stand-by current: 0.1µA (2V, ty p.)
- No clocks, No ref resh
The M5M5W816 is a family of low v oltage 8-Mbit static RAMs
organized as 524288-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.18µm CMOS technology .
- Data retention supply v oltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1#, S2, BC1#
and BC2#
The M5M5W816 is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectiv es.
M5M5W816WG is packaged in a CSP (chip scale package),
with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It giv es the best solution f or a
compaction
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE prev ents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 48ball 7.5mm x 8.5mm CSP
of mounting area as well as f lexibility of wiring pattern of printed
circuit boards.
Activ e
Stand-by current
Version,
Power
Access time
max.
current
Ratings (max.)
* Ty pical
Part name
Operating
Icc1
Supply
25°C 40°C 25°C 40°C 70°C 85°C
* ( ty p.)
temperature
40mA
(10MHz)
10mA
I-version
-40 ~ +85°C
M5M5W816WG -
85HI
85ns
1.0
20
40
2
4
2.7 ~ 3.0V
0.5
(1MHz)
* Typical parameter indicates the value for the
center
of distribution, and is not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
A0
BC1#
DQ16
DQ14
GND
A1
A2
S2
O E #
A
B
C
D
E
F
A3
A5
A4
A6
D Q 1
S1#
BC2#
DQ15
DQ13
DQ12
DQ10
Pin
Function
D Q 3
VCC
GND
D Q 2
A0 ~ A18 Address input
DQ1 ~ DQ16
S1#
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
A17
A7
D Q 4
D Q 5
NC or
GND
S2
VCC
A16
A15
A13
W#
D Q 11
A14
A12
A9
D Q 7
D Q 6
D Q 8
N.C.
OE#
BC1#
BC2#
Vcc
D Q 9
A18
N.C.
A8
W #
G
H
A10
A11
GND
Ground supply
Outline : 48F7Q
NC : No Connection
*Don't connect E3 ball to voltage level more than 0V
1
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
When setting BC1# and BC2# at a high lev el or S1# at a high
The M5M5W816WG is organized as 524288-words by 16-bit.
These dev ices operate on a single +2.7~3.0V power supply ,
and are directly TTL compatible to both input and output. Its
fully static circuit needs no clocks and no refresh, and
makes it useful.
lev el or S2 at a low lev el, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1#,
BC2# and S1#, S2.
The power supply current is reduced as low as 0.1µA(25°C,
ty pical), and the memory data can be held at +2.0V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S1#, S2 , W# and
OE#. Each mode is summarized in the function table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S1# and the high lev el S2. The address(A0~A18) must
be set up bef ore the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting W# at a high lev el
and OE# at a low lev el while BC1# and/or BC2# and S1# and
S2 are in an activ e state(S1#=L,S2=H).
When setting BC1# at the high lev el and other pins are in
an activ e stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-byte
are in a selectable mode and upper-by te are in a non-
selectable mode.
FUNCTION TABLE
S2
OE#
BC1# BC2#
S1#
W#
DQ1~8 DQ9~16
Icc
Mode
Non selection
Non selection
Non selection
Non selection
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Standby
Standby
Standby
Standby
Activ e
H
L
H
X
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
L
H
H
H
L
X
X
X
H
H
H
H
L
L
L
L
L
X
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
X
L
H
X
L
H
X
H
H
H
H
H
H
H
H
H
High-Z
Din
Write
Read
Dout High-Z Activ e
High-Z High-Z Activ e
High-Z Din
High-Z Dout
High-Z High-Z Activ e
Write
Read
Activ e
Activ e
H
X
L
Din
Din
Activ e
Activ e
Write
Read
L
L
Dout
Dout
L
H
High-Z High-Z Activ e
BLOCK DIAGRAM
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
524288 WORDS
x 16 BITS
A17
A18
-
DQ
9
CLOCK
GENERATOR
S1#
DQ
16
S2
BC1#
BC2#
W#
Vcc
GND
OE #
2
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Units
Conditions
Ratings
V
Supply v oltage
Input v oltage
With respect to GND
With respect to GND
With respect to GND
-0.3* ~ +4.6
cc
VI
-0.3* ~ Vcc + 0.3 (max. 4.6V)
V
Output v oltage
Power dissipation
VO
Pd
0 ~ Vcc
700
25°C
Ta=
mW
°C
Operating
Ta
- 40 ~ +85
temperature
Storage temperature
Tstg
°C
- 65 ~ +150
<
* -3.0V in case of AC (Pulse width 30ns)
=
( Vcc=2.7 ~ 3.0V, unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Limits
Ty p
Symbol
Parameter
Conditions
Units
Min
Max
Vcc+0.2V
0.6
High-lev el input v oltage
Low-lev el input v oltage
High-lev el output v oltage
Low-lev el output v oltage
Input leakage current
2.2
-0.2 *
2.4
VIH
VIL
VOH
VOL
II
V
IOH= -0.5mA
IOL=2mA
0.4
±1
VI =0 ~ Vcc
µA
BC1# and BC2# =VIH or S1# =VIH or S2=VIL or OE# =VIH, VI/O=0 ~ Vcc
Output leakage current
IO
±1
<
<
BC1# and BC2# 0.2V, S1# 0.2V, S2 Vcc-0.2V
=
=
f= 10MHz
f= 1MHz
f= 10MHz
f= 1MHz
-
-
-
-
30
5
40
10
40
10
Activ e supply current
( AC,MOS lev el )
<
>
other inputs 0.2V or
Output - open (duty 100%)
Vcc-0.2V
Icc1
=
=
mA
µA
BC1# and BC2#=VIL , S1#=VIL ,S2=VIH
other pins =VIH or VIL
Output - open (duty 100%)
30
5
Activ e supply current
( AC,TTL lev el )
Icc2
>
(1)
S1# Vcc - 0.2V,
=
~ +25°C
~ +40°C
0.5
-
-
2
4
>
S2 Vcc - 0.2V,
=
other inputs = 0 ~ Vcc
1.0
<
(2)
(3)
S2 0.2V,
Stand by supply current
( AC,MOS lev el )
=
Icc3
other inputs = 0 ~ Vcc
>
~ +70°C
~ +85°C
-
-
-
-
-
20
40
2
BC1# and BC2# Vcc - 0.2V
=
>
<
S1# 0.2V, S2 Vcc - 0.2V
other inputs = 0 ~ Vcc
=
=
BC1# and BC2# =VIH or S1# =VIH or S2=VIL
Other inputs= 0 ~ Vcc
Stand by supply current
( AC,TTL lev el )
mA
<
-
Icc4
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
* -3.0V in case of AC (Pulse width 30ns)
=
Note 2: Typical parameter indicates the value for the center of distribution, and is not 100% tested.
(Vcc=2.7 ~ 3.0V, unless otherwise noted)
CAPACITANCE
Limits
Units
Symbol
Conditions
Parameter
Ty p
Min
Max
10
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
CI
pF
CO
10
3
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.0V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
1TTL
Supply v oltage
2.7~3.0V
Input pulse
VIH=2.4V, VIL=0.4V
DQ
Input rise time and f all time
5ns
CL
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Reference lev el
Output loads
VOH=VOL=1.5V
Fig.1,CL=30pF
Including scope and
jig capacitance
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
Units
Parameter
Symbol
Min
Max
tCR
ta(A)
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
85
85
85
85
85
45
30
30
30
30
30
ta(S1)
ta(S2)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
By te control 2 access time
Output enable access time
Output disable time after S1# high
Output disable time after S2 low
Output disable time after BC1# high
Output disable time after BC2# high
Output disable time after OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC1# low
Output enable time af ter BC2# low
Output enable time af ter OE# low
10
10
5
5
5
ten(S2)
tdis(BC1)
tdis(BC2)
ten(OE)
tV(A)
10
Data v alid time after address
ns
(3) WRITE CYCLE
Limits
Units
Symbol
Parameter
Min
Max
ns
ns
ns
ns
ns
Write cy cle time
Write pulse width
85
60
0
70
70
70
70
70
45
0
tCW
tw(W)
tsu(A)
Address setup time
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time from W# low
Output disable time from OE# high
Output enable time f rom W# high
ns
ns
ns
ns
ns
ns
ns
ns
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
0
30
30
5
5
ns
ns
Output enable time f rom OE# low
4
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~18
tv (A)
ta(A)
ta(BC1)or
ta(BC2)
BC1#,BC2#
(Note3)
(Note3)
tdis (BC1) or tdis (BC1)
ta(S1)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
tdis (S1)
ta(S2)
tdis (S2)
ta (OE)
OE#
(Note3)
(Note3)
ten (OE)
tdis (OE)
W# = "H" lev el
DQ1~16
ten (BC1)
ten (BC2)
VALID DATA
ten (S1)
ten (S2)
Write cycle
( W# control mode )
tCW
A0~18
tsu (BC1) or tsu(BC2)
BC1#,BC2#
(Note3)
(Note3)
tsu (S1)
tsu (S2)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
OE#
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
W#
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ1~16
tsu (D) th (D)
5
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
tCW
A0~18
tsu (BC1) or
tsu (BC2)
trec (W)
tsu (A)
BC1#,BC2#
S1#
(Note3)
(Note3)
(Note3)
(Note3)
S2
(Note5)
W#
(Note4)
tsu (D)
(Note3)
(Note3)
th (D)
DATA IN
STABLE
DQ1~16
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S1# low, S2 high overlaps BC1# and/or BC2# low and W# low.
Note 5: When the falling edge of W# is simultaneously or prior to the falling edge of BC1# and/or BC2# or the falling edge of S1#
or rising edge of S2, the outputs are maintained in the high impedance state.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
6
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S1# control mode)
tCW
A0~18
BC1#,BC2#
(Note3)
(Note3)
trec (W)
tsu (S1)
tsu (A)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
Write cycle (S2 control mode)
tCW
A0~18
BC1#,BC2#
(Note3)
(Note3)
trec (W)
tsu (S2)
tsu (A)
S1#
S2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
7
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
2001.4.11
Ver. 2.0
M5M5W816WG - 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Vcc (PD)
VI (BC#)
Parameter
Test conditions
Units
V
Ty p
Min
2.0
Max
Power down supply voltage
Vcc(PD)
Vcc(PD)
Vcc(PD)
Vcc(PD)
2.0
2.2V
2.0V
2.2V
2.0V
Byte control input BC1# &
BC2#
V
V
2.2V
2.2V
Vcc(PD)
Vcc(PD)
0.1
2.0
VI (S1#)
VI (S2)
Chip select input S1#
Chip select input S2
0.2
1.5
3
Vcc=2.0V
~ +25°C
~ +40°C
-
-
-
-
>
(1)
(2)
(3)
S1# Vcc - 0.2V,
=
other inputs = 0 ~ Vcc
0.2
Power down
supply current
<
S2 0.2V,
Icc (PD)
=
other inputs = 0 ~ Vcc
µA
-
-
15
30
~ +70°C
~ +85°C
>
BC1# and BC2# Vcc - 0.2V
=
>
<
S1# 0.2V, S2 Vcc - 0.2V
other inputs = 0 ~ Vcc
=
=
Note 2: Typical parameter of Icc(PD) indicates the value for the
center of distribution, and is not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Symbol
Parameter
Units
Test conditions
Ty p
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
ns
ms
5
Power down recov ery time
(3) TIMING DIAGRAM
>
On the BC# control mode, the lev el of S1# and S2 must be f ixed at S1#, S2 Vcc-0.2V or S2 0.2V
BC# control mode
Vcc
=
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
BC1#
BC2#
>
BC1# , BC2# Vcc-0.2V
=
>
On the S1# control mode, the lev el of S2 must be fixed at S2 Vcc-0.2V or S2 0.2V
S1# control mode
Vcc
=
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
>
S1# Vcc-0.2V
S1#
=
S2 control mode
Vcc
2.7V
2.7V
S2
trec (PD)
tsu (PD)
0.2V
0.2V
S2 0.2V
8
MITSUBISHI ELECTRIC
MITSUBISHI ELECTRIC
48FBGA for 8MSRAM
0.75 x 5=3.75
0.75(TYP)
0.2
A
C
7.5 TYP
(7.3)
1.2MAX
0.35±0.05
A
H
G
F
B
E
D
C
B
A
C
2
3
5
6
4
1
X4
48-ø0.45±0.05
0.2
M
AB
C
ø0.08
15th.Dec.2000
Date:
Code:
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M5M5W817KT-70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
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