M5M5W816WG-85L [MITSUBISHI]
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM; 8388608 - BIT （ 524288 - WORD 16位） CMOS静态RAM
| 型号： | M5M5W816WG-85L |
| 厂家： | 
Mitsubishi Group |
| 描述： | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
DESCRIPTION
FEATURES
- Single 1.8~2.7V power supply
- Small stand-by current: 0.1µA (2.7V, typ.)
- No clocks, No refresh
The M5M5W816 is a family of low voltage 8-Mbit static RAMs
organized as 524288-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.18µm CMOS technology.
- Data retention supply voltage =1.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1, S2, BC1 and BC2
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE prevents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 48ball 7.0mm x 8.5mm CSP
The M5M5W816 is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5W816WG is packaged in a CSP (chip scale package),
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It gives the best solution for a compaction
of mounting area as well as flexibility of wiring pattern of printed
circuit boards.
From the point of operating temperature, the family is divided
into two versions; "Standard" and "I-version".
Active
current
Icc1
(2.7V, typ.)
Stand-by current (Vcc=2.7V)
Version,
Power
Supply
Access time
max.
Ratings (max.)
* Typical
Part name
Operating
temperature
25°C 40°C 25°C 40°C 70°C 85°C
M5M5W816WG -85L
M5M5W816WG -10L
M5M5W816WG -85H
M5M5W816WG -10H
M5M5W816WG -85LI
M5M5W816WG -10LI
M5M5W816WG -85HI
M5M5W816WG -10HI
85ns
100ns
85ns
100ns
85ns
100ns
85ns
100ns
---
1
---
2
---
---
1.8 ~ 2.7V
1.8 ~ 2.7V
1.8 ~ 2.7V
1.8 ~ 2.7V
0.1
0.1
0.2
0.2
16
8
Standard
0 ~ +70°C
40mA
(10MHz)
5mA
---
---
(1MHz)
16
8
30
15
0.1
0.1
0.2
0.2
I-version
-40 ~ +85°C
1
2
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
A
A0
BC1
A1
A2
S2
OE
DQ9
B
A3
A5
BC2
A4
A6
S1
DQ1
DQ3
Pin
Function
A0 ~ A18 Address input
C DQ10 DQ11
DQ2
DQ1 ~ DQ16
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower Byte (DQ1 ~ 8)
Upper Byte (DQ9 ~ 16)
Power supply
D
GND
VCC
DQ12
DQ13
DQ14
A17
A7
DQ4
DQ5
VCC
GND
S1
S2
E
F
GND
A16
W
DQ15
A14
A15
DQ6
DQ7
DQ8
N.C.
OE
BC1
BC2
Vcc
GND
DQ16
A18
G
H
N.C.
A8
A12
A9
A13
A10
W
A11
Ground supply
Outline: 48FHA
NC: No Connection
1
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W816WG is organized as 524288-words by 16-
bit. These devices operate on a single +1.8~2.7V power
When setting BC1 and BC2 at a high level or S1 at a high level
or S2 at a low level, the chips are in a non-selectable mode in
supply, and are directly TTL compatible to both input and which both reading and writing are disabled. In this mode, the
output. Its fully static circuit needs no clocks and no refresh,
and makes it useful.
output stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S1, S2.
The power supply current is reduced as low as 0.1µA(25°C,
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S1, S2 , W and OE. typical), and the memory data can be held at +1V power supply,
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low level
S1 and the high level S2. The address(A0~A18) must be set
up before the write cycle and must be stable during the entire
cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S1 and S2
are in an active state(S1=L,S2=H).
When setting BC1 at the high level and other pins are in an
active stage , upper-byte are in a selectable mode in which
both reading and writing are enabled, and lower-byte are in a
non-selectable mode. And when setting BC2 at a high level
and other pins are in an active stage, lower-byte are in a
selectable mode and upper-byte are in a non-selectable
mode.
enabling battery back-up operation during power failure or
power-down operation in the non-selected mode.
FUNCTION TABLE
DQ1~8 DQ9~16
S2
BC1 BC2
OE
Icc
S1
Mode
W
Non selection High-Z High-Z
Standby
Standby
Standby
Standby
Active
H
L
H
X
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
L
L
L
H
H
H
L
X
X
X
H
H
H
H
L
L
L
L
L
X
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
X
L
H
X
L
Non selection
High-Z High-Z
High-Z High-Z
Non selection
H
X
H
H
H
H
H
H
H
H
H
Non selection High-Z High-Z
High-Z
Dout High-Z Active
High-Z High-Z Active
Write
Read
Din
Write
Read
High-Z Din
High-Z Dout
Active
Active
H
X
L
High-Z High-Z Active
Din
Dout
Din
Dout
Active
Active
Write
Read
L
L
L
H
High-Z High-Z Active
BLOCK DIAGRAM
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
524288 WORDS
x 16 BITS
A17
A18
DQ
9
-
CLOCK
GENERATOR
DQ
16
S1
S2
BC1
BC2
W
Vcc
GND
OE
2
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Units
Conditions
Ratings
V
Supply voltage
Input voltage
With respect to GND
With respect to GND
With respect to GND
Ta=25¥ C
-0.5* ~ +4.6
cc
VI
-0.2* ~ Vcc + 0.2 (max. 4.6V)
V
Output voltage
Power dissipation
VO
Pd
0 ~ Vcc
700
mW
°C
0 ~ +70
- 40 ~ +85
Standard
I-version
(-L, -H)
Operating
temperature
Ta
(-LI, -HI)
Storage temperature
Tstg
°C
- 65 ~ +150
<
* -3.0V in case of AC (Pulse width 30ns)
=
( Vcc=1.8 ~ 2.7V, unless otherwise noted)
Limits
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Units
Min
0.7 x Vcc
-0.2 *
1.6
Typ
Max
Vcc+0.2V
0.4
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
VIH
VIL
VOH
VOL
II
V
IOH= -0.1mA
IOL=0.1mA
VI =0 ~ Vcc
0.2
±1
±1
50
10
50
10
1
µA
BC1 and BC2=VIHor S1=VIHor S2=VIL or OE=VIH, VI/O=0 ~ Vcc
IO
<
<
BC1 and BC2 0.2V, S1 0.2V, S2 Vcc-0.2V
=
=
f= 10MHz
f= 1MHz
f= 10MHz
-
-
-
40
5
Active supply current
( AC,MOS level )
>
other inputs <0.2V or
Vcc-0.2V
Icc1
=
=
Output - open (duty 100%)
mA
BC1 and BC2=VIL , S=VIL ,S2=VIH
other pins =VIH or VIL
Output - open (duty 100%)
40
Active supply current
( AC,TTL level )
Icc2
f= 1MHz
~ +25°C
5
0.1
-
-
-
>
(1)
(2)
(3)
S1 Vcc - 0.2V,
=
other inputs = 0 ~ Vcc
~ +40°C
~ +70°C
~ +85°C
~ +70°C
~ +85°C
0.2
2
-H, -HI
>
S2 0.2V,
=
-
-
-
-
-
-
-
-
8
Stand by supply current
( AC,MOS level )
other inputs = 0 ~ Vcc
Icc3
µA
15
16
30
-HI
-L, -LI
-LI
>
BC1 and BC2 Vcc - 0.2V
=
>
<
S1 0.2V, S2 Vcc - 0.2V
=
=
other inputs = 0 ~ Vcc
Stand by supply current
( AC,TTL level )
BC1 and BC2=VIH or S1=VIH or S2=VIL
Other inputs= 0 ~ Vcc
mA
-
-
0.5
Icc4
<
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical parameter indicates the value for the center of distribution at 2.7V, and not 100% tested.
* -1.0V in case of AC (Pulse width 30ns)
=
(Vcc=1.8 ~ 2.7V, unless otherwise noted)
CAPACITANCE
Limits
Typ
Symbol
Conditions
Parameter
Units
pF
Min
Max
10
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
CO
10
3
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=1.8 ~ 2.7V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
1TTL
Supply voltage
1.8~2.7V
Input pulse
VIH=0.7 x Vcc, VIL=0.2V
5ns
DQ
Input rise time and fall time
CL
Transition is measured ±200mV from
Reference level
Output loads
VOH=VOL=0.9V
steady state voltage.(for ten,tdis)
Including scope and
jig capacitance
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
85L, 85H,
85LI, 85HI
10L, 10H,
10LI, 10HI
Units
Parameter
Symbol
Min
Max
Min
Max
tCR
ta(A)
ta(S1)
ta(S2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after BC1 high
Output disable time after BC2 high
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after BC1 low
Output enable time after BC2 low
Output enable time after OE low
85
100
85
85
85
85
85
45
30
30
30
30
30
100
100
100
100
100
50
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
tdis(BC1)
tdis(BC2)
ten(OE)
35
35
35
35
35
10
10
10
10
5
10
10
10
10
5
tV(A)
10
10
Data valid time after address
ns
(3) WRITE CYCLE
Limits
85L, 85H,
85LI, 85HI
10L, 10H,
10LI, 10HI
Units
Symbol
Parameter
Min
Max
Min
Max
ns
ns
ns
ns
ns
Write cycle time
Write pulse width
100
75
0
85
85
85
85
85
50
85
60
0
tCW
tw(W)
tsu(A)
Address setup time
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
70
70
70
70
70
45
0
0
ns
ns
ns
ns
ns
ns
ns
ns
th(D)
0
0
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
30
30
35
35
5
5
5
5
ns
ns
Output enable time from OE low
4
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~18
tv (A)
ta(A)
ta(BC1) or
ta(BC2)
BC1,BC2
(Note3)
(Note3)
tdis (BC1) or tdis (BC1)
tdis (S1)
ta(S1)
S1
S2
OE
(Note3)
(Note3)
(Note3)
(Note3)
ta(S2)
tdis (S2)
ta (OE)
(Note3)
(Note3)
ten (OE)
tdis (OE)
W = "H" level
DQ1~16
ten (BC1)
ten (BC2)
VALID DATA
ten (S1)
ten (S2)
Write cycle
( W control mode )
tCW
A0~18
tsu (BC1) or tsu(BC2)
BC1,BC2
S1
(Note3)
(Note3)
tsu (S1)
tsu (S2)
(Note3)
(Note3)
(Note3)
(Note3)
S2
OE
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
W
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ1~16
tsu (D)
th (D)
5
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
tCW
A0~18
tsu (BC1) or
tsu (BC2)
trec (W)
tsu (A)
BC1,BC2
S1
(Note3)
(Note3)
(Note3)
(Note3)
S2
W
(Note5)
(Note4)
tsu (D)
(Note3)
(Note3)
th (D)
DATA IN
STABLE
DQ1~16
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S1 low, S2 high overlaps BC1 and/or BC2 low and W low.
Note 5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
6
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S1 control mode)
tCW
A0~18
BC1,BC2
(Note3)
(Note3)
trec (W)
tsu (S1)
tsu (A)
S1
S2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
Write cycle (S2 control mode)
tCW
A0~18
BC1,BC2
(Note3)
(Note3)
trec (W)
tsu (S2)
tsu (A)
S1
S2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
7
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
1999.1.15
Ver. 0.1
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Vcc (PD)
VI (BC)
Parameter
Test conditions
Units
V
Typ
Min
1.0
Max
Power down supply voltage
Vcc(PD)
Vcc(PD)
Vcc(PD)
Vcc(PD)
0.7xVcc
1.8V
1.0V
1.8V
1.0V
Byte control input BC1 & BC2
V
V
1.8V
1.8V
Vcc(PD)
0.7xVcc
VI (S1)
VI (S2)
Chip select input S1
Chip select input S2
Vcc(PD)
0.02
0.05
-
-
0.2
0.5
1
Vcc=1.0V
~ +25°C
~ +40°C
~ +70°C
~ +85°C
~ +70°C
-
-
-
-
-
-
>
(1)
S1 Vcc - 0.2V,
=
-H, -HI
other inputs = 0 ~ Vcc
Power down
supply current
>
4
7.5
(2)
S2 0.2V,
Icc (PD)
=
µA
other inputs = 0 ~ Vcc
-HI
-L, -LI
>
(3)
BC1 and BC2 Vcc - 0.2V
=
-
-
8
15
>
<
S1 0.2V, S2 Vcc - 0.2V
=
=
other inputs = 0 ~ Vcc
-LI
~ +85°C
Note 2: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 1.0V, and not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Symbol
Parameter
Units
Test conditions
Typ
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
ns
ms
5
Power down recovery time
(3) TIMING DIAGRAM
BC control mode
Vcc
1.8V
1.8V
tsu (PD)
trec (PD)
0.7 x Vcc
BC1
BC2
0.7 x Vcc
>
BC1 , BC2 Vcc-0.2V
=
S1 control mode
Vcc
1.8V
1.8V
1.8V
tsu (PD)
trec (PD)
0.7 x Vcc
0.7 x Vcc
S1
>
S1 Vcc-0.2V
=
S2 control mode
Vcc
1.8V
S2
tsu (PD)
trec (PD)
Vcc-0.2V
0.7 x Vcc
S2 0.2V
8
MITSUBISHI ELECTRIC
相关型号：
M5M5W817KT-70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
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