HAT2195R [RENESAS]
Silicon N Channel Power MOS FET Power Switching; 硅N通道功率MOS FET电源开关
| 型号： | HAT2195R |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Silicon N Channel Power MOS FET Power Switching |
| 文件： | 总7页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HAT2195R
Silicon N Channel Power MOS FET
Power Switching
REJ03G0060-0300Z
Rev.3.00
Apr.01.2004
Features
•
•
•
•
•
High speed switching
Capable of 4.5 V gate drive
Low drive current
High density mounting
Low on-resistance
RDS(on) = 4.6 mΩ typ. (at VGS = 10 V)
Outline
SOP-8
5 6
D D
7
D
8
D
5
6
7
4
G
8
1, 2, 3 Source
4 Gate
5, 6, 7, 8 Drain
4
3
2
1
S
1
S
2
S
3
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
VDSS
VGSS
ID
Ratings
Unit
Drain to source voltage
Gate to source voltage
Drain current
30
V
±20
V
18
A
Note1
Drain peak current
ID(pulse)
144
A
Body-drain diode reverse drain current
Avalanche current
IDR
18
A
Note 2
IAP
18
A
Note 2
Avalanche energy
EAR
32.4
mJ
W
°C/W
°C
°C
Channel dissipation
Pch Note3
θch-a Note3
Tch
2.5
Channel to ambient thermal impedance
Channel temperature
50
150
Storage temperature
Tstg
–55 to +150
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. Value at Tch = 25°C, Rg ≥ 50 Ω
3. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW ≤ 10s
Rev.3.00, Apr.01.2004, page 1 of 6
HAT2195R
Electrical Characteristics
(Ta = 25°C)
Item
Symbol Min
Typ
—
Max
—
Unit
V
Test Conditions
Drain to source breakdown voltage
Gate to source leak current
Zero gate voltage drain current
Gate to source cutoff voltage
Static drain to source on state
resistance
V(BR)DSS 30
ID = 10 mA, VGS = 0
IGSS
IDSS
VGS(off)
RDS(on)
RDS(on)
|yfs|
—
—
1.0
—
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
± 0.1
1
µA
µA
V
VGS = ±20 V, VDS = 0
VDS = 30 V, VGS = 0
VDS = 10 V, I D = 1 mA
ID = 9 A, VGS = 10 V Note4
ID = 9 A, VGS = 4.5 V Note4
ID = 9 A, VDS = 10 V Note4
VDS = 10 V
—
—
2.5
5.8
8.4
—
4.6
5.8
42
mΩ
mΩ
S
Forward transfer admittance
Input capacitance
Ciss
Coss
Crss
Rg
3400
785
250
1.0
23
—
pF
pF
pF
Ω
Output capacitance
—
VGS = 0
Reverse transfer capacitance
Gate Resistance
—
f = 1 MHz
—
Total gate charge
Qg
—
nC
nC
nC
ns
ns
ns
ns
V
VDD = 10 V
Gate to source charge
Gate to drain charge
Turn-on delay time
Qgs
Qgd
td(on)
tr
10
—
VGS = 4.5 V
5.5
12
—
ID = 18 A
—
VGS = 10 V, ID = 9 A
VDD 10 V
Rise time
16
—
Turn-off delay time
td(off)
tf
50
—
RL = 1.11 Ω
Fall time
6.5
0.80
32
—
Rg = 4.7 Ω
IF = 18 A, VGS = 0 Note4
Body–drain diode forward voltage
VDF
1.04
—
Body–drain diode reverse recovery
time
trr
ns
IF = 18 A, VGS = 0
diF/ dt = 100 A/ µs
Notes: 4. Pulse test
Main Characteristics
Power vs. Temperature Derating
Maximum Safe Operation Area
10 µs
4.0
3.0
2.0
1.0
500
100
Test Condition :
When using the glass epoxy board
(FR4 40x40x1.6 mm), PW < 10 s
10
1
Operation in
this area is
limited by RDS(on)
0.1
Ta = 25 °C
1 shot Pulse
0.01
0
0.1
50
100
150
200
0.3
1
3
10
30
100
Drain to Source Voltage VDS (V)
Ambient Temperature Ta (°C)
Note 5 :
When using the glass epoxy board
(FR4 40x40x1.6 mm)
Rev.3.00, Apr.01.2004, page 2 of 6
HAT2195R
Typical Output Characteristics
10 V
Typical Transfer Characteristics
50
40
30
20
10
50
40
30
20
10
2.8 V
V
= 10 V
DS
Pulse Test
4 V
2.6 V
25°C
Tc = 75°C
V
GS = 2.4 V
–25°C
Pulse Test
0
0
5
1
2
3
Gate to Source Voltage VGS (V)
4
2
4
6
8
10
Drain to Source Voltage VDS (V)
Static Drain to Source on State Resistance
vs. Drain Current
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
100
200
160
120
80
Pulse Test
Pulse Test
50
20
10
5
ID = 20 A
VGS = 4.5 V
10 V
10 A
5 A
40
2
1
0
4
8
12
16
20
1
3
10
30 100 300 1000
Gate to Source Voltage VGS (V)
Drain Current ID (A)
Static Drain to Source on State Resistance
vs. Temperature
Forward Transfer Admittance vs.
Drain Current
12
1000
Pulse Test
300
100
Tc = –25 °C
20 A
10
8
5 A, 10 A
30
10
VGS = 4.5 V
75 °C
25 °C
6
3
1
ID = 5 A, 10 A, 20 A
4
VDS = 10 V
Pulse Test
10 V
0.3
0.1
2
0.1 0.3
3
30
–25
0
25 50 75 100 125 150
1
10
100
Case Temperature Tc (°C)
Drain Current ID (A)
Rev.3.00, Apr.01.2004, page 3 of 6
HAT2195R
Body Drain Diode Reverse
Recovery Time
Typical Capacitance vs.
Drain to Source Voltage
10000
100
Ciss
3000
1000
50
Coss
Crss
300
100
20
10
30
10
di/dt = 100 A/µs
VGS = 0
VGS = 0, Ta = 25°C
f = 1 MHz
0.1 0.3
1
3
10
30
100
0
5
10
15
20
25
30
Reverse Drain Current IDR (A)
Drain to Source Voltage VDS (V)
Dynamic Input Characteristics
Switching Characteristics
50
40
30
20
10
20
16
12
8
1000
ID = 18 A
VGS
300
100
t
r
t
d(off)
VDS
VDD = 25 V
10 V
5 V
30
10
t
d(on)
t
f
4
VDD = 25 V
10 V
5 V
3
1
VGS = 10 V, VDS = 10 V
Rg = 4.7 Ω, duty < 1 %
0
0.1 0.3
1
3
10
30
100
0
20
40
60
80
100
Drain Current ID (A)
Gate Charge Qg (nC)
Maximum Avalanche Energy vs.
Channel Temperature Derating
Reverse Drain Current vs.
Source to Drain Voltage
50
40
30
20
10
50
40
30
20
I
AP = 18 A
V
DD = 15 V
10 V
duty < 0.1 %
Rg > 50 Ω
VGS = –5.0 V
5 V
10
0
Pulse Test
1.6
Source to Drain Voltage VSD (V)
0
0.4
0.8
1.2
2.0
25
50
75
100
125
150
Channel Temperature Tch (°C)
Rev.3.00, Apr.01.2004, page 4 of 6
HAT2195R
Normalized Transient Thermal Impedance vs. Pulse Width
10
D = 1
0.5
1
0.1
0.1
θch - f(t) = γs (t) x θch - f
θch - f = 83.3°C/W, Ta = 25°C
When using the glass epoxy board
(FR4 40x40x1.6 mm)
0.01
PW
T
P
DM
D =
0.001
PW
T
0.0001
100 µ
1 m
10 m
100 m
1
10
100
1000
10000
10 µ
Pulse Width PW (S)
Avalanche Test Circuit
Avalanche Waveform
VDSS
1
2
EAR
=
L • IAP •
VDSS – VDD
2
L
VDS
Monitor
I
AP
Monitor
V
(BR)DSS
IAP
Rg
VDS
VDD
D. U. T
ID
Vin
15 V
50 Ω
VDD
0
Switching Time Test Circuit
Vin Monitor
Switching Time Waveform
Vout
Monitor
90%
D.U.T.
Rg
RL
10%
10%
Vin
VDS
= 10 V
Vin
10 V
Vout
10%
90%
90%
td(off)
td(on)
t
f
tr
Rev.3.00, Apr.01.2004, page 5 of 6
HAT2195R
Package Dimensions
As of January, 2003
Unit: mm
4.90
5.3 Max
8
5
1
4
+ 0.10
– 0.30
ꢀ.10
0.75 Max
1.08
0˚ – 8˚
+ 0.ꢀ7
– 0.20
0.ꢀ0
1.27
*0.42 0.08
0.40 0.0ꢀ
0.15
M
0.25
Package Code
JEDEC
JEITA
FP-8DA
Conforms
—
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
0.085 g
Ordering Information
Part Name
Quantity
Shipping Container
HAT2195R-EL-E
2500pcs
Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.3.00, Apr.01.2004, page 6 of 6
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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