HAT2197R [RENESAS]
Silicon N Channel Power MOS FET Power Switching; 硅N通道功率MOS FET电源开关
| 型号： | HAT2197R |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Silicon N Channel Power MOS FET Power Switching |
| 文件： | 总8页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HAT2197R
Silicon N Channel Power MOS FET
Power Switching
REJ03G0061-0200Z
Rev.2.00
Apr.02.2004
Features
•
•
•
•
•
High speed switching
Capable of 4.5 V gate drive
Low drive current
High density mounting
Low on-resistance
RDS(on) = 5.3 mΩ typ. (at VGS = 10 V)
Outline
SOP-8
5
6
7
8
4
3
2
1
5 6
7
8
D D
D
D
4
G
1, 2, 3
4
Source
Gate
5, 6, 7, 8 Drain
S
1
S
2
S
3
Rev.2.00, Apr.02.2004, page 1 of 7
HAT2197R
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
VDSS
VGSS
ID
Ratings
30
Unit
V
Drain to source voltage
Gate to source voltage
Drain current
±20
V
16
A
Note1
Drain peak current
ID(pulse)
128
A
Body-drain diode reverse drain current IDR
16
A
Note 2
Note 2
Avalanche current
Avalanche energy
Channel dissipation
IAP
16
A
EAR
Pch Note3
25.6
2.5
mJ
W
Channel to ambient thermal impedance θch-a Note3
50
°C/W
°C
°C
Channel temperature
Tch
150
Storage temperature
Tstg
–55 to +150
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. Value at Tch = 25°C, Rg ≥ 50 Ω
3. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW ≤ 10s
Electrical Characteristics
(Ta = 25°C)
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V(BR)DSS 30
—
—
V
ID = 10 mA, VGS = 0
Gate to source leak current
Zero gate voltage drain current
Gate to source cutoff voltage
Static drain to source on state
resistance
IGSS
IDSS
VGS(off)
RDS(on)
RDS(on)
|yfs|
—
—
1.0
—
—
22
—
—
—
—
—
—
—
—
—
—
—
—
—
—
± 0.1
1
µA
µA
V
VGS = ±20 V, VDS = 0
VDS = 30 V, VGS = 0
VDS = 10 V, I D = 1 mA
ID = 8 A, VGS = 10 V Note4
ID = 8 A, VGS = 4.5 V Note4
ID = 8 A, VDS = 10 V Note4
VDS = 10 V
—
—
2.5
6.7
9.9
—
5.3
6.8
38
mΩ
mΩ
S
Forward transfer admittance
Input capacitance
Ciss
Coss
Crss
Rg
2650
610
190
1.2
18
—
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Gate Resistance
—
VGS = 0
—
f = 1 MHz
—
Total gate charge
Qg
—
nC
nC
nC
ns
ns
ns
ns
V
VDD = 10 V
Gate to source charge
Gate to drain charge
Turn-on delay time
Qgs
Qgd
td(on)
tr
7.5
4.2
10
—
VGS = 4.5 V
—
ID = 16 A
—
VGS = 10 V, ID = 8 A
VDD 10 V
Rise time
25
—
Turn-off delay time
td(off)
tf
45
—
RL = 1.25 Ω
Fall time
4.2
0.80
30
—
Rg = 4.7 Ω
IF = 16 A, VGS = 0 Note4
Body–drain diode forward voltage VDF
1.04
—
Body–drain diode reverse
recovery time
trr
ns
IF = 16 A, VGS = 0
diF/ dt = 100 A/ µs
Notes: 4. Pulse test
Rev.2.00, Apr.02.2004, page 2 of 7
HAT2197R
Power vs. Temperature Derating
Maximum Safe Operation Area
500
100
4.0
Test Condition :
When using the glass epoxy board
(FR4 40x40x1.6 mm), PW < 10 s
10 µs
3.0
2.0
1.0
10
1
Operation in
this area is
limited by R
DS(on)
0.1
Ta = 25°C
1 shot Pulse
0.01
0
0.1
0.3
1
3
10
30
100
50
100
150
200
Drain to Source Voltage
V
(V)
DS
Ambient Temperature Ta (°C)
Note 4 :
When using the glass epoxy board
(FR4 40x40x1.6 mm)
Typical Output Characteristics
Typical Transfer Characteristics
20
16
12
8
20
16
12
8
10 V
Pulse Test
V
= 10 V
DS
Pulse Test
2.8 V
2.6 V
2.5 V
Tc = 75°C
V
GS
= 2.4 V
25°C
4
4
–25°C
0
0
5
1
2
3
Gate to Source Voltage
4
(V)
GS
2
4
6
8
10
V
Drain to Source Voltage
V
(V)
DS
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Static Drain to Source on State Resistance
vs. Drain Current
100
200
160
120
80
Pulse Test
Pulse Test
50
20
10
5
V
GS
= 4.5 V
I
= 20 A
10 A
D
10 V
40
2
1
5 A
16
0
4
8
12
Gate to Source Voltage
20
1
10
Drain Current
100
1000
V
(V)
GS
I
(A)
D
Rev.2.00, Apr.02.2004, page 3 of 7
HAT2197R
Static Drain to Source on State Resistance
vs. Temperature
Forward Transfer Admittance vs.
Drain Current
1000
100
12
10
8
Pulse Test
I
= 20 A
D
Tc = –25°C
5, 10 A
V
= 4.5 V
GS
10
1
25°C
6
5 A, 10 A, 20 A
75°C
10 V
4
2
V
= 10 V
DS
Pulse Test
0.1 0.3
3
30
(A)
-25
0
25 50 75 100 125 150
1
10
100
Case Temperature Tc (°C)
Drain Current
I
D
Body–Drain Diode Reverse
Recovery Time
Typical Capacitance vs.
Drain to Source Voltage
10000
100
50
Ciss
3000
1000
Coss
300
100
Crss
20
10
30
10
di/dt = 100 A/µs
V
GS
= 0
V
GS
= 0, Ta = 25°C
f = 1 MHz
0.1
1
10
100
(A)
0
5
10
15
20
25 30
Reverse Drain Current
I
DR
Drain to Source Voltage
V
(V)
DS
Dynamic Input Characteristics
= 16 A
Switching Characteristics
50
40
30
20
10
20
16
12
8
1000
100
I
V
= 10 V , V = 10 V
DS
D
GS
Rg = 4.7 , duty < 1 %
Ω
V
= 25 V
10 V
5 V
DD
t
r
V
GS
t
d(off)
V
DS
t
d(on)
10
1
4
0
V
= 25 V
10 V
5 V
DD
t
f
0.1
1
10
100
0
16
32
48
64
80
Drain Current
I
(A)
Gate Charge Qg (nC)
D
Rev.2.00, Apr.02.2004, page 4 of 7
HAT2197R
Maximum Avalanche Energy vs.
Channel Temperature Derating
Reverse Drain Current vs.
Source to Drain Voltage
20
16
12
8
50
40
30
20
I
= 16 A
= 15 V
AP
V
10 V
DD
duty < 0.1 %
Ω
V
= 0 V
Rg > 50
GS
5 V
4
10
0
Pulse Test
1.6 2.0
0
0.4
0.8
1.2
25
50
75
100
125
150
Channel Temperature Tch (°C)
Source to Drain Voltage
V
(V)
SD
Normalized Transient Thermal Impedance vs. Pulse Width
10
D = 1
0.5
1
0.1
0.1
θ
θ
γ
θ
ch - f(t) = s (t) x ch - f
ch - f = 83.3°C/W, Ta = 25°C
0.01
0.001
When using the glass epoxy board
(FR4 40 x 40 x 1.6 mm)
PW
T
P
DM
D =
PW
T
0.0001
100 µ
1 m
10 m
100 m
1
10
100
1000
10000
10 µ
Pulse Width PW (s)
Rev.2.00, Apr.02.2004, page 5 of 7
HAT2197R
Avalanche Test Circuit
Avalanche Waveform
V
DSS
1
2
EAR
=
L
•
IAP
•
V
- V
DD
DSS
2
L
V
DS
Monitor
I
AP
Monitor
V
(BR)DSS
I
AP
Rg
V
V
DD
D. U. T
DS
I
D
Vin
15 V
50Ω
V
DD
0
Switching Time Test Circuit
Vin Monitor
Switching Time Waveform
Vout
Monitor
90%
D.U.T.
Rg
10%
10%
Vin
R
L
Vout
10%
V
DS
= 10 V
Vin
10 V
90%
tr
90%
td(off)
td(on)
t
f
Rev.2.00, Apr.02.2004, page 6 of 7
HAT2197R
Package Dimensions
As of January, 2003
Unit: mm
4.90
5.3 Max
8
5
1
4
+ 0.10
– 0.30
6.10
0.75 Max
1.27
1.08
0˚ – 8˚
+ 0.67
– 0.20
0.60
*0.42 0.08
0.40 0.06
0.15
M
0.25
Package Code
JEDEC
JEITA
FP-8DA
Conforms
—
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
0.085 g
Ordering Information
Part Name
Quantity
Shipping Container
HAT2197R-EL-E
2500pcs
Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to
check the state of production before ordering the product.
Rev.2.00, Apr.02.2004, page 7 of 7
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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