HAT2198R [RENESAS]
Silicon N Channel Power MOS FET Power Switching; 硅N通道功率MOS FET电源开关
| 型号： | HAT2198R |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Silicon N Channel Power MOS FET Power Switching |
| 文件： | 总8页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HAT2198R
Silicon N Channel Power MOS FET
Power Switching
REJ03G0062-0200
Rev.2.00
Oct.18.2004
Features
•
•
•
•
•
High speed switching
Capable of 4.5 V gate drive
Low drive current
High density mounting
Low on-resistance
RDS(on) = 7.2 mΩ typ. (at VGS = 10 V)
Outline
SOP-8
5
6
7
8
D
D
D
D
5
6
7
8
4
G
1, 2, 3 Source
4 Gate
5, 6, 7, 8 Drain
4
3
2
1
S
1
S
2
S
3
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Symbol
VDSS
VGSS
ID
Ratings
Unit
V
30
±20
V
14
A
Note1
Drain peak current
ID(pulse)
112
A
Body-drain diode reverse drain current
Avalanche current
IDR
14
A
Note 2
IAP
14
A
Note 2
Avalanche energy
EAR
19.6
2.5
mJ
W
Channel dissipation
Pch Note3
θch-a Note3
Tch
Channel to ambient thermal impedance
Channel temperature
Storage temperature
50
°C/W
°C
°C
150
Tstg
–55 to +150
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. Value at Tch = 25°C, Rg ≥ 50 Ω
3. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW ≤ 10s
Rev.2.00, Oct.18.2004, page 1 of 7
HAT2198R
Electrical Characteristics
(Ta = 25°C)
Item
Symbol
Min
30
—
—
1.0
—
—
18
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
Max
—
Unit
V
Test Conditions
Drain to source breakdown voltage V(BR)DSS
ID = 10 mA, VGS = 0
VGS = ±20 V, VDS = 0
VDS = 30 V, VGS = 0
VDS = 10 V, I D = 1 mA
ID = 7 A, VGS = 10 V Note4
ID = 7 A, VGS = 4.5 V Note4
ID = 7 A, VDS = 10 V Note4
VDS = 10 V
Gate to source leak current
Zero gate voltage drain current
Gate to source cutoff voltage
IGSS
IDSS
VGS(off)
RDS(on)
RDS(on)
|yfs|
—
± 0.1
1
µA
µA
V
—
—
2.5
9.0
14.0
—
Static drain to source on state
resistance
7.2
9.6
30
mΩ
mΩ
S
Forward transfer admittance
Input capacitance
Ciss
Coss
Crss
Rg
1650
390
135
0.55
11
—
pF
pF
pF
Ω
V
GS = 0
f = 1 MHz
Output capacitance
Reverse transfer capacitance
Gate Resistance
—
—
—
Total gate charge
Qg
—
nC
nC
nC
ns
ns
ns
ns
V
VDD = 10 V
GS = 4.5 V
ID = 14 A
V
Gate to source charge
Gate to drain charge
Turn-on delay time
Rise time
Qgs
Qgd
td(on)
tr
4.7
2.5
8.5
5
—
—
—
VGS = 10 V, ID = 7 A
VDD 10 V
RL = 1.42 Ω
Rg = 4.7 Ω
—
Turn-off delay time
Fall time
td(off)
tf
38
—
3.8
0.80
28
—
Body–drain diode forward voltage
VDF
1.04
—
IF = 14 A, VGS = 0 Note4
Body–drain diode reverse recovery
time
trr
ns
IF = 14 A, VGS = 0
diF/ dt = 100 A/ µs
Notes: 4. Pulse test
Rev.2.00, Oct.18.2004, page 2 of 7
HAT2198R
Main Characteristics
Power vs. Temperature Derating
Maximum Safe Operation Area
500
100
4.0
3.0
2.0
1.0
Test Condition :
When using the glass epoxy board
(FR4 40 x 40 x 1.6 mm), PW < 10 s
10
µ
s
PW = 10
10
1
s
Operation in
this area is
limited by RDS(on)
0.1
Ta = 25°C
1 shot Pulse
0.01
0
0.1
0.3
1
3
10
30
100
50
100
150
200
Drain to Source Voltage
V
(V)
DS
Ambient Temperature Ta (°C)
Note 5 :
When using the glass epoxy board
(FR4 40x40x1.6 mm)
Typical Output Characteristics
Typical Transfer Characteristics
20
16
12
8
20
16
12
8
10 V
3 V
Pulse Test
V
= 10 V
DS
Pulse Test
2.8 V
2.6 V
Tc = 75°C
25°C
–25°C
V
GS = 2.4 V
4
4
0
0
5
1
2
3
Gate to Source Voltage VGS (V)
4
2
4
6
8
10
Drain to Source Voltage
V
(V)
DS
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Static Drain to Source on State Resistance
vs. Drain Current
100
300
240
180
120
60
Pulse Test
Pulse Test
50
V
= 4.5 V
10 V
GS
20
10
5
I
= 20 A
D
10 A
5 A
2
1
0
4
8
12
16
Gate to Source Voltage VGS (V)
20
1
10
Drain Current
100
1000
I
(A)
D
Rev.2.00, Oct.18.2004, page 3 of 7
HAT2198R
Static Drain to Source on State Resistance
vs. Temperature
Forward Transfer Admittance vs.
Drain Current
1000
100
20
Pulse Test
20 A
Tc = –25°C
16
12
8
I
D
= 5 A, 10 A
V
GS
= 4.5 V
10
1
25°C
75°C
5 A, 10 A, 20 A
10 V
4
0
V
= 10 V
DS
Pulse Test
0.1 0.3
3
30
(A)
-25
0
25 50 75 100 125 150
1
10
100
Case Temperature Tc (°C)
Drain Current
I
D
Body–Drain Diode Reverse
Recovery Time
Typical Capacitance vs.
Drain to Source Voltage
10000
100
50
3000
1000
Ciss
Coss
Crss
300
100
20
10
30
10
di/dt = 100 A/µs
V
= 0
GS
f = 1 MHz
V
= 0, Ta = 25°C
GS
0.1
1
10
100
(A)
0
5
10
15
20
25 30
Reverse Drain Current
I
DR
Drain to Source Voltage
V
(V)
DS
Dynamic Input Characteristics
= 14 A
Switching Characteristics
50
40
30
20
10
20
16
12
8
1000
100
I
D
V
= 10 V, V = 10 V
DS
Rg = 4.7 Ω, duty < 1 %
GS
V
GS
V
= 25 V
10 V
5 V
DD
t
d(off)
V
DS
t
r
t
d(on)
10
1
V
= 25 V
10 V
5 V
DD
4
0
t
f
0.1
1
10
100
0
8
16
24
32
40
Drain Current
I
D
(A)
Gate Charge Qg (nc)
Rev.2.00, Oct.18.2004, page 4 of 7
HAT2198R
Maximum Avalanche Energy vs.
Channel Temperature Derating
Reverse Drain Current vs.
Source to Drain Voltage
20
16
12
8
20
16
12
8
I
= 11 A
AP
10 V
5 V
V
= 15 V
DD
duty < 0.1 %
Rg > 50 Ω
V
= 0,-5 V
GS
4
4
0
Pulse Test
1.6 2.0
0
0.4
0.8
1.2
25
50
75
100
125
150
Channel Temperature Tch (°C)
Source to Drain Voltage
V
SD
(V)
Normalized Transient Thermal Impedance vs. Pulse Width
10
D = 1
0.5
1
0.1
0.1
θch - f(t) = γs (t) x θch - f
θch - f = 83.3°C/W, Ta = 25°C
When using the glass epoxy board
(FR4 40 x 40 x 1.6 mm)
0.01
0.001
PW
T
P
DM
D =
PW
T
0.0001
100 µ
1 m
10 m
100 m
1
10
100
1000
10000
10 µ
Pulse Width PW (s)
Rev.2.00, Oct.18.2004, page 5 of 7
HAT2198R
Avalanche Test Circuit
Avalanche Waveform
V
DSS
1
2
EAR
=
L
•
IAP
•
V
- V
DD
DSS
2
L
V
DS
Monitor
I
AP
Monitor
V
(BR)DSS
I
AP
Rg
V
V
DD
D. U. T
DS
I
D
Vin
15 V
50Ω
V
DD
0
Switching Time Test Circuit
Vin Monitor
Switching Time Waveform
Vout
Monitor
90%
D.U.T.
Rg
10%
10%
Vin
R
L
Vout
10%
V
DS
= 10 V
Vin
10 V
90%
tr
90%
td(off)
td(on)
t
f
Rev.2.00, Oct.18.2004, page 6 of 7
HAT2198R
Package Dimensions
As of January, 2003
Unit: mm
4.90
5.3 Max
8
5
1
4
+ 0.10
– 0.30
ꢀ.10
0.75 Max
1.08
0˚ – 8˚
+ 0.ꢀ7
– 0.20
0.ꢀ0
1.27
*0.42 0.08
0.40 0.0ꢀ
0.15
M
0.25
Package Code
JEDEC
JEITA
FP-8DA
Conforms
—
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
0.085 g
Ordering Information
Part Name
HAT2198R-EL-E
Quantity
Shipping Container
2500 pcs
Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.2.00, Oct.18.2004, page 7 of 7
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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