FS8108 [PTC]
Low Power Phase-Locked Loop IC; 低功耗锁相环IC
| 型号： | FS8108 |
| 厂家： | 
PRINCETON TECHNOLOGY CORP |
| 描述： | Low Power Phase-Locked Loop IC |
| 文件： | 总10页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FS8108 Low Power Phase-Locked Loop IC
Princeton Technology Corp. reserves the right to change the product described in this datasheet. All information con-
tained in this datasheet is subject to change without prior notice. Princeton Technology Corp. assumes no responsibility
for the use of any circuits shown in this datasheet.
Description
The FS8108 is a serial data input, phase-locked loop IC with programmable input and ref-
erence frequency dividers. When combined with a VCO, the FS8108 becomes the core of
a very low power frequency synthesizer well-suited for mobile communication applica-
tions such as paging systems. The FS8108 includes an 18-bit programmable input fre-
quency divider and also implements a separate pin for stand-by control.
Features
High maximum input operating frequency — 185 MHz at VDD1 = 1.0 V
Up to 22 MHz internal crystal oscillator reference frequency at VDD1 = 1.0 V
Extremely low current consumption (IDD,total typically 0.4 mA at fFIN = 90 MHz)
18-bit programmable input frequency divider (including a ÷ 64/65 prescaler) with
divide ratio range from 4032 to 262143
13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with
divide ratio range from 40 to 65528
Optional lock detector output
Charge pump output for passive low-pass filter
Quick-lock signal output for faster locking
Separate pin for stand-by control
TSSOP 16L package (0.65mm pitch)
Applications
Pager
Wireless communication system
Page 1
Jan 2003
FS8108
Package and Pin Assignment: 16L, TSSOP
1
2
3
4
5
6
7
8
16
XIN
TEST
NC
15
14
13
12
11
10
9
XOUT
VDD2
DB
OPR
LE
DO
DATA
CLK
LD
VSS
FIN
VDD1
NC
Dimensions in mm
Dimensions in inch
Symbols
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.30
0.20
5.10
---
MIN.
---
NOM.
---
MAX.
0.048
0.006
0.041
0.012
0.008
0.201
---
A
A1
A2
b
0.05
0.80
0.19
0.09
4.90
---
---
0.002
0.031
0.007
0.004
0.193
---
---
1.00
---
0.039
---
C
---
---
D
E
5.00
6.40
4.40
0.65
0.60
---
0.197
0.252
0.173
0.026
0.024
---
E1
e
4.30
---
4.50
---
0.169
---
0.177
---
L
0.45
---
0.75
0.10
0.018
---
0.030
0.004
y
θ
---
---
0
°
8
°
0
°
8
°
Note: Tolerance + 0.1mm unless otherwise specified
Page 2
Jan 2003
FS8108
Pin Descriptions
Number
1
Name
XIN
I/O
I
Description
Reference crystal oscillator or external clock input with internally biased amplifier
(any external input to XIN must be ac-coupled)
2
3
4
5
6
XOUT
VDD2
DB
O
Reference crystal oscillator or external clock output
POWER Nominal 3.0 V supply voltage
O
O
Single-ended quick-lock output for faster locking
DO
Single-ended charge pump output for passive low pass filter
Ground
VSS
GND
VCO frequency input with internally biased input amplifier
(any external input to FIN must be ac-coupled)
7
FIN
I
8
VDD1
NC
POWER Nominal 1.0 V supply voltage
9
NC
No connection
10
11
12
13
14
15
16
LD
O
Lock detector output (high when PLL is locked)
Shift register clock input
CLK
DATA
LE
I
I
Serial data input
I
I
Latch enable input
OPR
NC
Battery-save control input; normal operation when high, stand-by mode when low
No connection
NC
I
TEST
Test mode control input with internal pull-down resistor
Block Diagram
FIN
÷ 64/65
N-COUNTER
LOCK
DETECTOR
LD
DO
DB
N-LATCH
DATA
CLK
LE
TEST
OPR
CONTROL
LOGIC
CHARGE
PUMP
SHIFT REGISTER
PFD
R-LATCH
QUICK-
LOCK
XIN
R-COUNTER
÷ 8
WINDOW
GENERATOR
XOUT
Page 3
Jan 2003
FS8108
Absolute Maximum Ratings
VSS = 0 V
Parameter
Symbol
VDD1
VDD2
VFIN
Rating
Unit
V
VSS – 0.3 to VSS + 2.0
VSS – 0.3 to VSS + 7.0
VSS – 0.3 to VDD + 0.3
Supply voltage
V
Input voltage range
V
oC
oC
oC
s
TOPR
Operating temperature range
Storage temperature range
Soldering temperature range
Soldering time range
–10 to 60
–40 to 125
255
TSTG
TSLD
tSLD
10
Recommended Operating Conditions
VSS = 0 V
Value
Parameter
Symbol
Unit
min.
0.95
typ.
1.0
max.
2.0
VDD1
VDD2
TA
V
V
Supply voltage range
Operating temperature
2.0
3.0
25
3.3
60
oC
–10
Page 4
Jan 2003
FS8108
Electrical Characteristics
(VDD1 = 0.95 to 2.0 V, VDD2 = 2.7 to 3.3 V, VSS = 0 V, TA = 0 to 60
°
C
unless otherwise noted)
Value
Parameter
Symbol
Condition
Unit
mA
min.
typ.
max.
1.10
VDD1 = 1.0 V, OPR=”H”,
VFIN = 0.3 Vpk-pk sinusoid,
IDD,total
fFIN = 100 MHz,
Current consumption
0.40
VXIN = 0.3 Vpk-pk sinusoid,
fXIN = 12.8 MHz
Standby current consumption (IDD2
FIN operating frequency range
XIN operating frequency range
FIN input voltage swing
)
IDD,standby
fFIN
VDD1 = 0 V, OPR=”L”
10
185
25
µA
MHz
MHz
Vpk-pk
Vpk-pk
V
VFIN = 0.3 Vpk-pk sinusoid
VXIN = 0.3 Vpk-pk sinusoid
20
7
fXIN
VFIN
VXIN
VIL
0.3
0.3
XIN input voltage swing
CLK, DATA, LE logic LOW input voltage
CLK, DATA, LE logic HIGH input voltage
0.3
VDD
0.3
-
VIH
V
IIL,XIN
IIH,XIN
IIL,FIN
IIH,FIN
IOL,DOP
IOH,DOP
IOL
VIL = 0 V
VIH = VDD1
XIN logic LOW input current
XIN logic HIGH input current
FIN logic LOW input current
FIN logic HIGH input current
DO logic LOW output current
DO logic HIGH output current
LD, FV, FR logic LOW output current
LD, FV, FR logic HIGH output current
DATA to CLK setup time
10
10
60
60
µA
µA
µA
µA
mA
mA
mA
mA
µs
VIL = 0 V
VIH = VDD1
VOL = 0.4 V
1.0
1.0
0.1
0.1
2
VOH = VDD2 – 0.4 V
VOL = 0.4 V
IOH
VOH = VDD2 – 0.4 V
tSU1
tSU2
CLK to LE setup time
2
µs
tHOLD
Hold time
2
µs
Page 5
Jan 2003
FS8108
Functional Description
Programmable Input Frequency Divider
The VCO input to the FIN pin is divided by the programmable divider and then internally
output to the phase/frequency detector (PFD) as fV. The programmable input frequency
divider consists of a ÷ 64/65 (P/P+1) dual-modulus prescaler and a 18-bit (N) counter,
which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B) counter.
The total divide ratio, M, is related to values for P, A, and B through the relation
M = (P+ 1) × A+ P× (B– A) = P× B+ A,
with B≥ A. The minimum programmable divisor for continuous counting is given by
P× (P– 1) = 64× 63 = 4032, and the valid total divide ratio range for the input
divider isM = 4032 to 262143.
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable divider and then internally
output to the PFD as fR. The programmable reference frequency divider consists of a fixed
÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to
values for S and R through the relation
T = S× R = 8× R.
The usable divisior range of the reference counter isR = 5 to 8191,and therefore, the
valid total divide ratio range for the reference divider isT = 40 to 65528(in steps of 8.)
Serial Input Data Format
The divide ratios for the input and reference dividers are input using a 19-bit serial inter-
face consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The
format of the serial data is shown in Fig. 1. The data on the DATA line is written to the
shift register on the rising edge of the CLK signal and is input with MSB first, and the last
bit is used as the latch select control bit. The data on the DATA line should be changed on
the falling edge of CLK, and LE should be held low while data is being written to the shift
register. Data is transferred from the shift register to one of the frequency divider latches
when LE is set high. When the latch select control bit is set low, data is loaded to the 18-
bit N-counter latch, and when the latch select control bit is set high, the 2 MSBs are
Page 6
Jan 2003
FS8108
ignored, the next 13 data bits are loaded to the 13-bit R-counter latch and the remaining 3
LSBs are used to control testing modes and should be set as follows for normal operation:
R14 = high, R15 = low, R16 = low. To disable LD output (i.e. set LD low), R14 should be
set low.
Serial input data timing waveforms are shown in Fig. 2.
Fig. 1 – Serial input data format
18-bit data for N-counter
13-bit data for R-counter
ignored
Fig. 2 – Serial input data timing waveforms
DATA
tHOLD
tSU1
CLK
LE
tSU2
DATA
CLK
LE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
Page 7
Jan 2003
FS8108
Phase/Frequency Detector (PFD)
The PFD compares an internal input frequency divider output signal, fV, with an internal
reference frequency divider output signal, fR, and generates an error signal, DO, which is
proportional to the phase error between fV and fR. The DO output is intended for use with
a passive filter as shown in Fig. 3.
The input/output waveforms for the PFD are shown in Fig. 4.
Fig. 3 – Passive low-pass filter circuit
R1
DO
to VCO
R2
C
Fig. 4 – PFD input/output waveforms
fR
fV
high-Z
high-Z
high-Z
DO
LD
Page 8
Jan 2003
FS8108
Quick-lock Signal (DB)
The quick-lock output signal, DB, is provided so that the PLL may achieve higher speed
locking. When connected, the DB output effectively doubles the charge pump current out-
put to the loop filter during the initial start-up of the PLL (when OPR first goes high).
Once the PLL phase error is within a specific tolerance, the quick-lock circuitry sets the
DB output to a high impedance state and the PLL continues toward lock with its normal
charge pump current.
Stand-by Mode
The stand-by mode for the PLL is entered by setting the OPR pin low and VDD1 to 0 V
while the circuit is in operation. In the stand-by mode, the XIN and FIN amplifiers, N-
counter, and R-counter are stopped, the N- and R-counters are also reset, and the DO and
DB outputs are set to the high impedance state. As long as voltage is supplied to VDD2
,
data loaded to the latches is kept. To exit from stand-by mode to normal operation, the
OPR pin must be set high and voltage must again be supplied to VDD1
.
Page 9
Jan 2003
FS8108
Application Circuit
1st IF
amplifier
2nd IF
amplifier Discriminator
Wave
shaper
LNA
1st mixer
2nd mixer
LPF
Frequency
multiplier (×4,5)
2nd LO
1st LO
XIN
XOUT
VDD2
DB
TEST
NC
RAM
CPU
ROM
OPR
LE
DO
DATA
CLK
LD
Decoder
VSS
FIN
VDD1
NC
LCD driver
LCD
Driver
DC/DC
converter
Page 10
Jan 2003
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