FS8806 [ETC]
加密芯片;
ETC 
Preliminary Datasheet
Data Sheet
Product Name
Date
FS8806/FS8826
2007/1/31
1
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
Contents
CONTENTS.........................................................................................................................................................2
1. FEATURES....................................................................................................................................................3
2. GENERAL DESCRIPTION..........................................................................................................................3
3. CONNECTION DIAGRAMS........................................................................................................................3
4. ELECTRICAL SECIFICATIONS.................................................................................................................4
4.1. ABSOLUTE MAXIMUM RATING .........................................................................................................4
4.2. OPERATING CONDITION..................................................................................................................4
4.3. CAPACITANCE ................................................................................................................................4
4.4. DC CHARACTERISTICS...................................................................................................................5
4.5. AC CHARACTERISTICS ...................................................................................................................6
4.5.1. I2C AC Characteristics.........................................................................................................6
4.5.2. SPI AC Characteristics.........................................................................................................7
4.5.3. SPI Mode Selection..............................................................................................................8
5. APPLICATION CIRCUIT ..................................................................................................................9
5.1. ONLY I2C MODE .............................................................................................................................9
5.2. I2C AND SPI MODE.........................................................................................................................9
6. PACKAGE DIMENSION .............................................................................................................................10
7. PRODUCT ORDER INFORMATION.........................................................................................................11
8. REVISION HISTORY...................................................................................................................................12
2
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
1. Features
Secure the authentication and completeness of embedded software
Supports I2C and SPI serial interface with secure information exchanged
Supports I2C standard mode (100 kbit/s) and fast mode (400 kbit/s)
Supports SPI two clock modes, CPOL=0, CPHA=0 and CPOL=1, CPHA=1 under 100 kbit/s or 400
kbit/s.
Support 768 bits EEPROM to store user data
8-pin SOP package
Part Number
FS8806
CLK Frequency Range
1M ~ 10MHz
FS8826
1M ~ 80MHz
2. General Description
FS8806/FS8826 is a companion chip with a solution to authenticate the embedded software license
right at the embedded system. It provides a simple and easy solution to implement authentication
mechanism in an embedded system. Just connect FS8806/FS8826 with host CPU via I2C or SPI and
add pieces of concerto software in original run-time software, then a secure system is ready. The
authentication for the embedded software (ESW) license is also very easy. The ESW failed to run in the
customer board without FS8806/FS8826 companion or the unmatched FS8806/FS8826 connected
with customer board. Two application configurations are shown as below:
Customer Board - A
Customer Board - B
Flash
ESW
ESW
Concerto
Concerto
SW
SW
Main CPU
Main CPU
I2C/SPI
I2C/SPI
FS8806
FS8826
FS8806
FS8826
3. Connection Diagrams
8
7
6
5
VDD
1
2
3
4
SDA
SCL
CLK
GND
FS8806
FS8826
SDOUT
SS_N
RST_N
Pin NO. Pin Name I/O
Description
Open-drain configuration with external pull-up resistor.
I2C serial data or SPI slave data input. 3.3V/5V tolerant.
1
SDA
I/O
Open-drain configuration with external pull-up resistor.
I2C or SPI serial clock. 3.3V/5V tolerant.
Clock input. 3.3V/5V tolerant.
2
SCL
I/O
I
3
4
5
6
CLK
GND
RST_N
SS_N
Ground.
I
I
Low active hardware reset. 3.3V/5V tolerant.
Low active SPI slave select. 3.3V/5V tolerant.
Open-drain output with external pull-up resistor.
SPI slave data output. 3.3V/5V tolerant.
3.3V VDD.
7
8
SDOUT
VDD
I/O
3
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
4. Electrical Secifications
4.1. Absolute Maximum Rating
Symbol
TSTG
Parameter
Min.
-10
Max.
85
Unit
0C
Storage Temperature
VIO
Input and Output Voltage
-0.5
VCC+0.5
V
Electrostatic Discharge Voltage (Human Body
VESD
VESD
-4000
4000
V
mode)
Electrostatic Discharge Voltage (Machine mode)
Latch-up
-200
-200
200
200
V
mA
4.2. Operating Condition
Symbol
Parameter
Min.
3.0
0
Max.
3.6
70
Unit
V
0C
VCC
TA
Supply Voltage
Ambient Operating Temperature
I2C under 100kbit/s
I2C 400kbit/s
1
10
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FS8806
4
10
CLK
SPI under 100kbit/s
SPI 400kbit/s
I2C under 100kbit/s
I2C 400kbit/s
1
10
(Note 1,2)
2.5
1
10
80
32
1
80
FS8826
SPI under 100kbit/s
SPI 400kbit/s
80
CLK
(Note 1,3)
20
80
Note: 1. Concerto software need to do proper modification when CLK frequency changes.
2. CLK frequency must be more than 10 times I2C/SPI serial clock of FS8806.
3. CLK frequency must be more than 80 times I2C/SPI serial clock of FS8826.
4.3. Capacitance
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min.
--
Max.
10
Unit
pF
COUT
VOUT = 0V
--
10
pF
4
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
4.4. DC Characteristics
CLK: 10MHz Operation
Symbol
Parameter
Input Leakage
Current
Test Condition
Min.
Typ.
Max.
Unit
ILI
VIN = VCC or GND
--
0.01
1
uA
Output Leakage
Current
ILO
VOUT = VCC or GND
--
0.01
1
uA
I2C at 100kbit/s
I2C at 400kbit/s
SPI at 100kbit/s
SPI at 400kbit/s
CLK signal is running
CLK signal is stop
VCC = 3.3V
--
--
3.3
3.5
3.3
3.5
160
10
--
--
--
mA
mA
mA
mA
uA
uA
V
ICC1
Operating Current
Operating Current
--
--
ICC2
--
--
ISB1
ISB2
VIL
Standby Current)
Standby Current
--
--
--
--
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
--
0.8
--
VIH
VCC = 3.3V
2.4
--
--
V
VOL
VOH
VCC = 3.3V
--
0.4
--
V
VCC = 3.3V
3
--
V
5
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
4.5. AC Characteristics
4.5.1. I2C AC Characteristics
CLK: 10MHz Operation
Standard-Mode
Fast-Mode
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fSCL
tHD;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tr
SCL clock frequency
Hold time START condition
Low period of SCL clock
HIGH period of SCL clock
Data hold time
0
4.0
4.7
4.0
0
250
--
--
100
--
--
--
3.45
--
0
0.6
1.3
0.6
0
400
--
--
--
0.9
--
kHz
us
us
us
us
ns
ns
ns
Data setup time
100
20+0.1Cb
20+0.1Cb
Rise time of SDA and SCL
Fall time of SDA and SCL
Setup time for STOP
condition
Bus free time between STOP
and START condition
1000
300
300
300
tf
tSU;STO
tBUF
4.0
4.7
--
--
0.6
1.3
--
--
us
us
Cb = capacitance of one bus line in pF.
tf
SDA
tBUF
tr
tr
tSU;DAT
tf
tLOW
SCL
tHD;STA
tSU;STO
tHIGH
tHD;DAT
S
P
S
6
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
4.5.2. SPI AC Characteristics
CLK: 10MHz Operation
100kHz-Mode
400kHz-Mode
Symbol
Parameter
Min.
100
100
--
Max.
Min.
100
100
--
Max.
Unit
tDC
tCDH
tCDD
tCL
Data to SCL setup time
SCL to Data hold time
SCL to Data delay
SCL low time
--
--
--
ns
--
ns
ns
200
5
200
1.25
1.25
400
100
--
--
--
us
tCH
SCL high time
--
5
--
us
tCLK
tR, tF
tCC
SCL clock frequency
SCL rise and fall time
SS_N to SCL setup time
SCL to SS_N hold time
SS_N inactive time
--
100
100
--
--
kHz
ns
--
--
5
1.25
1.25
1.25
us
tCCH
tCWH
5
--
--
us
5
--
--
us
tCC
SS_N
SCL
tCWH
tDC
tCL
tCH
tCDH
tR tF
D1
SDA
D7
D6
D0
tCCH
SS_N
SCL
tCDD
SDOUT
D6
D1
D0
D7
SCL CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL=1
7
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
4.5.3. SPI Mode Selection
FS8806/FS8826 will operate in I2C mode by default. SPI mode will be entered by receiving 3 rising
pulses on SS_N pin after hardware reset. The waveform is shown as below. It will still enter SPI mode
if more than 3 rising pulses on SS_N is detected. It is suggested to connect SS_N to power or ground
when operating in I2C mode. This serial interface operation mode will be reset only by hardware reset
and it will not be changed by software reset.
1
2
3
SS_N
Enter SPI mode on
third rising edge
SPI data transfer starts
8
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
5. Application Circuit
5.1. Only I2C mode
FS8806/FS8826
5.2. I2C and SPI mode
FS8806/FS8826
9
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
6. Package Dimension
SYMBOLS
MIN.
0.053
0.004
—
MAX.
A
A1
A2
D
0.069
0.010
0.059
0.196
0.157
0.244
0.050
0.189
0.150
0.228
0.016
0
E
H
L
θ 0
8
UNIT: INCH
NOTES:
1. JEDEC OUTLINE: MS-012 AA
2. DIMENSIONS “D” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.MOLD
FLASH, PROTRUSIONS AND GATE BURRS SHALL NOT EXCEED .15mm (.006in) PER SIDE.
3. DIMENSIONS “E” DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD
FLASH AND PROTURSIONS SHALL NOT EXCEED .25mm (.010in) PER SIDE.
10
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
7. Product Order Information
FS8806 - ESPL
Package Type
ESPL = 8-pins SOP (Non-RoHS)
ESPR = 8-pins SOP(RoHS)
FameG ASoC Device Name
Part Number
FS8806ESPL
FS8806ESPR
FS8826ESPR
Package Type
8-pin SOP Package (Non-RoHS)
8-pin SOP Package (RoHS)
8-pin SOP Package (RoHS)
11
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
Preliminary Datasheet
8. Revision History
Rev.
Date
Page
10
9
Description of Changes
V1.0 March.2006
V0.2 March.2006
V0.3 March.2006
V1.0 Mar.28.2006
V1.1 Aug.29.2006
Initial Release
Re-compose
9
Revise DC Characteristics
Initial Release to Customers.
Revise DC Characteristics.
10
10
1. Revise CLK descriptions in DC Characteristics
section.
2. Revise page header.
1. Revise for FS8826
2. Add package dimension
V1.2 Dec.29.2006
V1.3 Jan.31.2007
10
12
12
Issue Date: January, 2007 Rev. 1.3
The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from
FameG
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