FS8308 [PTC]
Low Power PLL Frequency Synthesizer IC; 低功耗锁相环频率合成器IC
| 型号： | FS8308 |
| 厂家： | 
PRINCETON TECHNOLOGY CORP |
| 描述： | Low Power PLL Frequency Synthesizer IC |
| 文件： | 总15页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FS8308 Low Power PLL Frequency Synthesizer IC
A d v a n c e I n f o r m a t i o n
Princeton Technology Corp. reserves the right to change the product described in this datasheet. All information con-
tained in this datasheet is subject to change without prior notice. Princeton Technology Corp. assumes no responsibility
for the use of any circuits shown in this datasheet.
Description
The FS8308 is a serial data input, phase-locked loop IC with programmable input and ref-
erence frequency dividers. When combined with a VCO, this IC becomes the core of a
very low power frequency synthesizer well-suited for mobile communication applications,
e.x. paging systems and family radio service (FRS). There are some features implemented
in this IC, including an 18-bit programmable input frequency divider, a terminal for refer-
ence oscillator buffer output, as well as stand-by control through programming, and etc.
Details are listed in the following.
Features
Up to 40 MHz external crystal oscillator reference frequency under normal condition
Low current consumption (IDD,total typically 1.2 mA at fFIN = 500 MHz and VDD1 = 1.0
V)
With Schmitt trigger added for noise-immune programming input
18-bit programmable input frequency divider (including a ÷ 64/65 prescaler) with
divide ratio range from 4032 to 262143
13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with
divide ratio range from 40 to 65528
Optional lock detector output (LD, fR/2, fV/2)
Charge pump output for passive low-pass filter
Wide tuning range of charge pump output for external VCO (VSS+0.5 to VDD2-0.5)
Switchover terminal for constant of loop filter or general open drain output
Reference oscillator buffer output
Programmable stand-by control
TSSOP 16L package (0.65mm pitch)
Applications
Pager
Family radio service (FRS)
Wireless communication system
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April 2003
A d v a n c e I n f o r m a t i o n
FS8308
Package and Pin Assignment: 16L, TSSOP
1
2
3
4
5
6
7
8
16
XIN
XOUT
VDD2
NC
BO
15
14
13
12
11
10
9
TEST
SW
LE
DO
DATA
CLK
LD
VSS
FIN
VDD1
NC
Dimensions in mm
Dimensions in inch
Symbols
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.30
0.20
5.10
---
MIN.
---
NOM.
---
MAX.
0.048
0.006
0.041
0.012
0.008
0.201
---
A
A1
A2
b
0.05
0.80
0.19
0.09
4.90
---
---
0.002
0.031
0.007
0.004
0.193
---
---
1.00
---
0.039
---
C
---
---
D
E
5.00
6.40
4.40
0.65
0.60
---
0.197
0.252
0.173
0.026
0.024
---
E1
e
4.30
---
4.50
---
0.169
---
0.177
---
L
0.45
---
0.75
0.10
0.018
---
0.030
0.004
y
θ
---
---
0
°
8
°
0
°
8
°
Note: Tolerance + 0.1mm unless otherwise specified
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A d v a n c e I n f o r m a t i o n
FS8308
Pin Descriptions
Number
1
Name
XIN
I/O
I
Description
Reference crystal oscillator or external clock input with internally biased amplifier
(any external input to XIN must be ac-coupled)
2
3
4
5
6
XOUT
VDD2
NC
O
Reference crystal oscillator or external clock output
POWER Nominal 3.0 V supply voltage
NC
O
No connection
DO
Single-ended charge pump output for passive low-pass filter
Ground
VSS
GND
VCO frequency input with internally biased input amplifier
(any external input to FIN must be ac-coupled)
7
FIN
I
8
VDD1
NC
POWER Nominal 1.0 V supply voltage
9
NC
O
I
No connection
10
11
12
13
14
15
16
LD
Lock detector output (high when PLL is locked)
Shift register clock input
CLK
DATA
LE
I
Serial data input
I
Latch enable input
SW
O
I
Switchover terminal for constant of loop filter or a general open drain output
Test mode control input with internal pull-down resistor
Terminal of reference crystal oscillator buffer output
TEST
BO
O
Block Diagram
FIN
÷ 64/65
N-COUNTER
N-LATCH
CHARGE
PUMP
DATA
CLK
LE
DO
LD
CONTROL
LOGIC
SHIFT REGISTER
PFD
TEST
LOCK
DETECTOR
S-LATCH
R-LATCH
BO
R-COUNTER
XIN
÷ 8
WINDOW
GENERATOR
XOUT
SW
SW
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A d v a n c e I n f o r m a t i o n
FS8308
Absolute Maximum Ratings
VSS = 0 V
Parameter
Symbol
VDD1
VDD2
VFIN
Rating
Unit
V
VSS – 0.3 to VSS + 2.0
VSS – 0.3 to VSS + 6.0
VSS – 0.3 to VDD + 0.3
Supply voltage
V
Input voltage range
V
oC
oC
oC
s
TPS
Operating temperature range
Storage temperature range
Soldering temperature range
Soldering time range
–30 to 60
–40 to 125
255
TSTG
TSLD
tSLD
10
Recommended Operating Conditions
VSS = 0 V
Value
Parameter
Symbol
Unit
min.
0.95
typ.
1.0
max.
2.0
VDD1
VDD2
TA
V
V
Supply voltage range
Operating temperature
2.4
3.0
25
3.6
60
oC
–30
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A d v a n c e I n f o r m a t i o n
FS8308
Electrical Characteristics
(VDD1 = 0.95 to 2.0 V, VDD2 = 2.4 to 3.6 V, VSS = 0 V, TA = 0 to 60
°
C
unless otherwise noted)
Value
Parameter
Symbol
IDD,total
Condition
Unit
mA
min.
typ.
max.
1.5
VDD1 = 1.0 V
fFIN = 500 MHz
Current consumption
1.2
fXIN =24 MHz
IDD,standby
fFIN
Standby current consumption
FIN operating frequency range
PS=”H”
10
500
40
µA
PFIN = -15dBm
20
MHz
VDD1 = 1.0 V, PS=”L”
fXIN
PFIN
VXIN
VIL
VDD1 = 1.0 V
XIN operating frequency range
FIN input voltage swing
7
MHz
dBm
Vpk-pk
V
-15
0.3
XIN input voltage swing
CLK, DATA, LE logic LOW input voltage
0.3
VDD
0.3
-
VIH
CLK, DATA, LE logic HIGH input voltage
V
IIL,XIN
IIH,XIN
IIL,FIN
IIH,FIN
IDO
VIL = 0 V
VIH = VDD1
XIN logic LOW input current
XIN logic HIGH input current
FIN logic LOW input current
FIN logic HIGH input current
Charge Pump Drive Current
10
10
60
60
µA
µA
µA
µA
mA
mA
mA
mA
VIL = 0 V
VIH = VDD1
VDD2 = 3.0V, VDO = 1.5V
VDD2 = 3.0V, VDO = 1.5V
VOL = 0.4 V
1.0
1.0
IDO
Charge Pump Sink Current
IOL
LD, FV, FR logic LOW output current
LD, FV, FR logic HIGH output current
0.1
0.1
IOH
VOH = VDD2 – 0.4 V
SW = ’L’
VSW = VDD2 = 3.0V
ISW,OFF
SW logic LOW output current
SW logic HIGH output current
10
µA
SW = ’H’
VSW = VDD2 = 3.0V
ISW,ON
tSU1
tSU2
2.8
mA
DATA to CLK setup time
CLK to LE setup time
Hold time
2
2
2
µs
µs
µs
tHOLD
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A d v a n c e I n f o r m a t i o n
FS8308
Functional Description
Programmable Input Frequency Divider
The VCO input to the FIN pin is divided by the programmable divider and then internally
output to the phase/frequency detector (PFD) as fV. The programmable input frequency
divider consists of a ÷ 64/65 (P/P+1) dual-modulus prescaler in prior to a 18-bit (N)
counter, which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B)
counter. The total divide ratio, N, is related to values for P, A, and B through the relation
N = (P+ 1) × A+ P× (B– A) = P× B+ A,
with B≥ A. The minimum available programmable divisor for continuous counting is
given by P× (P– 1) = 64× 63 = 4032, and the valid total divide ratio range for the
input divider is M = 4032 to 262143.
Take N=10000 for example, since P=64 and hence that B=156 and A=16. Therefore, the
binary codes of B and A should be 0000 1001 1100 and 010000, respectively. An alterna-
tive approach is to translate the decimal N into binary code directly. And then just take the
last 6-bit as A and the remaining 12-bit as B. By far the binary code of N=10000 is
00 0010 0111 0001 0000. One can get the same result as the former method.
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable divider and then internally
output to the PFD as fR. The programmable reference frequency divider consists of a fixed
÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to
values for S and R through the relation
T = S× R = 8× R.
The usable divisior range of the reference counter is R = 5 to 8191 and therefore, the
T = 40 to 65528
valid total divide ratio range for the reference divider is
8.)
(in steps of
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A d v a n c e I n f o r m a t i o n
FS8308
Serial Input Data Format
The divsors of the input and reference dividers are input using a 20-bit serial interface
consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format
of the serial data is shown in Fig. 1. The data on the DATA line is written to the shift reg-
ister on the rising edge of the CLK signal and is input with MSB first. The last two bits are
recognized as the latch select control bits. Data on the DATA line should be changed on
the falling edge of CLK, and LE should be held low while data is being written to the shift
register. Data is transferred from the shift register to either one of the frequency divider
latches or the optional control latch when LE is set high. When the latch select control bits
are set high-low or low-low, data is loaded to the 18-bit N-counter latch, and when the
latch select control bits are set high-high, the 2 MSBs are ignored, the next 13 data bits are
loaded to the 13-bit R-counter latch and the remaining 3 LSBs are used to control testing
modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 =
low. To disable LD output (i.e. set LD low), R14 should be set low. When the latch select
control bits are set low-high, the 2 MSBs are recognized as PS and SW, which are used as
stand-by control and open drain output control, respectively. The detail of two control bits
setting is summarized in Table 1. In normal work condition, PS is set to low. When PS is
programmed to high, it will enter stand-by mode.
Serial input data timing waveforms are shown in Fig. 2.
Fig. 1 – Serial input data format
18-bit data for N-counter
13-bit data for R-counter
ignored
optionalcontrol
ignored
Table 1: Control Bit Setting
1st CB
2nd CB
Fetching Target of Serial Data Input
X
0
0
1
1
N-counter
PS and SW
R-counter
1
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A d v a n c e I n f o r m a t i o n
FS8308
Fig. 2 – Serial input data timing waveforms
DATA
CLK
LE
tHOLD
tSU1
tSU2
DATA
CLK
LE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
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A d v a n c e I n f o r m a t i o n
FS8308
Phase/Frequency Detector (PFD)
The PFD compares an internal input frequency divider output signal, fV, with an internal
reference frequency divider output signal, fR, and generates an error signal, DO, which is
proportional to the phase error between fV and fR. The DO output is intended for use with
a passive filter as shown in Fig. 2.
Lock Detector (LD)
When phase comparator detects phase difference, LD terminal outputs “L”. When phase
comparator locks, LD terminal outputs “H”. On standby, outputs “H”. The criteria for lock
condition is that the phase difference between fV and fR is less than 2/xin and continues for
more than three consecutive times.
The input/output waveforms for the PFD and LD are shown in Fig. 3.
Fig. 2 – Passive low-pass filter circuit
DO
to VCO
R1
C1
C2
Fig. 3 – PFD input/output waveforms
2/xin
fR
fV
high-Z
high-Z
high-Z
DO
LD
< 2/xin
< 2/xin
< 2/xin
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A d v a n c e I n f o r m a t i o n
FS8308
Stand-by Mode
The stand-by mode for the PLL is entered by programming the PS bit to high. In the stand-
by mode, the XIN and FIN amplifiers, N-counter, and R-counter are stopped, as well as the
internal current bias for charge pump block, the N- and R-counters are also reset, and the
DO and DB outputs are set to the high impedance state. As long as voltage is supplied to
VDD2, data loaded to the latches is kept. To exit from stand-by mode to normal operation,
the PS bit must be programmed to low.
Reference Crystal Oscillator Buffer Output (BO)
This IC provides a reference crystal oscillator buffer output intended to be used as a crys-
tal local oscillator to a 2nd mixer. The terminal is represented as BO. For cases to enhance
the buffer output swing, increasing VDD1 will be an efficient way.
Filter Switch Control (SW)
Control of SW terminal by “SW” bit. This terminal is for switching time-constant of loop
filter. Output type of this terminal is open drain output. When constant of loop filter
doesn’t change by this switch, general open drain output is available. Note that there is an
internal 200Ω resistor connected between and drain terminal and output pin.
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A d v a n c e I n f o r m a t i o n
FS8308
Application Circuit
1st IF
amplifier
2nd IF
amplifier Discriminator
Wave
shaper
LNA
1st mixer
2nd mixer
LPF
Frequency
multiplier (×4,5)
2nd LO
1st LO
XIN
XOUT
VDD2
NC
BO
RAM
CPU
ROM
TEST
SW
LE
DO
DATA
CLK
LD
Decoder
VSS
FIN
VDD1
NC
LCD driver
LCD
Driver
DC/DC
converter
Page 11
April 2003
A d v a n c e I n f o r m a t i o n
FS8308
Typical Characteristics
FIN Input Sensitivity vs. Input Frequency
0
-4
Vdd2=3.0V
fXIN=24MHz, R=5
-8
-12
-16
-20
-24
-28
-32
-36
-40
Vdd1=1.0V
Vdd1=1.1V
Vdd1=1.2V
0
100 200 300 400 500 600
fFIN (MHz)
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A d v a n c e I n f o r m a t i o n
FS8308
Current Consumption of Idd1 vs. Operating Frequency
Vdd2=3.0V, Pfin=-15dBm
fXIN=24MHz, R=5
2.0
1.6
1.2
0.8
Vdd1=1.0V
Vdd1=1.1V
0.4
Vdd1=1.2V
0.0
0
100 200 300 400 500 600
fFIN (MHz)
Current Consumption of Idd2 vs. Supply Voltage Vdd2
0.40
0.36
0.32
0.28
0.24
0.20
0.16
1.6 2.0 2.4 2.8 3.2 3.6 4.0
Vdd2 (V)
Page 13
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A d v a n c e I n f o r m a t i o n
FS8308
Charge Pump Output Characteristics
Vdd2=3.0V
1.2
0.8
FR > FV
0.4
Drive Current
Sink Current
0.0
-0.4
-0.8
-1.2
FR < FV
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VDO (V)
Charge Pump Output Current vs. Power Supply Voltage
Charge Pump Output Current
1.1
1.0
0.9
1
2
Vdd2
VDO
=
0.8
0.7
0.6
0.5
0.4
Drive Current
Sink Current
1.5 2.0 2.5 3.0 3.5 4.0
Vdd2 (V)
Page 14
April 2003
A d v a n c e I n f o r m a t i o n
FS8308
Single Voltage Operation
This IC requires two separate power supplies to operate. If only one voltage source is
available, ex. use battery to serve as power source, the user can apply the configuration as
shown in the following which is referred to as single voltage operation.
POWER SUPPLY
VDD2
R
VDD1
Since there is only one voltage source provided in the so-called single voltage configura-
tion, which is directly connected to Vdd2, one needs to choose a reasonable R value to set
Vdd1 to operate within the safe region, whose requirement is Vdd1 > 0.95V. Keep in mind
that the lower Vdd1 is, the less current this IC will consume, but the poorer crystal buffer
output it drives. In order to balance the trade-off between the current consumption and
crystal buffer driving capability, Vdd1 is suggested to be about 1.1V. Vdd1 vs. Vdd2 for vari-
ous R at fin=470MHz is plotted in the following figure. Note that although smaller resistor
R makes this IC consume more current, the reward is with wider power supply input
range. Typical value of R is recommended to be around 1.6KΩ..
Single Voltage Characteristic: Vdd1 vs. Vdd2 for Various R
R=1.2K
R=1.6K
1.5
R=1.8K
R=2.0K
1.4
1.3
1.2
1.1
Safe Operation Region
1.0
0.9
fin=470MHz, Pfin=-10dBm
xin=24MHz, N=4032, R=5
0.8
1.5
2.0
2.5
3.0
3.5
4.0
Vdd2 (V)
Page 15
April 2003
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