NVMFWS040N10MCLT1G [ONSEMI]
Single N-Channel Power MOSFET 100V, 28A, 26mΩ;
| 型号： | NVMFWS040N10MCLT1G |
| 厂家： | 
ONSEMI |
| 描述： | Single N-Channel Power MOSFET 100V, 28A, 26mΩ |
| 文件： | 总8页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Power, Single
N-Channel
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
38 mW @ 10 V
53 mW @ 4.5 V
100 V
21 A
100 V, 38 mW, 21 A
D (5,6)
NVMFS040N10MCL
Features
• Small Footprint (5x6 mm) for Compact Design
G (4)
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
S (1,2,3)
• AEC−Q101 Qualified and PPAP Capable
N−CHANNEL MOSFET
• NVMFWS040N10MCL − Wettable Flanks Product
• These Devices are Pb−Free, Halogen Free/BFR Free, Beryllium Free
and are RoHS Compliant
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
1
Parameter
Drain−to−Source Voltage
Symbol
Value
100
20
Unit
V
DFN5
(SO−8FL)
CASE 488AA
DFN5
(SO8FL WF)
CASE 507BA
V
DSS
Gate−to−Source Voltage
V
GS
V
Continuous Drain
T
= 25°C
= 100°C
= 25°C
I
21
A
C
D
Current R
(Note 1)
q
JC
T
C
15
MARKING DIAGRAM
Steady
State
Power Dissipation
(Note 1)
T
C
P
36
W
A
D
D
R
q
JC
T
C
= 100°C
18
S
S
S
G
D
D
XXXXXX
AYWZZ
Continuous Drain
Current R
T = 25°C
A
I
D
6.5
4.6
3.5
1.7
94
q
JA
T = 100°C
A
(Notes 1, 2)
Steady
State
D
Power Dissipation
T = 25°C
A
P
W
D
R
(Notes 1, 2)
q
JA
A
Y
= Assembly Location
= Year
T = 100°C
A
Pulsed Drain Current
T = 25°C, t = 10 ms
I
DM
A
W
ZZ
= Work Week
= Lot Traceability
A
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
Source Current (Body Diode)
I
S
28
A
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
Single Pulse Drain−to−Source Avalanche
E
AS
109
mJ
Energy (I
= 0.9 A)
L(pk)
Lead Temperature Soldering Reflow for Solder-
ing Purposes (1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Value
4.2
Unit
Junction−to−Case − Steady State (Note 1)
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
R
43
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using 1 in pad size, 2 oz. Cu pad.
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
February, 2022 − Rev. 2
NVMFS040N10MCL/D
NVMFS040N10MCL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
100
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/
70
mV/°C
(BR)DSS
I
D
= 250 mA, ref to 25°C
T
J
Zero Gate Voltage Drain Current
I
T = 25°C
1
mA
DSS
J
V
DS
= 0 V,
GS
V
= 100 V
T = 125°C
J
100
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
Gate Threshold Voltage
V
V
GS
= V , I = 26 mA
1
3
V
GS(TH)
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
I
D
= 250 mA, ref to 25°C
−5.9
31
mV/°C
mW
GS(TH)
J
R
V
GS
= 10 V, I = 5 A
38
53
DS(on)
D
V
GS
= 4.5 V, I = 4 A
42
D
Forward Transconductance
CHARGES & CAPACITANCES
Input Capacitance
g
V
= 10 V, I = 5 A
18
S
FS
DS
D
C
500
200
3.7
4.0
8.3
0.8
1.6
1.2
2.9
pF
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0 V, f = 1 MHz, V = 50 V
DS
GS
Reverse Transfer Capacitance
Total Gate Charge
Q
V
= 4.5 V, V = 50 V, I = 4 A
nC
G(TOT)
Q
G(TOT)
GS
DS
D
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
G(TH)
Q
V
= 10 V, V = 50 V, I = 5 A
DS D
GS
GD
GP
GS
Q
V
V
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
t
7.2
9.3
ns
d(ON)
Rise Time
t
r
V
= 10 V, V = 50 V,
DS
GS
D
I
= 5 A, R = 6 W
G
Turn−Off Delay Time
t
15.9
3.1
d(OFF)
Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T = 25°C
0.85
0.73
23
1.3
V
SD
J
V
= 0 V,
GS
S
I
= 5 A
T = 125°C
J
Reverse Recovery Time
Reverse Recovery Charge
Charge Time
t
ns
nC
ns
ns
RR
Q
11
RR
V
= 0 V, dI /dt = 100 A/ms,
S
GS
I
S
= 2 A
t
11.2
11.4
a
Discharge Time
t
b
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Switching characteristics are independent of operating junction temperatures
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2
NVMFS040N10MCL
TYPICAL CHARACTERISTICS
20
20
18
16
14
12
10
8
V
DS
= 10 V
V
V
= 3.0 V
= 2.8 V
GS
18
16
14
12
10
8
*
GS
T = −55°C
J
V
GS
= 2.6 V
= 2.4 V
T = 25°C
J
V
GS
6
6
T = 150°C
J
4
4
2
2
0
*V = 3.2 V to 10 V
GS
0
0
1
2
3
4
5
0
1
2
3
4
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
100
90
80
70
60
50
40
30
20
10
50
T = 25°C
T = 25°C
D
J
J
I
= 5 A
45
40
35
30
25
20
V
= 4.5 V
= 10 V
GS
V
GS
1
2
3
4
5
6
7
8
9
10
1
1.5
2
2.5
3
3.5
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.5
2
1000K
100K
10K
1K
V
I
= 10 V
= 5 A
GS
D
T = 175°C
J
T = 150°C
J
T = 125°C
J
1.5
1
T = 85°C
J
100
10
T = 25°C
J
0.5
−50 −25
1
10
20
30
40
50
60
70
80
90 100
0
25
50
75
100 125 150 175
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFS040N10MCL
TYPICAL CHARACTERISTICS
10000
1000
100
10
10
V
= 50 V
= 5 A
9
8
7
6
5
4
3
2
1
0
DS
I
D
T = 25°C
J
C
ISS
C
OSS
Q
Q
GS
GD
V
= 0 V
GS
C
RSS
T = 25°C
J
f = 1 MHz
1
0
20
40
60
80
100
0
1
2
3
4
5
6
7
8
9
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
100
10
1
V
= 0 V
GS
V
V
= 10 V
= 50 V
= 5 A
GS
DS
T = 175°C
J
t
r
I
D
t
t
t
d(off)
f
T = 150°C
J
10
d(on)
T = 125°C
J
T = 25°C
J
T = −55°C
J
1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1
10
R , GATE RESISTANCE (W)
100
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
100
10
1
V
≤ 10 V
= 25°C
GS
T
C
Single Pulse
T
= 25°C
J(initial)
10 ms
1
T = 125°C
J(initial)
R
Limit
DS(on)
0.5 ms
1 ms
10 ms
Thermal Limit
Package Limit
0.1
0.1
0.1
1
10
100
1000
0.0001
0.001
TIME IN AVALANCHE (s)
0.01
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
NVMFS040N10MCL
TYPICAL CHARACTERISTICS
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (s)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Package
Shipping
NVMFS040N10MCLT1G
DFN5
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVMFWS040N10MCLT1G
Wettable Flank DFN5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
SCALE 2:1
2 X
DATE 25 JUN 2018
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
GENERIC
SIDE VIEW
MARKING DIAGRAM*
DETAIL A
1
8X b
A B
XXXXXX
AYWZZ
0.10
0.05
C
c
e/2
e
L
1
4
XXXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
K
RECOMMENDED
SOLDERING FOOTPRINT*
W
ZZ
= Work Week
= Lot Traceability
E2
2X
PIN 5
M
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
(EXPOSED PAD)
L1
0.495
4.560
2X
1.530
D2
G
2X
BOTTOM VIEW
0.475
3.200
1.330
4.530
STYLE 1:
STYLE 2:
PIN 1. ANODE
2. ANODE
2X
0.905
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
1
3. ANODE
4. NO CONNECT
5. CATHODE
0.965
5. DRAIN
4X
1.000
1.270
PITCH
DIMENSIONS: MILLIMETERS
4X
0.750
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW5 5x6 (FULL−CUT SO8FL WF)
CASE 507BA
ISSUE A
DATE 03 FEB 2021
q
q
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
A
Y
= Assembly Location
= Year
W
ZZ
= Work Week
= Lot Traceability
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON26450H
DFNW5 5x6 (FULL−CUT SO8FL WF)
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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