NTHS5404T1G [ONSEMI]
Power MOSFET; 功率MOSFET
| 型号： | NTHS5404T1G |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET |
| 文件： | 总6页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTHS5404
Power MOSFET
20 V, 7.2 A, N−Channel ChipFETE
Features
• Low R
for Higher Efficiency
DS(on)
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• Logic Level Gate Drive
• Miniature ChipFET Surface Mount Package Saves Board Space
• Pb−Free Package is Available
V
R
TYP
I MAX
D
(BR)DSS
DS(on)
20 V
25 mW @ 4.5 V
7.2 A
Applications
• Power Management in Portable and Battery−Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
D
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Steady
State
G
Rating
Symbol 5 Secs
Unit
V
Drain−Source Voltage
Gate−Source Voltage
Continuous Drain Current
V
V
20
DS
GS
S
"12
V
N−Channel MOSFET
I
A
D
(T = 150°C) (Note 1)
J
7.2
5.2
5.2
3.8
T = 25°C
A
ChipFET
CASE 1206A
STYLE 1
T = 85°C
A
Pulsed Drain Current
I
"20
A
A
DM
Continuous Source Current
(Diode Conduction) (Note 1)
I
S
7.2
5.2
PIN
MARKING
DIAGRAM
CONNECTIONS
Maximum Power Dissipation
(Note 1)
P
W
D
2.5
1.3
1.3
0.7
T = 25°C
A
8
1
2
3
4
1
8
7
6
5
D
D
D
G
D
D
D
S
T = 85°C
A
2
3
4
7
6
5
Operating Junction and Storage
Temperature Range
T , T
J
−55 to +150
°C
stg
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
A2 = Specific Device Code
M = Month Code
1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
ORDERING INFORMATION
†
Device
Package
Shipping
NTHS5404T1
NTHS5404T1G
ChipFET
3000/Tape & Reel
3000/Tape & Reel
ChipFET
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
October, 2004 − Rev. 3
NTHS5404T1/D
NTHS5404
THERMAL CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Maximum Junction−to−Ambient (Note 2)
t v 5 sec
Steady State
R
°C/W
q
JA
40
80
50
95
Maximum Junction−to−Foot (Drain)
Steady State
R
15
20
°C/W
q
JF
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
Static
Gate Threshold Voltage
Gate−Body Leakage
V
V
= V , I = 250 mA
0.6
−
−
−
−
−
−
"100
1.0
V
GS(th)
DS
GS
D
I
V
DS
= 0 V, V = "12 V
nA
mA
GSS
GS
Zero Gate Voltage Drain Current
I
V
= 16 V, V = 0 V
−
DSS
DS
GS
V
= 16 V, V = 0 V,
−
5.0
DS
GS
T = 85°C
J
On−State Drain Current (Note 3)
I
V
w 5.0 V, V = 4.5 V
20
−
−
−
0.030
0.045
−
A
D(on)
DS
GS
Drain−Source On−State Resistance (Note 3)
r
V
V
= 4.5 V, I = 5.2 A
0.025
0.038
20
W
DS(on)
GS
GS
D
= 2.5 V, I = 4.3 A
−
D
Forward Transconductance (Note 3)
Diode Forward Voltage (Note 3)
g
fs
V
= 10 V, I = 5.2 A
−
S
V
DS
D
V
I
S
= 5.2 A, V = 0 V
−
0.8
1.2
SD
GS
Dynamic (Note 4)
Total Gate Charge
Q
−
−
−
−
−
−
−
−
12
2.4
3.2
20
40
40
15
30
18
−
nC
ns
G
V
= 10 V, V = 4.5 V,
GS
DS
Gate−Source Charge
Gate−Drain Charge
Turn−On Delay Time
Rise Time
Q
GS
Q
GD
I
D
= 5.2 A
−
t
30
60
60
23
60
d(on)
V
D
= 10 V, R = 10 W
L
t
r
DD
I
^ 1.0 A, V
= 4.5 V,
GEN
Turn−Off Delay Time
Fall Time
t
d(off)
R
= 6 W
G
t
f
Source−Drain Reverse Recovery Time
t
rr
I = 1.1 A, di/dt = 100 A/ms
F
2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Guaranteed by design, not subject to production testing.
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2
NTHS5404
TYPICAL ELECTRICAL CHARACTERISTICS
12
10
12
10
1.8 V
5 V
2 V
T = 25°C
J
V
GS
= 2 V − 5 V
8
6
4
8
1.6 V
6
4
125°C
1.4 V
25°C
2
0
2
0
V
GS
= 1.2 V
T
C
= −55°C
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.040
0.06
T = 25°C
J
0.038
0.036
0.034
0.032
0.030
0.028
I
= 5.2 A
D
0.05
0.04
0.03
0.02
T = 25°C
J
V
V
= 2.5 V
= 4.5 V
GS
GS
0.01
0
V
GS
= 6 V
0.026
0.024
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I
D,
DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
Figure 3. On−Resistance versus
Gate−to−Source Voltage
1.6
1.4
1.2
1
1E−05
1E−06
1E−07
1E−08
I
V
= 5.2 A
D
V
GS
= 0 V
= 4.5 V
GS
T = 150°C
J
T = 100°C
J
0.8
0.6
−50 −25
0
25
50
75
100
125 150
0
4
8
12
16
20
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTHS5404
TYPICAL ELECTRICAL CHARACTERISTICS
5
11
10
9
Q
V
DS
= 0 V
V
GS
= 0 V
G
C
iss
1800
1500
1200
900
T = 25°C
J
4
3
2
1
0
8
7
C
rss
6
5
Q
4
Q
1
GS
GD
4
I
= 5.2 A
600
D
3
T = 25°C
Q
J
C
2
oss
/Q = 1.33
GD GS
300
0
1
0
12
8
4
0
4
8
12
16
20
0
2
3
5
6
7
8
9
10 11 12
V
GS
V
DS
Q , TOTAL GATE CHARGE (nC)
G
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 7. Capacitance Variation
100
5
t
d(off)
4
3
2
V
= 0 V
GS
t
f
T = 25°C
J
t
d(on)
10
t
r
V
= 10 V
= +1.0 A
= 4.5 V
DD
1
0
I
D
V
GS
1
0
0.2
0.4
0.6
0.8
1
10
R , GATE RESISTANCE (OHMS)
100
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
1
Duty Cycle = 0.5
0.2
0.1
PER UNIT BASE = R
= 80°C/W
P
DM
q
JA
0.1
T
JM
− T = P
Z
(t)
q
A
DM JA
SURFACE MOUNTED
0.05
0.02
t
1
t
2
DUTY CYCLE, D = t /t
1 2
Single Pulse
0.001
0.01
0.0001
0.01
0.1
1
10
100
1000
SQUARE WAVE PULSE DURATION (sec)
Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient
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4
NTHS5404
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.025
1.727
0.068
0.457
0.018
0.178
0.007
0.711
0.028
0.711
0.028
0.66
0.66
0.026
0.026
Figure 12. Basic
Figure 13. Style 1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 1, 2, 3, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0054 sq. in. (or 3.51 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead−frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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5
NTHS5404
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
A
M
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
K
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
S
B
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
L
D
J
MILLIMETERS
INCHES
G
DIM MIN
MAX
3.10
1.70
1.10
0.35
MIN
MAX
0.122
0.067
0.043
0.014
A
B
C
D
G
J
2.95
1.55
1.00
0.25
0.116
0.061
0.039
0.010
0.65 BSC
0.025 BSC
0.10
0.28
0.20
0.42
0.004 0.008
0.011 0.017
0.022 BSC
C
K
L
0.55 BSC
5 ° NOM
1.80 2.00
M
S
5 ° NOM
0.05 (0.002)
0.072
0.080
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHS5404T1/D
相关型号：
NTHS5443T1G
3600mA, 20V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, LEAD FREE, CASE 1206A-03, CHIPFET-8
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