NTHS5443T1/D [ETC]
Power MOSFET P-Channel ChipFET? ; 功率MOSFET P通道ChipFET ？\n
| 型号： | NTHS5443T1/D |
| 厂家： | 
ETC |
| 描述： | Power MOSFET P-Channel ChipFET?
|
| 文件： | 总8页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTHS5443T1
Power MOSFET
P-Channel ChipFETE
3.6 Amps, 20 Volts
Features
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• Low R
for Higher Efficiency
DS(on)
• Logic Level Gate Drive
• Miniature ChipFET Surface Mount Package Saves Board Space
3.6 AMPS
20 VOLTS
Applications
• Power Management in Portable and Battery–Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
RDS(on) = 65 mW
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
G
Steady
State
Rating
Symbol
5 secs
Unit
V
Drain–Source Voltage
Gate–Source Voltage
Continuous Drain Current
(T = 150°C) (Note 1.)
T = 25°C
V
DS
V
GS
–20
"12
"15
V
D
I
D
A
P–Channel MOSFET
J
"4.9
"3.5
"3.6
"2.6
A
T = 85°C
A
Pulsed Drain Current
I
A
A
DM
Continuous Source Current
(Note 1.)
I
AS
–2.1
–1.1
Maximum Power Dissipation
(Note 1.)
P
D
W
ChipFET
CASE 1206A
STYLE 1
T = 25°C
2.5
1.3
1.3
0.7
A
T = 85°C
A
Operating Junction and Storage
Temperature Range
T , T
–55 to +150
°C
J
stg
MARKING
DIAGRAM
1. Surface Mounted on 1″ x 1″ FR4 Board.
PIN CONNECTIONS
8
7
6
5
1
2
3
4
D
D
D
G
D
D
D
S
1
2
3
4
8
7
6
5
A4 = Specific Device Code
ORDERING INFORMATION
Device
Package
Shipping
3000/Tape & Reel
NTHS5443T1
ChipFET
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
May, 2001 – Rev. 2
NTHS5443T1/D
NTHS5443T1
THERMAL CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Maximum Junction–to–Ambient (Note 2.)
R
°C/W
thJA
t v 5 sec
Steady State
40
80
50
95
Maximum Junction–to–Foot (Drain)
Steady State
R
15
20
°C/W
thJF
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
Static
Gate Threshold Voltage
V
V
= V , I = –250 µA
–0.6
–
–
–
–
–
V
GS(th)
DS
GS
D
Gate–Body Leakage
I
V
= 0 V, V = "12 V
–
–
–
"100
–1.0
–5.0
nA
µA
GSS
DS
GS
Zero Gate Voltage Drain Current
I
V
= –16 V, V = 0 V
GS
DSS
DS
DS
V
= –16 V, V = 0 V,
GS
T = 85°C
J
On–State Drain Current (Note 3.)
I
V
DS
v –5.0 V, V = –4.5 V
–15
–
–
A
D(on)
GS
Drain–Source On–State Resistance (Note 3.)
r
V
GS
V
GS
= –4.5 V, I = –3.6 A
–
–
0.056
0.065
0.065
0.074
Ω
DS(on)
D
= –3.6 V, I = –3.3 A
D
V
= –2.5 V, I = –2.7 A
–
–
–
0.095
10
0.110
–
GS
D
Forward Transconductance (Note 3.)
Diode Forward Voltage (Note 3.)
g
V
= –10 V, I = –3.6 A
S
V
fs
DS
D
V
SD
I
= –1.1 A, V = 0 V
–0.8
–1.2
S
GS
Dynamic (Note 4.)
Total Gate Charge
Q
–
–
–
–
–
–
–
–
9.0
2.2
2.2
15
30
50
35
30
14
–
nC
g
V
= –10 V, V = –4.5 V,
GS
DS
Gate–Source Charge
Gate–Drain Charge
Turn–On Delay Time
Rise Time
Q
gs
Q
gd
I
D
= –3.6 A
–
t
25
45
75
50
60
ms
d(on)
V
= –10 V, R = 10 Ω
L
DD
t
r
I
D
^ –1.0 A, V
= –4.5 V,
GEN
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 6 Ω
G
t
f
Source–Drain Reverse Recovery Time
t
rr
I = –1.1 A, di/dt = 100 A/µs
F
ns
2. Surface Mounted on 1″ x 1″ FR4 Board.
3. Pulse Test: Pulse Width v 300 µs, Duty Cycle v 2%.
4. Guaranteed by design, not subject to production testing.
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2
NTHS5443T1
TYPICAL ELECTRICAL CHARACTERISTICS
10
8
10
–6 V
–5 V
–4 V
–2.4 V
–2.2 V
V
DS
≥ –10 V
8
6
4
T = 25°C
–3.4 V
–2.8 V
–2.6 V
J
–2 V
6
–1.8 V
–1.6 V
4
125°C
2
0
2
0
25°C
V
GS
= –1.4 V
T = –55°C
J
0
0.5
1
1.5
2
2.5
3
0.5
1
1.5
2
2.5
3
–V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
–V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.08
0.06
0.2
0.15
0.1
T = 25°C
J
I
= –3.6 A
D
T = 25°C
J
V
GS
= –4.5 V
V
GS
= –6 V
0.04
0.02
0.05
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
–V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
–I DRAIN CURRENT (AMPS)
D,
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
Figure 3. On–Resistance versus
Gate–to–Source Voltage
1.6
1.4
1.2
1
10,000
1000
100
I
V
= –3.6 A
V
GS
= 0 V
D
= –4.5 V
GS
T = 150°C
J
T = 100°C
J
0.8
0.6
10
–50 –25
0
25
50
75
100
125 150
0
4
8
12
16
20
T , JUNCTION TEMPERATURE (°C)
J
–V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
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3
NTHS5443T1
TYPICAL ELECTRICAL CHARACTERISTICS
1800
1500
1200
900
6
24
20
16
12
8
V
DS
= 0 V
V
GS
= 0 V
T = 25°C
J
QT
C
iss
5
4
3
2
V
DS
V
GS
C
rss
Q1
Q2
600
C
oss
I
= –3.6 A
D
300
0
1
0
4
0
T = 25°C
J
10
5
0
5
10
15
20
0
2
4
6
8
10
–V
GS
–V
DS
Q , TOTAL GATE CHARGE (nC)
g
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
Figure 7. Capacitance Variation
1000
V
DD
= –10 V
I
D
= –1.0 V
V
GS
= –4.5 V
100
t
d(off)
t
t
f
r
10
1
t
d(on)
1
10
R , GATE RESISTANCE (OHMS)
100
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
1
Duty Cycle = 0.5
0.2
0.1
P
DM
0.1
0.05
0.02
PER UNIT BASE = R = 80°C/W
θ
JA
T
- T = P Z
θ
DM JA
(t)
JM
A
t
1
SURFACE MOUNTED
t
2
DUTY CYCLE, D = t /t
1 2
Single Pulse
0.001
0.01
0.0001
0.01
0.1
1
10
100
1000
SQUARE WAVE PULSE DURATION (sec)
Figure 10. Normalized Thermal Transient Impedance, Junction–to–Ambient
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4
NTHS5443T1
20
15
10
V
= 0 V
GS
T = 25°C
J
5
0
0.4
0.5
0.6
0.7
0.8
0.9
–V , SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 11. Diode Forward Voltage versus
Current
80 mm
80 mm
18 mm
25 mm
68 mm
28 mm
28 mm
26 mm
26 mm
Figure 12.
Figure 13.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 1, 2, 3, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0054 sq. in. (or 3.51 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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5
NTHS5443T1
PACKAGE DIMENSIONS
ChipFET
CASE 1206A–03
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
A
M
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
K
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
S
B
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A-01 AND 1206A-02 OBSOLETE. NEW
STANDARD IS 1206A-03.
L
D
J
MILLIMETERS
INCHES
G
DIM MIN
MAX
MIN
0.116
MAX
0.122
0.067
0.043
0.014
A
B
C
D
G
J
2.95
1.55
1.00
0.25
3.10
1.70 0.061
1.10 0.039
0.35 0.010
0.65 BSC
0.025 BSC
0.10
0.28
0.20 0.004
0.42 0.011
0.008
0.017
0.022 BSC
C
K
L
0.55 BSC
5 ° NOM
1.80 2.00
M
S
5 ° NOM
0.05 (0.002)
0.072
0.080
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
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6
NTHS5443T1
Notes
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7
NTHS5443T1
ChipFET is a trademark of Vishay Siliconix
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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CENTRAL/SOUTH AMERICA:
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For additional information, please contact your local
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NTHS5443T1/D
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