MC100EP210SMNG [ONSEMI]
2.5V 1:5 Dual Differential LVDS Compatible Clock Driver; 2.5V 1 ： 5双差分LVDS兼容的时钟驱动器
| 型号： | MC100EP210SMNG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver |
| 文件： | 总7页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EP210S
2.5Vꢀ1:5 Dual Differential
LVDS Compatible Clock
Driver
Description
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MARKING
The MC100EP210S is a low skew 1−to−5 dual differential driver,
designed with LVDS clock distribution in mind. The LVDS or
LVPECL input signals are differential and the signal is fanned out to
five identical differential LVDS outputs.
DIAGRAM*
The EP210S specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
Two internal 50 W resistors are provided across the inputs. For
LVDS inputs, VTA and VTB pins should be unconnected. For
MC100
EP210S
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
LVPECL inputs, VTA and VTB pins should be connected to the V
TT
(V − 2.0 V) supply.
CC
Designers can take advantage of the EP210S performance to
distribute low skew LVDS clocks across the backplane or the board.
1
Features
MCxxx
EP210S
ALYWG
• 20 ps Typical Output−to−Output Skew
• 85 ps Typical Device−to−Device Skew
• 550 ps Typical Propagation Delay
32
1
QFN32
MN SUFFIX
CASE 488AM
• The 100 Series Contains Temperature Compensation
• Maximum Frequency > 1 GHz Typical
• Operating Range: V = 2.375 V to 2.625 V with V = 0 V
xxx
A
= 10 or 100
CC
EE
= Assembly Location
• Internal 50 W Input Termination Resistors
• LVDS Input/Output Compatible
• Pb−Free Packages are Available*
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 8
MC100EP210S/D
MC100EP210S
Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1
V
CC
Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 V
CC
32
31 30
29 28
27 26
25
24 23 22 21 20 19 18 17
1
2
3
4
5
6
7
8
V
24
23
22
21
20
19
Qa3
Qa3
Qa4
Qa4
Qb0
EE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
V
CC
CC
VTA
CLKa
CLKa
VTB
Qa2
Qa2
Qa1
Qa1
Qa0
Qa0
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
MC100EP210S
MC100EP210S
Qb0
Qb1
Qb1
CLKb
CLKb
18
17
V
CC
V
CC
V
EE
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
V
CC
Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 V
CC
V
EE
VTA
VTB
V
EE
Figure 1. 32−Lead QFN Pinout (Top View)
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLKn, CLKn
Qn0:4, Qn0:4
VTA
LVDS, LVPECL CLK Inputs*
LVDS Outputs
50 W Termination Resistors
50 W Termination Resistors
Positive Supply
VTB
V
CC
EE
V
Ground
EP for QFN−32,
only
The Exposed Pad (EP) on the QFN−32 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to V
.
EE
*Under open or floating conditions with input pins converging to a common termination
bias voltage the device is susceptible to auto oscillation.
VTA
VTB
Qa0
Qa0
Qb0
Qb0
50 W
50 W
50 W
50 W
Qa1
Qa1
Qb1
Qb1
CLKa
CLKa
CLKb
CLKb
Qa2
Qa2
Qb2
Qb2
Qa3
Qa3
Qb3
Qb3
Qa4
Qa4
Qb4
Qb4
Figure 2. Logic Diagram
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2
MC100EP210S
Table 2. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP−32
Pb Pkg
Level 2
Pb−Free Pkg
Level 2
Level 1
QFN−32
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
461 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
Power Supply
V
V
V
6
−6
6
EE
CC
EE
Power Supply (GND)
LVDS, LVPECL Input Voltage
Output Current
= 2.5 V
= 0 V
V
V ≤ V
V
I
CC
I
Continuous
Surge
50
mA
mA
out
100
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
2S2P
32 LQFP
12 to 17
°C/W
JC
JA
QFN−32
QFN−32
31
27
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
Wave Solder
QFN−32
12
°C/W
°C
JC
T
sol
Pb
Pb−Free
265
265
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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3
MC100EP210S
Table 4. DC CHARACTERISTICS V = 2.5 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Typ
150
Max
200
Min
Max
200
Min
Max
200
Unit
mA
mV
mV
V
I
EE
150
150
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
1250
800
1.2
1400
950
1550
1100
2.5
1250
800
1.2
1400
950
1550
1100
2.5
1250
800
1.2
1400
950
1550
1100
2.5
OH
OL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
IHCMR
R
Internal Termination Resistor
Input HIGH Current
43
57
43
50
57
43
57
W
T
IH
IL
I
I
150
150
150
mA
mA
Input LOW Current
CLK −150
CLK −150
150
150
−150
−150
150
150
−150
−150
150
150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
.
CC
3. All loading with 100 W across LVDS differential outputs.
4. V min varies 1:1 with V , V max varies 1:1 with V . The V range is referenced to the most positive side of the differential
IHCMR
IHCMR
EE IHCMR
CC
input signal.
Table 5. AC CHARACTERISTICS V = 2.375 to 2.625 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
> 1
85°C
Typ
> 1
Symbol
Characteristic
Min
Typ
Max
Min
Max
Min
Max
Unit
f
Maximum Frequency
(See Figure 2. F /JITTER)
> 1
GHz
maxLVDS/
LVPECL
max
t
t
Propagation Delay
425
525
625
450
550
650
475
575
675
ps
ps
PLH
PHL
t
Within−Device Skew (Note 6)
Device−to−Device Skew (Note 7)
Duty Cycle Skew (Note 8)
20
85
80
25
160
100
20
85
80
25
160
100
20
85
80
35
160
100
skew
t
RMS Random Clock Jitter
Minimum Input Swing
0.2
800
130
< 1
0.2
800
150
< 1
0.2
800
160
< 1
1200
230
ps
mV
ps
JITTER
V
150
50
1200 150
200 75
1200 150
225 80
PP
t /t
r
Output Rise/Fall Time (20%−80%)
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured with 400 mV source, 50% duty cycle clock source. All loading with 100 W across differential outputs.
6. Skew is measured between outputs under identical transitions of similar paths through a device.
7. Device−to−Device skew for identical transitions at identical V levels.
CC
8. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
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4
MC100EP210S
450
400
350
300
250
200
150
100
50
Simulated
0
0
200
400
600
800
1000
1200
1400
FREQUENCY (MHz)
Figure 2. Fmax
Q
Q
D
Receiver
Device
Driver
Device
100
W
D
Figure 3. Typical Termination for Output Driver and Device Evaluation
ORDERING INFORMATION
†
Device
MC100EP210SFA
Package
Shipping
LQFP−32
250 Units / Tray
250 Units / Tray
MC100EP210SFAG
LQFP−32
(Pb−Free)
MC100EP210SFAR2
MC100EP210SFAR2G
LQFP−32
2000 / Tape & Reel
2000 / Tape & Reel
LQFP−32
(Pb−Free)
MC100EP210SMNG
72 Units / Tray
QFN−32
(Pb−Free)
MC100EP210SMNR4G
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MC100EP210S
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE B
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
1
AE
AE
−U−
V1
−T−
P
B
V
B1
DETAIL Y
−Z−
BASE
METAL
DETAIL Y
17
8
N
9
4X
0.20 (0.008) AC T−U
Z
9
F
D
S1
S
_
8X M
J
R
DETAIL AD
G
SECTION AE−AE
−AB−
−AC−
E
C
SEATING
PLANE
0.10 (0.004) AC
W
_
Q
H
K
X
DETAIL AD
NOTES:
MILLIMETERS
DIM MIN MAX
7.000 BSC
3.500 BSC
INCHES
MIN MAX
0.276 BSC
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
A
A1
B
0.138 BSC
0.276 BSC
0.138 BSC
MILLIMETER.
7.000 BSC
3.500 BSC
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.012
0.053
0.012
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5 _
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
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6
MC100EP210S
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
A
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
D
PIN ONE
LOCATION
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
0.15
C
TOP VIEW
A3
b
D
0.200 REF
0.180 0.250 0.300
5.00 BSC
2 X
0.15
C
C
D2 2.950 3.100 3.250
5.00 BSC
E2 2.950 3.100 3.250
E
(A3)
0.10
0.08
e
K
L
0.500 BSC
0.200 −−−
0.300 0.400 0.500
A
−−−
SEATING
PLANE
32 X
C
A1
SIDE VIEW
D2
C
L
32 X
EXPOSED PAD
K
32 X
9
16
17
SOLDERING FOOTPRINT*
8
5.30
E2
3.20
1
24
32 X
25
0.63
32
32 X
b
e
0.10
0.05
C
C
A
B
3.20 5.30
BOTTOM VIEW
32 X
28 X
0.28
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC100EP210S/D
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