MC100EP221TBR2 [MOTOROLA]
100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, EXPOSED PAD, PLASTIC, LQFP-52;
| 型号： | MC100EP221TBR2 |
| 厂家： | 
MOTOROLA |
| 描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, EXPOSED PAD, PLASTIC, LQFP-52 驱动 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC100EP221/D
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See Upgrade Product – MC100ES6221
The MC100EP221 is a low skew 1–to–20 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The input signals can be either differential or single–ended if
the VBB output is used. The selected signal is fanned out to 20 identical
differential outputs.
LOW–VOLTAGE
1:20 DIFFERENTIAL
• 270ps max. Part–to–Part Skew
• 50ps max. Output–to–Output Skew
• Differential Design
ECL/PECL CLOCK DRIVER
• VBB Output
• Voltage and Temperature Compensated Outputs
• Supports 3.3V and 2.5V, ECL and PECL Operation
• Supports HSTL and PECL Clock Systems
The EP221 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate–
to–gate skew within a device, and empirical modeling is used to deter-
mine process control limits that ensure consistent tpd distributions from lot
to lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50Ω, even if only
one side is being used. In most applications, all ten differential pairs will
be used and therefore terminated. In the case where fewer than ten pairs
are used, it is necessary to terminate at least the output pairs on the same
package side as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of prop-
agation delay (on the order of 10–20ps) of the output(s) being used
which, while not being catastrophic to most designs, will mean a loss of
skew margin.
TB SUFFIX
52–LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336
6
The MC100EP221, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the EP221 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the
EP221’s performance to distribute low skew clocks across the backplane. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies.
Rev 1
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
639
MC100EP221
Pinout: 52–Lead LQFP
(Top View)
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FUNCTION
CLK_SEL
Active Input
6
0
1
CLK0, CLK0
CLK1, CLK1
LOGIC SYMBOL
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640
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
MC100EP221
Table 1: PIN CONFIGURATION
Pin
I/O
Type
Function
CLK0, CLK0
Input
ECL/LVPECL
Differential reference clock signal input
CLK1, CLK1
CLK_SEL
Input
Input
ECL/LVPECL or HSTL
LVPECL
Alternative differential reference clock signal input
Output frequency divider select
Q[0-19], Q[0-19]
Output
Supply
Supply
LVPECL
Differential clock outputs
Negative power supply
a
VEE
V
CC
, V
CCO
Positive power supply. All V and V
pins must be connected to
CC
CCO
the positive power supply for correct DC and AC operation
VBB
Output
DC bias output for single ended input operation
a. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V).
In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V.
In both modes, the input and output levels are referrenced to the most positive supply (VCC).
Table 2: ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
Condition
V
CC
Supply Voltage
4.6
V
IN
DC Input Voltage
V
V
+0.3
V
CC
CC
V
OUT
DC Output Voltage
DC Input Current
+0.3
V
I
IN
20
50
mA
mA
°C
I
DC Output Current
Storage temperature
OUT
T
S
-65
125
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 3: GENERAL SPECIFICATIONS
Symbol
Characteristics
Output termination voltage
Min
Typ
Max
Unit
V
Condition
6
a
V
TT
V
- 2
CC
MM
HBM
CDM
LU
ESD Protection (Machine model)
ESD Protection (Human body model)
ESD Protection (Charged device model)
Latch-up immunity
75
1500
500
200
V
V
V
mA
pF
C
4.0
Inputs
IN
b
θ
Thermal resistance junction to ambient
Thermal resistance junction to case
See application information
See application information
JA
JC
θ
a. Output termination voltage V = 0V for V =2.5V operation is supported but the power consumption of the device will increase.
TT
CC
b. Proper thermal management is critical for reliable system operation. This especially true for high-fanout and high drive capability products.
Thermal package information and exposed pad land pattern design recommendations are available in the applications section of this data-
sheet. In addition, the means of calculating die power consumption, the corresponding die temperature and the relationsship to long-term
reliability is addressed in the Motorola application note AN1545. Thermal modeling is recommended for the MC100EP221.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
641
MC100EP221
Table 4: PECL and HSTL DC Characteristics (VCCO = VCC = 2.375V to 3.8V, VEE = GND)
Symbol
Characteristics
T
A
= -40°C
T
A
= 25°C
T = 85°C
A
Unit
Condition
Min
Max
Min
Max
Min
Max
a
Clock input pair CLK0, CLK0, CLK1, CLK1 (LVPECL differential signals)
V
PP
Differential input
b
voltage
V
CC
V
CC
=3.3V
=2.5V
0.10
0.15
0.10
0.15
0.10
0.15
V
V
V
CMR
Differential cross point
c
voltage
CLK0
1.0
0.1
V
CC
V
CC
-0.4
-1.0
1.0
0.1
V
CC
V
CC
-0.4
-1.0
1.0
0.1
V
CC
V
CC
-0.4
-1.0
V
V
CLK1
d
Clock input pair CLK1, CLK1 (HSTL differential signals)
V
DIF
Differential input
e
voltage
V
CC
V
CC
=3.3V
=2.5V
0.4
0.4
1.0
1.0
0.4
0.4
1.0
1.0
0.4
0.4
1.0
1.0
V
V
V
X
Differential cross point
voltage
0.68
0.9
0.68
0.9
0.68
0.9
V
f
V
Input high voltage
Input low voltage
V +0.2
V +0.5
V +0.2
V +0.5
V +0.2
V +0.5
V
V
IH
X
X
X
X
X
X
V
V -0.5
X
V -0.2
X
V -0.5
X
V -0.2
X
V -0.5
X
V -0.2
X
IL
All inputs (LVPECL single ended signals)
V
Input high voltage
Input low voltage
Input Current
V
-1.165
-1.810
V
V
-0.880
V
V
-1.165
V
V
-0.880
V
V
-1.165
V
V
-0.880
V
V
IH
CC
CC
CC
CC
CC
CC
CC
V
I
V
-1.480
-1.810
-1.480
-1.810
-1.480
IL
CC
CC
CC
CC
CC
150
150
150
µA
V
IN
= V to
CC
IH
V
EE
LVPECL clock outputs (Q0-19, Q0-19)
g
V
Output High Voltage
Output Low Voltage
V
-1.20
-1.90
V
-0.82
V
-1.15
-1.90
V
-0.82
V
-1.15
V
-0.82
V
V
I
= -30mA
OH
OH
CC
CC
CC
CC
CC
CC
g
V
V
CC
V
CC
-1.40
V
CC
V
CC
-1.40
V
-1.9
V
CC
-1.40
I
OL
= -5mA
OL
CC
Supply current and V
BB
6
I
Max. Supply Current
Max. Supply Current
190
750
190
750
190
750
mA
mA
V
V
pin
EE
CC
EE
h
I
pins
CC
V
BB
Output reference
i
voltage
V
CC
V
CC
=3.3V
=2.5V
V
CC
V
CC
-1.35
-1.35
V
CC
V
CC
-1.24
-1.24
V
CC
V
CC
-1.35
-1.35
V
CC
V
CC
-1.24
-1.22
V
V
-1.35
-1.35
V
CC
V
CC
-1.24
-1.22
V
V
CC
CC
a. The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets
both HSTL and LVPECL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage
(V
CMR
).
b. V is the minimum differential input voltage swing required to maintain device functionality.
PP
c. V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(DC)
(DC)
CMR
CMR
range and the input swing lies within the V (DC) specification.
d. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1.
PP
e. V
(DC) is the minimum differential HSTL input voltage swing required for device functionality. Only applicable to CLK1, CLK1.
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
DIF
f.
V
C
M
R
C
M
R
range and the input swing lies within the V (DC) specification.
PP
g. Equivalent to an output termination of 50Ω to V
.
TT
h. I includes current through the output resistors (all outputs terminated 50W to V ).
CC
TT
i.
V output can be used to bias the complementary input when the device is used with single ended clock signals. V can sink max. 0.3
BB BB
mA DC current.
642
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
MC100EP221
Table 5: ECL DC Characteristics (VCC = VCCO = GND, VEE = -3.8V to -2.375V)
Symbol
Characteristics
T
A
= -40°C
T
A
= 25°C
T = 85°C
A
Unit
Condition
Min
Max
Min
Max
Min
Max
a
Clock input pair CLK0, CLK0, CLK1, CLK1 for ECL differential signals
b
V
PP
Differential input voltage
V
V
=-3.3V
=-2.5V
c
0.10
0.15
0.10
0.15
0.10
0.15
V
V
EE
EE
V
CMR
Differential cross point voltage
CLK0
CLK1
V
EE
V
EE
+1.0
+0.1
-0.4
–1.0
V
EE
V
EE
+1.0
+0.1
-0.4
–1.0
V
EE
V
EE
+1.0
+0.1
-0.4
–1.0
V
V
All inputs ECL single ended signals
V
Input high voltage
Input low voltage
Input Current
-1.165
-1.810
-0.880
-1.480
150
-1.165
-1.810
-0.880
-1.480
150
-1.165
-1.810
-0.880
-1.480
150
V
V
IH
V
IL
I
IH
µA
V
V
= V
to
IN
CC
EE
LVPECL clock outputs (Q0-19, Q0-19)
d
V
Output High Voltage
Output Low Voltage
-1.20
-1.90
-0.82
-1.40
-1.20
-1.90
-0.82
-1.40
-1.20
-1.90
-0.82
-1.40
V
V
I
= -30 mA
OH
OH
d
V
I = -5 mA
OL
OL
Supply current and V
BB
I
Max. Supply Current
Max. Supply Current
190
750
190
750
190
750
mA
mA
V
V
pin
EE
CC
EE
e
I
Pins
CC
f
V
BB
Output reference voltage
V
EE
V
EE
=-3.3V
=-2.5V
-1.35
-1.35
-1.24
-1.24
-1.35
-1.35
-1.24
-1.22
-1.35
-1.35
-1.24
-1.22
V
V
a. The input pairs CLK0, CLK1 are compatible to differential signaling standards such as ECL. The difference between CLK0 and CLK1 is the
differential input threshold voltage (V ).
CMR
b. V is the minimum differential input voltage swing required to maintain device functionality.
PP
c. V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(DC)
CMR
CMR
range and the input swing lies within the V (DC) specification.
PP
6
d. Equivalent to an output termination of 50Ω to V
.
TT
e. I includes current through the output resistors (all outputs terminated 50W to V ).
CC
TT
f.
V output can be used to bias the complementary input when the device is used with single ended clock signals. V can sink max. 0.3
BB BB
mA DC current.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
643
MC100EP221
Table 6: PECL/ECL/HSTL AC Characteristicsa (VCC = VCCO = 2.375V to 3.8V, VEE = GND) or (VEE = -3.8V to -2.375V,
V
CC = VCCO = GND)
Symbol
Characteristics
T
A
= -40°C
T
A
= 25°C
T = 85°C
A
Unit Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
b
Clock input pair CLK0, CLK0, CLK1, CLK1 for PECL differential signals
c
V
PP
Differential input voltage
(peak-to-peak)
0.5
1.0
0.5
1.0
0.5
1.0
V
V
CMR
Differential cross point
voltage
d
CLK0
CLK1
1.0
0.3
V
CC
V
CC
-0.4
-1.3
1.0
0.3
V
V
-0.4
-1.3
1.0
0.3
V
V
-0.4
-1.3
V
V
CC
CC
CC
CC
f
Input Frequency (PECL)
0
1.0
1.0
1.0
GHz
CLK
Clock input pair CLK0, CLK0, CLK1, CLK1 for ECL differential signals
V
PP
Differential input voltage
(peak-to-peak)
0.5
1.0
0.5
1.0
0.5
1.0
V
V
CMR
Differential cross point
voltage
CLK0
CLK1
V
EE
V
EE
+1.0
+0.3
-0.4
-1.3
V
EE
V
EE
+1.0
+0.3
-0.4
–1.3
V
EE
V
EE
+1.0
+0.3
-0.4
-1.3
V
V
f
Input Frequency (ECL)
0
1.0
1.0
1.0
GHz
CLK
Clock input pair CLK1, CLK1 for HSTL differential signals
e
V
DIF
Differential input voltage
0.4
1.0
0.5
1.0
0.5
1.0
V
(peak-to-peak)
CLK1
V
X
Differential cross point
voltage
f
CLK1
0.68
0
0.9
1.0
0.68
0.9
1.0
0.68
0.9
1.0
V
f
Input Frequency (HSTL)
GHz
CLK
PECL/ECL clock outputs (Q0-19, Q0-19)
Propagation Delay
CLK to Qx
t
PD
350
370
460
500
600
640
390
440
520
570
660
710
480
530
630
680
750
800
ps
ps
Diff.
Diff.
0
CLK to Qx
1
6
V
O(P-P)
Differential output voltage
(peak-to-peak) f < 50 MHz
450
400
375
550
500
400
550
500
400
mV
mV
mV
O
f
O
f
O
< 0.8 GHz
< 1.0 GHz
t
Output-to-output skew
(within device)
sk(O)
30
50
50
30
50
50
30
50
50
ps
ps
Diff.
Diff.
t
Output-to-output skew
(part-to-part)
sk(PP)
270
270
270
t
Output cycle-to-cycle jitter
(RMS)
JIT(CC)
TBD
50.5
500
TBD
50.5
500
TBD
50.5
500
ps
%
DC
Output duty cycle
49.5
100
49.5
100
.
49.5
100
DC = 50%
O
fref
t , t
Output Rise/Fall Time
ps
20% to 80%
r
f
a. AC characteristics apply for parallel output termination of 50Ω to V
TT
b. The input pairs CLK0, CLK1 are compatible to differential signaling standards such as ECL. The difference between CLK0 and CLK1 is the
differential input threshold voltage (V ).
CMR
c. V (AC) is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
PP
d. V
(AC) is the crosspoint of the differential input signal. AC operation is obtained when the crosspoint is within the V
range and the
CMR
CMR
input swing lies within the V (AC) specification. Violation of V
(AC) or V
(AC) impacts the device propagation delay and part-to-
PP
CMR
PP
part skew.
e. V (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics. Only applicable to CLK1.
DIF
f.
V (AC) is the crosspoint of the differential HSTL input signal. AC operation is obtained when the crosspoint is within the V (AC) range
X X
and the input swing lies within the V
to-part skew.
(AC) specification. Violation of V (AC) or V
(AC) impacts the device propagation delay and part-
DIF
DIF
X
644
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
MC100EP221
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ꢁ Ω
ꢤ ꢥ ꢏ ꢁΩ
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ꢂ
ꢁ
ꢁ
ꢈ
ꢟ
ꢒ
ꢒ
ꢂ
ꢦ
ꢧ
ꢥ
ꢏ
ꢁ
Ω
ꢦ ꢥ ꢏ ꢁΩ
ꢧ
ꢍ
ꢧ ꢧ
ꢍ
ꢧ ꢧ
Figure 1. MC100EP221 AC test reference
ꢃ
ꢄ
ꢅ
ꢅ
ꢫ
ꢍ
ꢟ ꢟ
ꢥ ꢁ ꢯꢊ ꢍ
ꢍ ꢥ ꢍ ꢮꢂ ꢯ ꢑꢍ
ꢃ ꢩ ꢦ ꢃ ꢃ
ꢃ
ꢄ
ꢫ
ꢀ
ꢬ
ꢬ
ꢀ
ꢜ ꢪꢃꢄ ꢅ ꢜ ꢣ ꢀ ꢭ
ꢟ ꢖ ꢫ ꢬ
Figure 2. MC100EP221 AC reference measurement waveform
6
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
645
MC100EP221
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100EP221
array. Because a large solder mask opening may result in a
poor release, the opening should be subdivided as shown in
Figure 4 For the nominal package standoff 0.1 mm, a stencil
thickness of 5 to 8 mils should be considered.
The MC100EP221 uses a thermally enhanced exposed pad
(EP) 52 lead LQFP package. The package is molded so that
the leadframe is exposed at the surface of the package bottom
side. The exposed metal pad will provide the low thermal im-
pedance that supports the power consumption of the
MC100EP221 high-speed bipolar integrated circuit and eases
the power management task for the system design. A thermal
land pattern on the printed circuit board and thermal vias are
recommended in order to take advantage of the enhanced
thermal capabilities of the MC100EP221. Direct soldering of
the exposed pad to the thermal land will provide an efficient
thermal path. In multilayer board designs, thermal vias ther-
mally connect the exposed pad to internal copper planes.
Number of vias, spacing, via diameters and land pattern de-
sign depend on the application and the amount of heat to be
removed from the package. A nine thermal via array, arranged
in a 3 x 3 array and using a 1.2 mm pitch in the center of the
thermal land is the absolute minimum requirement for
MC100EP221 applications on multi-layer boards. The recom-
mended thermal land design comprises a 5 x 5 thermal via
array as shown in Figure 3 “Recommended thermal land pat-
tern”, providing an efficient heat removal path.
ꢝ ꢞꢞ ꢠ ꢛ ꢗꢜꢡ ꢱꢱ
ꢁ
ꢯ
ꢒ
ꢂ ꢯꢁ
ꢓ
ꢧ
ꢰ
ꢒ
ꢑ
ꢙ
ꢱ
ꢱ
ꢚ
ꢱ
ꢝ
ꢱ
ꢱ
ꢞ
ꢶ
ꢲ
ꢗ
ꢝ
ꢝ
ꢵ
ꢚ
ꢚ
ꢝ
ꢳ
ꢪ
ꢏ
ꢴ
ꢏ
ꢭ
ꢵ
ꢂ
ꢯ
ꢗ
ꢜ
ꢷ
ꢰ
ꢈ
ꢴ
ꢶꢣ
ꢡ
ꢙ
ꢸ
ꢶ
ꢝ
ꢸ
ꢁ
ꢯ
ꢸ ꢗꢝꢱ ꢙꢜ ꢙ ꢚ
ꢞꢝ ꢛꢸ ꢶ ꢝꢜ ꢜ ꢙꢚ
ꢛ
Figure 4. Recommended solder mask openings
ꢝꢞ ꢞ ꢠ ꢛꢗꢜ ꢡ ꢱꢱ
For thermal system analysis and junction temperature cal-
culation the thermal resistance parameters of the package is
provided. For thermal system analysis and junction tempera-
ture calculation the thermal resistance parameters of the pack-
age is provided:
6
Table 7: Thermal Resistancea
b
c
d
e
Convection-
LFPM
R
R
R
°C/W
R
THJB
°C/W
THJA
THJA
THJC
°C/W
57.1
50.0
46.9
43.4
38.6
°C/W
24.9
21.3
20.0
18.7
16.9
Natural
100
200
15.8
9.7
400
ꢓ
800
a. Thermal data pattern with a 3 x 3 thermal via array on
2S2P boards (based on empirical results)
b. Junction to ambient, single layer test board, per JESD51-6
c. Junction to ambient, four conductor layer test board
(2S2P), per JES51-6
ꢧ
ꢰ
ꢒ
ꢑ
ꢙ
ꢱ
ꢱ
ꢚ
ꢱ
ꢝ
ꢱ
ꢱ
ꢞ
ꢶ
ꢲ
ꢗ
ꢝ
ꢝ
ꢵ
ꢚ
ꢚ
ꢝ
ꢳ
ꢪ
ꢏ
ꢴ
ꢏ
ꢭ
ꢵ
ꢈ
ꢴ
ꢛ
ꢶ
ꢸ
ꢣ
ꢶ
ꢡ
ꢝ
ꢙ
ꢜ
ꢸ
ꢶ
ꢚ
ꢝ
ꢛ
ꢸ
ꢂ
ꢁ
ꢯ
ꢯ
ꢗ
ꢜ
ꢷ
ꢰ
ꢞ
ꢝ
ꢜ
ꢙ
ꢸ ꢗꢝ ꢱꢙ ꢜꢙ ꢚ
Figure 3. Recommended thermal land pattern
The via diameter is should be approx. 0.3 mm with 1 oz.
d. Junction to case, per MIL-SPEC 883E, method 1012.1
copper via barrel plating. Solder wicking inside the via resulting e. Junction to board, four conductor layer test board (2S2P)
in voids during the solder process must be avoided. If the cop-
per plating does not plug the vias, stencil print solder paste
per JESD 51-8
It is recommended that users employ thermal modeling
onto the printed circuit pad. This will supply enough solder analysis to assist in applying the general recommendations to
paste to fill those vias and not starve the solder joints. The their particular application. The exposed pad of the
attachment process for exposed pad package is equivalent to MC100EP221 package does not have an electrical low imped-
standard surface mount packages. Figure 4 “Recommended ance path to the substrate of the integrated circuit and its termi-
solder mask openings” shows a recommend solder mask nals. The thermal land should be connected to GND through
opening with respect to the recommended 5 x 5 thermal via connection of internal board layers.
646
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
相关型号：
MC100EP223FA
Low Skew Clock Driver, 100E Series, 22 True Output(s), 0 Inverted Output(s), ECL, PQFP64, PLASTIC, TQFP-64
MOTOROLA
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