MC100EP29DTR2 [ONSEMI]
3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset; 3.3V / 5V ECL双差分数据和时钟D触发器有设定和复位
| 型号： | MC100EP29DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset |
| 文件： | 总8页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP29, MC100EP29
3.3V / 5VĄECL Dual
Differential Data and Clock
D Flip-Flop With Set and
Reset
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The MC10/100EP29 is a dual master–slave flip–flop. The device
features fully differential Data and Clock inputs as well as outputs.
The MC10/100EP29 is functionally equivalent to the
MC10/100EL29. Data enters the master latch when the clock is LOW
and transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
MARKING
DIAGRAM*
20
20
are left open the D input will pull down to V and the D input will
EE
xxx
EP29
ALYW
1
bias around V /2. The outputs will go to a defined state, however the
CC
TSSOP–20
DT SUFFIX
CASE 948E
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
1
xxx = MC10 or 100
A
L
Y
W
The V pin, an internally generated voltage supply, is available to
BB
= Assembly Location
this device only. For single-ended input conditions, the unused
= Wafer Lot
= Year
= Work Week
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
The 100 Series contains temperature compensation.
BB
*For additional information, see Application Note
AND8002/D
• Maximum Frequency > 3 GHz Typical
• 500 ps Typical Propagation Delays
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
ORDERING INFORMATION
CC
with V = 0 V
EE
Device
Package
Shipping
• NECL Mode Operating Range: V = 0 V
CC
MC10EP29DT
TSSOP–20
75 Units/Rail
with V = –3.0 V to –5.5 V
EE
MC10EP29DTR2 TSSOP–20 2500 Tape & Reel
MC100EP29DT TSSOP–20 75 Units/Rail
• Open Input Default State
• Safety Clamp on Inputs
MC100EP29DTR2 TSSOP–20 2500 Tape & Reel
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
September, 2002 – Rev. 2
MC10EP29/D
MC10EP29, MC100EP29
V
CC
R0
S0
Q0
Q0
Q1
Q1
S1
R1
V
EE
20
19
18
17
16
15
14
13
12
11
R
S
Q
Q
Q
S
R
Q
CLK
D
D
CLK
1
2
3
4
5
6
7
8
9
10
D0
D0
V
BB
CLK0 CLK0 CLK1 CLK1
D1
D1
V
CC
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
Figure 1. 20–Lead Pinout (Top View) and Logic Diagram
PIN DESCRIPTION
TRUTH TABLE
PIN
FUNCTION
R
S
D
CLK
Q
Q
D0*, D0*; D1*, D1*
R0*, R1*
ECL Differential Data Inputs
ECL Reset Inputs
L
L
H
L
H
L
L
L
H
H
L
H
X
X
X
Z
Z
X
X
X
L
H
L
H
Undef
H
L
H
L
CLK0*, CLK0*
CLK1*, CLK1*
S0*, S1*
ECL Differential Clock Inputs
ECL Differential Clock Inputs
ECL Set Inputs
Undef
Z = LOW to HIGH Transition
X = Don’t Care
Q0, Q0; Q1, Q1
ECL Differential Data Outputs
Reference Voltage Output
Positive Supply
V
BB
V
CC
V
EE
Negative Supply
*
Pins will default LOW when left open.
ATTRIBUTES
Characteristics
Value
75 kW
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V–0 @ 0.125 in
383 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC10EP29, MC100EP29
MAXIMUM RATINGS (Note 2)
Symbol Parameter
Condition 1
= 0 V
Condition 2
Rating
Units
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
6
V
V
EE
= 0 V
–6
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
V
V
EE
I
CC
V ꢁ V
–6
CC
I
EE
I
Output Current
Continuous
Surge
50
mA
mA
out
100
I
V
Sink/Source
± 0.5
mA
°C
BB
BB
TA
Operating Temperature Range
Storage Temperature Range
–40 to +85
–65 to +150
T
°C
stg
q
Thermal Resistance (Junction–to–Ambient) 0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JA
q
Thermal Resistance (Junction–to–Case)
Wave Solder
std bd
20 TSSOP
23 to 41
265
°C/W
°C
JC
T
sol
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3)
CC
EE
–40°C
Typ
25°C
85°C
Symbol
Characteristic
Power Supply Current
Min
Max
55
Min
37
Typ
48
Max
57
Min
Typ
49
Max
60
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
35
46
40
V
V
V
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
2165
1365
2090
1365
1790
2.0
2290
1490
2415
1615
2415
1690
1990
3.3
2230
1430
2155
1460
1855
2.0
2355
1555
2480
1680
2480
1755
2055
3.3
2290
1490
2215
1490
1915
2.0
2415
1615
2540
1740
2540
1815
2115
3.3
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Output Voltage Reference
IH
IL
V
V
1890
1955
2015
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
4. All loading with 50 W to V –2.0 volts.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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3
MC10EP29, MC100EP29
10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
55
Min
37
Max
57
Min
40
Max
60
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
35
46
48
49
V
V
V
V
V
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
3865
3065
3790
3065
3490
2.0
3990
3190
4115
3315
4115
3390
3690
5.0
3930
3130
3855
3130
3555
2.0
4055
3255
4180
3380
4180
3455
3755
5.0
3990
3190
3915
3190
3615
2.0
4115
3315
4240
3440
4240
3515
3815
5.0
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Output Voltage Reference
IH
IL
3590
3655
3715
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
7. All loading with 50 W to V –2.0 volts.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 9)
CC
EE
–40°C
Typ
46
25°C
Typ
48
85°C
Typ
49
Symbol
Characteristic
Power Supply Current
Min
35
Max
Min
Max
Min
Max
60
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
55
37
57
40
V
V
V
V
V
V
Output HIGH Voltage (Note 10)
Output LOW Voltage (Note 10)
–1135 –1010 –885 –1070 –945
–820 –1010 –885
–760
OH
–1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Output Voltage Reference
–1210
–1935
–885 –1145
–1610 –1870
–820 –1085
–1545 –1810
–760
IH
–1485
IL
–1510 –1410 –1310 –1445 –1345 –1245 –1385 –1285 –1185
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with V
.
CC
10.All loading with 50 W to V –2.0 volts.
CC
11. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP29, MC100EP29
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 12)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
55
Min
37
Max
57
Min
40
Max
60
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
35
46
48
49
V
V
V
V
V
V
Output HIGH Voltage (Note 13)
Output LOW Voltage (Note 13)
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Output Voltage Reference
IH
IL
1875
1875
1875
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12.Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
13.All loading with 50 W to V –2.0 volts.
CC
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 15)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
55
Min
37
Max
57
Min
40
Max
60
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
35
46
48
49
V
V
V
V
V
V
Output HIGH Voltage (Note 16)
Output LOW Voltage (Note 16)
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Output Voltage Reference
IH
IL
3575
3575
3575
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15.Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
16.All loading with 50 W to V –2.0 volts.
CC
17.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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5
MC10EP29, MC100EP29
100EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 18)
CC
EE
–40°C
Typ
46
25°C
Typ
48
85°C
Typ
49
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
35
55
37
57
40
60
V
V
V
V
V
V
Output HIGH Voltage (Note 19)
Output LOW Voltage (Note 19)
–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895
–1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695
OH
OL
Input HIGH Voltage (Single–Ended)
Input LOW Voltage (Single–Ended)
Output Voltage Reference
–1225
–1945
–880 –1225
–1625 –1945
–880 –1225
–1625 –1945
–880
IH
–1625
IL
–1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18.Input and output parameters vary 1:1 with V
.
CC
19.All loading with 50 W to V –2.0 volts.
CC
20.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
AC CHARACTERISTICS V = 0 V; V = –3.0 V to –5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 21)
CC
EE
CC
EE
–40°C
25°C
85°C
Typ
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
f
Maximum Frequency
(See Figure 2 F /JITTER)
> 3.0
> 3.0
> 3.0
GHz
max
max
t
t
,
Propagation Delay to
Output Differential
CLK
S
R
300
275
300
380
380
400
450
475
500
350
300
325
420
400
420
500
500
525
400
350
375
470
450
470
550
550
575
ps
PLH
PHL
t
t
Setup Time
Hold Time
100
100
20
20
100
100
20
20
100
100
20
20
ps
ps
S
H
t
t
/t
Set/Reset Recovery
Minimum Pulse Width
150
80
150
80
150
80
RR RR2
PW
Set, Reset
500
300
.2
500
300
.2
500
300
.2
ps
ps
t
Cycle–to–Cycle Jitter
< 1
< 1
< 1
JITTER
(See Figure 2 F
/JITTER)
max
V
Input Voltage Swing (Note 22)
150
100
800
180
1200
250
150
150
800
210
1200
300
150
175
800
230
1200
325
mV
ps
PP
t
r
t
f
Output Rise/Fall Times
(20% – 80%)
Q, Q
21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V –2.0 V.
CC
22.V (min) is the minimum input swing for which AC parameters are guaranteed.
PP
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6
MC10EP29, MC100EP29
900
800
700
600
500
400
300
200
100
0
9
8
7
6
5
4
3
2
(JITTER)
1
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
Q
D
D
Receiver
Device
Driver
Device
50
TT
50
W
W
V
TT
V
V
=
– 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
–
–
–
–
–
–
–
–
–
–
–
ECLinPS Circuit Performance at Non–Standard V Levels
IH
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire–OR Ties in ECLinPS Designs
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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7
MC10EP29, MC100EP29
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. ICONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
20X K REF
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
6.60 0.252
4.50 0.169
N
C
1.20
---
D
0.05
0.50
0.15 0.002
0.75 0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
J1
K
C
K1
L
6.40 BSC
0.252 BSC
0
G
D
M
0
8
8
_
_
_
_
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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