MC100EP31D [ONSEMI]
D Flip Flop with Set and Reset; D触发器具有置位和复位
| 型号： | MC100EP31D |
| 厂家： | 
ONSEMI |
| 描述： | D Flip Flop with Set and Reset |
| 文件： | 总8页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP31, MC100EP31
3.3V / 5VĄECL D Flip-Flop
with Set and Reset
The MC10/100EP31 is a D flip–flop with set and reset. The device
is pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip–flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
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MARKING DIAGRAMS*
8
8
8
HEP31
ALYW
KEP31
ALYW
The 100 Series contains temperature compensation.
1
SO–8
• 340 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
D SUFFIX
CASE 751
1
1
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
with V = 0 V
EE
8
1
8
1
8
• NECL Mode Operating Range: V = 0 V
CC
1
HP31
ALYW
KP31
ALYW
with V = –3.0 V to –5.5 V
EE
TSSOP–8
DT SUFFIX
CASE 948R
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V
EE
L = Wafer Lot
Y = Year
H = MC10
K = MC100
W = Work Week
A = Assembly Location
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC10EP31D
SO–8
98 Units/Rail
MC10EP31DR2
MC100EP31D
MC100EP31DR2
MC10EP31DT
SO–8
SO–8
2500 Tape & Reel
98 Units/Rail
SO–8
2500 Tape & Reel
100 Units/Rail
TSSOP–8
MC10EP31DTR2 TSSOP–8 2500 Tape & Reel
MC100EP31DT TSSOP–8 100 Units/Rail
MC100EP31DTR2 TSSOP–8 2500 Tape & Reel
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
April, 2001 – Rev. 5
MC10EP31/D
MC10EP31, MC100EP31
PIN DESCRIPTION
FUNCTION
PIN
CLK*
ECL Clock Inputs
ECL Asynchronous Reset
ECL Asynchronous Set
ECL Data Input
SET
D
1
2
8
7
V
CC
Reset*
Set*
D*
S
Q
Q
D
Q, Q
ECL Data Outputs
Positive Supply
V
V
CC
Flip Flop
Negative Supply
EE
CLK
3
4
6
5
*
Pins will default LOW when left open.
R
TRUTH TABLE
D
SET
RESET
CLK
Q
RESET
V
EE
L
L
L
H
L
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
H
X
X
X
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
H
UNDEF
Z = LOW to HIGH Transition
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
75 kW
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.)
Level 1
Flammability Rating
Oxygen Index
UL–94 code V–0 A 1/8”
28 to 34
Transistor Count
75 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Units
V
V
V
6
V
V
CC
EE
I
EE
V
V
= 0 V
–6
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V ꢀ V
6
–6
V
V
I
CC
EE
V ꢁ V
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
TA
Operating Temperature Range
–40 to +85
°C
°C
T
stg
Storage Temperature Range
–65 to +150
θ
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
°C/W
°C/W
JA
θ
θ
Thermal Resistance (Junction to Case)
Thermal Resistance (Junction to Ambient)
std bd
8 SOIC
41 to 44
°C/W
JC
JA
0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
θ
Thermal Resistance (Junction to Case)
Wave Solder
std bd
8 TSSOP
41 to 44
265
°C/W
°C
JC
T
<2 to 3 sec @ 248°C
sol
2. Maximum Ratings are those values beyond which device damage may occur.
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2
MC10EP31, MC100EP31
10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
44
Min
26
Max
45
Min
28
Max
47
Unit
mA
mV
mV
mV
mV
µA
I
EE
26
34
35
37
V
V
V
V
Output HIGH Voltage (Note 4.)
Output LOW Voltage (Note 4.)
2165
1365
2090
1365
2240
1490
2415
1615
2415
1690
150
2230
1430
2155
1430
2355
1555
2480
1680
2480
1755
150
2290
1490
2215
1490
2415
1615
2540
1740
2540
1815
150
OH
OL
IH
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Input HIGH Current
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
4. All loading with 50 ohms to V –2.0 volts.
CC
10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
44
Min
26
Max
45
Min
28
Max
47
Unit
mA
mV
mV
mV
mV
µA
I
EE
26
34
35
37
V
V
V
V
Output HIGH Voltage (Note 6.)
Output LOW Voltage (Note 6.)
3865
3065
3790
3065
3940
3190
4115
3315
4115
3390
150
3930
3130
3855
3130
4055
3255
4180
3380
4180
3455
150
3990
3190
3915
3190
4115
3315
4240
3440
4240
3515
150
OH
OL
IH
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Input HIGH Current
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
6. All loading with 50 ohms to V –2.0 volts.
CC
10EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 7.)
CC
EE
–40°C
Typ
34
25°C
Typ
35
85°C
Typ
37
Symbol
Characteristic
Power Supply Current
Min
26
Max
Min
Max
Min
Max
47
Unit
mA
mV
mV
mV
mV
µA
I
EE
44
26
45
28
V
V
V
V
Output HIGH Voltage (Note 8.)
Output LOW Voltage (Note 8.)
–1135 –1060 –885 –1070 –945
–820 –1010 –885
–760
OH
OL
IH
–1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Input HIGH Current
–1210
–1935
–885 –1145
–1610 –1870
150
–820 –1085
–1545 –1810
150
–760
–1485
150
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with V
.
CC
8. All loading with 50 ohms to V –2.0 volts.
CC
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3
MC10EP31, MC100EP31
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 9.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
44
Min
26
Max
45
Min
28
Max
47
Unit
mA
mV
mV
mV
mV
µA
I
EE
26
34
35
37
V
V
V
V
Output HIGH Voltage (Note 10.)
Output LOW Voltage (Note 10.)
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
OH
OL
IH
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Input HIGH Current
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with V . V can vary +0.3 V to –2.2 V.
CC
EE
10.All loading with 50 ohms to V –2.0 volts.
CC
100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 11.)
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
44
Min
26
Max
45
Min
28
Max
47
Unit
mA
mV
mV
mV
mV
µA
I
EE
26
34
35
37
V
V
V
V
Output HIGH Voltage (Note 12.)
Output LOW Voltage (Note 12.)
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
OH
OL
IH
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Input HIGH Current
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with V . V can vary +2.0 V to –0.5 V.
CC
EE
12.All loading with 50 ohms to V –2.0 volts.
CC
100EP DC CHARACTERISTICS, NECL V = 0 V; V = –5.5 V to –3.0 V (Note 13.)
CC
EE
–40°C
Typ
34
25°C
Typ
35
85°C
Typ
37
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
µA
I
EE
26
44
26
45
28
47
V
V
V
V
Output HIGH Voltage (Note 14.)
Output LOW Voltage (Note 14.)
–1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895
–1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695
OH
OL
IH
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Input HIGH Current
–1225
–1945
–880 –1225
–1625 –1945
150
–880 –1225
–1625 –1945
150
–880
–1625
150
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13.Input and output parameters vary 1:1 with V
.
CC
14.All loading with 50 ohms to V –2.0 volts.
CC
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4
MC10EP31, MC100EP31
AC CHARACTERISTICS V = 0 V; V = –3.0 V to –5.5 V or
V = 3.0 V to 5.5 V; V = 0 V (Note 15.)
CC EE
CC
EE
–40°C
25°C
85°C
Typ
> 3
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
f
Maximum Frequency
(See Figure 2. F /JITTER)
> 3
> 3
GHz
max
max
t
t
,
Propagation Delay to
Output Differential
ps
PLH
PHL
CLK to Q, Q
S, R to Q, Q
250
300
330
380
400
450
270
330
340
400
410
470
300
360
370
430
440
500
t
Set/Reset Recovery
225
225
225
ps
ps
RR
t
S
t
H
Setup Time
Hold Time
100
150
100
150
100
150
t
Minimum Pulse width
ps
ps
ps
PW
SET, RESET
550
50
450
0.2
550
60
450
0.2
550
70
450
0.2
t
Cycle–to–Cycle Jitter
< 1
< 1
< 1
JITTER
(See Figure 2. F
/JITTER)
max
t
r
t
f
Output Rise/Fall Times
(20% – 80%)
Q, Q
120
180
130
200
150
220
15.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V –2.0 V.
CC
1100
1000
900
800
700
600
500
400
300
200
100
11
10
9
8
7
6
5
4
3
2
1
(JITTER)
3000
0
0
1000
2000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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5
MC10EP31, MC100EP31
Q
D
Receiver
Device
Driver
Device
Qb
Db
50
TT
50
W
W
V
TT
V
V
=
– 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
ECLinPS Circuit Performance at Non–Standard VIH Levels
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire–OR Ties in ECLinPS Designs
The ECL Translator Guide
–
–
–
–
–
–
–
–
–
–
–
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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6
MC10EP31, MC100EP31
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
–Y–
G
MILLIMETERS
INCHES
DIM MIN
MAX
5.00
4.00
1.75
0.51
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
0.189
0.150
0.053
0.013
C
N X 45
_
SEATING
PLANE
–Z–
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25
0.25
1.27
8
0.004
0.010
0.010
0.050
8
0.007
0.016
0
M
J
H
D
K
M
N
S
_
_
_
_
0.25
5.80
0.50
6.20
0.010
0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
TSSOP–8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R–02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8x K REF
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2X L/2
8
5
4
0.25 (0.010)
B
–U–
L
1
M
PIN 1
IDENT
S
0.15 (0.006) T U
A
–V–
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
–W–
SEATING
PLANE
D
–T–
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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7
MC10EP31, MC100EP31
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC10EP31/D
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