MC100EP31 [ONSEMI]
3.3V / 5V ECL D Flip−Flop with Set and Reset; 3.3V / 5V ECL D触发器具有置位和复位
| 型号： | MC100EP31 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5V ECL D Flip−Flop with Set and Reset |
| 文件： | 总11页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP31, MC100EP31
3.3V / 5VꢀECL D Flip−Flop
with Set and Reset
Description
The MC10/100EP31 is a D flip−flop with set and reset. The device
is pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip−flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
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MARKING DIAGRAMS*
8
8
8
HEP31
ALYW
G
KEP31
ALYW
G
1
SOIC−8
D SUFFIX
CASE 751
Features
1
1
The 100 Series contains temperature compensation.
• 340 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range:
8
8
1
8
1
HP31
KP31
V
= 3.0 V to 5.5 V with V = 0 V
CC
EE
ALYWG
ALYWG
TSSOP−8
DT SUFFIX
CASE 948R
G
G
• NECL Mode Operating Range:
= 0 V with V = −3.0 V to −5.5 V
1
V
CC
EE
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V
• Pb−Free Packages are Available
EE
1
4
1
4
DFN8
MN SUFFIX
CASE 506AA
H
K
= MC10
= MC100
A
L
= Assembly Location
= Wafer Lot
5O = MC10
3J = MC100
Y
W
G
= Year
= Work Week
= Pb−Free Package
M
= Date Code
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 9
MC10EP31/D
MC10EP31, MC100EP31
Table 1. PIN DESCRIPTION
Pin
SET
D
1
2
8
7
V
CC
Function
CLK*
Reset*
Set*
ECL Clock Inputs
S
ECL Asynchronous Reset
ECL Asynchronous Set
ECL Data Input
Q
Q
D
D*
Flip Flop
Q, Q
ECL Data Outputs
Positive Supply
CLK
3
4
6
5
V
CC
V
EE
R
Negative Supply
EP
Exposed pad must be connected to a
sufficient thermal conduit. Electrically
connect to the most negative supply or
leave floating open.
RESET
V
EE
*Pins will default LOW when left open.
Figure 1. 8−Lead Pinout (Top View) and
Logic Diagram
Table 2. TRUTH TABLE
D
SET
RESET
CLK
Q
L
H
X
X
X
L
L
H
L
H
L
L
Z
Z
X
X
X
L
H
L
H
L
H
H
UNDEF
Z = LOW to HIGH Transition
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Value
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
75 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC10EP31, MC100EP31
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
6
EE
= 0 V
−6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
I
CC
V w V
CC
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
°C
°C
A
T
stg
JA
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
JC
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
q
q
Thermal Resistance (Junction−to−Case)
TSSOP−8
41 to 44
°C/W
JC
JA
DFN8
DFN8
129
84
°C/W
°C/W
500 lfpm
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10EP31, MC100EP31
Table 5. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Min
26
Typ
34
Max
44
Min
26
Max
45
Min
28
Max
47
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
EE
35
37
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Current
2165
1365
2090
1365
2290
1490
2415
1615
2415
1690
150
2230
1430
2155
1430
2355
1555
2480
1680
2480
1755
150
2290
1490
2215
1490
2415
1615
2540
1740
2540
1815
150
OH
OL
IH
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 4)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Characteristic
Power Supply Current
Min
26
Typ
34
Max
44
Min
26
Max
45
Min
28
Max
47
Unit
mA
mV
mV
mV
mV
mA
Symbol
I
EE
35
37
V
V
V
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Current
3865
3065
3790
3065
3990
3190
4115
3315
4115
3390
150
3930
3130
3855
3130
4055
3255
4180
3380
4180
3455
150
3990
3190
3915
3190
4115
3315
4240
3440
4240
3515
150
OH
OL
IH
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
5. All loading with 50 W to V − 2.0 V.
CC
Table 7. 10EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 6)
CC
EE
−40°C
Typ
34
25°C
Typ
35
85°C
Typ
37
Min
26
Max
Min
Max
Min
Max
47
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
EE
44
26
45
28
VOH
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Current
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
V
OL
V
IH
V
IL
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560
−1210
−1935
−885 −1145
−1610 −1870
150
−820 −1085
−1545 −1810
150
−760
−1485
150
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V
.
CC
7. All loading with 50 W to V − 2.0 V.
CC
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4
MC10EP31, MC100EP31
Table 8. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 8)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
26
Max
Min
26
Max
45
Min
28
Max
47
Unit
mA
mV
mV
mV
mV
mA
I
EE
34
44
35
37
V
V
V
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Current
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
OH
OL
IH
IL
I
IH
IL
I
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
9. All loading with 50 W to V − 2.0 V.
CC
Table 9. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 10)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
26
Max
Min
26
Max
45
Min
28
Max
47
Unit
mA
mV
mV
mV
mV
mA
I
EE
34
44
35
37
V
V
V
V
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Current
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
OH
OL
IH
IL
I
IH
IL
I
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
11. All loading with 50 W to V − 2.0 V.
CC
Table 10. 100EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 12)
CC
EE
−40°C
25°C
Typ
35
85°C
Typ
37
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
mA
I
EE
26
34
44
26
45
28
47
V
V
V
V
Output HIGH Voltage (Note 13)
Output LOW Voltage (Note 13)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Current
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
OH
OL
IH
−1225
−1945
−880 −1225
−1625 −1945
150
−880 −1225
−1625 −1945
150
−880
−1625
150
IL
I
IH
IL
I
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12.Input and output parameters vary 1:1 with V
.
CC
13.All loading with 50 W to V − 2.0 V.
CC
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5
MC10EP31, MC100EP31
Table 11. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 14)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 3
85°C
Typ
> 3
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
Unit
f
> 3
GHz
max
(Figure 2)
t
t
,
Propagation Delay to
Output Differential
ps
PLH
PHL
CLK to Q, Q
S, R to Q, Q
250
300
330
380
400
450
270
330
340
400
410
470
300
360
370
430
440
500
t
Set/Reset Recovery
225
225
225
ps
ps
RR
t
S
t
H
Setup Time
Hold Time
100
150
100
150
100
150
t
Minimum Pulse width
ps
ps
ps
PW
SET, RESET
Q, Q
550
50
450
0.2
550
60
450
0.2
550
70
450
0.2
t
Cycle−to−Cycle Jitter
(Figure 2)
< 1
< 1
< 1
JITTER
t
r
t
f
Output Rise/Fall Times
(20% − 80%)
120
180
130
200
150
220
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V −2.0 V.
CC
1100
1000
900
800
700
600
500
400
300
200
100
11
10
9
8
7
6
5
4
3
2
1
(JITTER)
3000
0
0
1000
2000
4000
5000
6000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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6
MC10EP31, MC100EP31
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10EP31D
SOIC−8
98 Units / Rail
98 Units / Rail
MC10EP31DG
SOIC−8
(Pb−Free)
MC10EP31DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
MC10EP31DR2G
SOIC−8
(Pb−Free)
MC10EP31DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC10EP31DTG
TSSOP−8
(Pb−Free)
MC10EP31DTR2
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
MC10EP31DTR2G
TSSOP−8
(Pb−Free)
MC10EP31MNR4
MC10EP31MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
MC100EP31D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100EP31DG
SOIC−8
(Pb−Free)
MC100EP31DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
MC100EP31DR2G
SOIC−8
(Pb−Free)
MC100EP31DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100EP31DTG
TSSOP−8
(Pb−Free)
MC100EP31DTR2
MC100EP31DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EP31MNR4
MC100EP31MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MC10EP31, MC100EP31
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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8
MC10EP31, MC100EP31
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MC10EP31, MC100EP31
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
http://onsemi.com
10
MC10EP31, MC100EP31
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
8 X b
0.05
C
NOTE 3
BOTTOM VIEW
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