MSM9210 [OKI]
32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming; 32位双面/三（ 1/2占空比/ 1/3占空比） VF控制器/驱动器与数字调光
| 型号： | MSM9210 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming |
| 文件： | 总20页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2C0038-39-95
This version: Sep. 1999
Previous version: Aug. 1999
¡ Semiconductor
MSM9210
32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming
GENERAL DESCRIPTION
The MSM9210 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty)
vacuum fluorescent display tube. It consists of a 32-segment driver multiplexed to drive up to
96 segments, and 10-bit digital dimming circuit.
MSM9210 features a selection of a master mode and a slave mode, and therefore it can be used
to expand segments for the VFD driver with keyscan and A/D converter function.
MSM9210 provides an interface with a microcontroller only by three signal lines: DATA IN,
CLOCK and CS.
FEATURES
• Logic supply voltage (V
• Driver supply voltage (V
)
: 4.5 to 5.5V
: 8 to 18V
DD
)
DISP
• Duplex/Triplex (1/2 duty / 1/3 duty) selectable
DUP/TRI=1/2 duty selectable at "H" level
DUP/TRI=1/3 duty selectable at "L" level
• Number of display segments
Max. 64-segment display (during 1/2 duty mode)
Max. 96-segment display (during 1/3 duty mode)
• Master/Slave selectable
M/S=Master mode selectable at "H" level
M/S=Slave mode selectable at "L" level
• Interface with a microcontroller
Three lines: CS, CLOCK, and DATA IN
• 32-segment driver outputs
(can be directly connected to VFD tube
and require no external resisters)
• 3-grid pre-driver outputs
(require external drivers)
: I =–5mA at V =V
–0.8V (SEG1 to 22)
DISP
DISP
OH
OH
: I =–10mA at V =V –0.8V (SEG23 to 32)
OH
OH
: I =500mA at V =2V (SEG1 to 32)
OL
OL
: I =–5.0mA at V =V –0.8V
OH
OH
DISP
I
=10mA at V =2V
OL
OL
• Logic outputs
: I =–200mA at V =V –0.8V
OH OH DD
I
=200mA at V =0.8V
OL
OL
• Built-in digital dimming circuit (10-bit resolution)
• Built-in oscillation circuit (external R and C)
• Built-in Power-On-Reset circuit
• Package options:
56-pin plastic QFP (QFP56-P-910-0.65-2K)
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
Product name: MSM9210GS-2K
Product name: MSM9210GS-BK
1/19
¡ Semiconductor
MSM9210
BLOCK DIAGRAM
SEG1
SEG32
GRID1 GRID2 GRID3
VDISP
32 Segment Driver
Out1-32
3 Grid pre Driver
D-GND
Power
On
Reset
VDD
POR
L-GND
96 to 32 Segment Control
in1-32
in1-32
in1-32
0H
4H
Out1-32
Segment Latch
Out1-32
Segment Latch
Out1-32
Segment Latch
1H
0H
2H
0H
3H
0H
Mode Select
in1-3
1
2
3
POR
POR
POR
POR
in1-32
in1-32
in1-32
CS
CLOCK
Out1-3
3bit Shift Register
Out1-32
32bit Shift Register
in1-10
Dimming Latch
Out1-10
4H
Control
POR
DATA IN
POR
POR
10bit Digital
Dimming
OSC0
OSC1
OSC
POR
DIM IN
SYNC IN1
SYNC IN2
M/S
DIM OUT
SYNC OUT1
SYNC OUT2
Timing Generator
DUP/TRI
2/19
¡ Semiconductor
MSM9210
INPUT AND OUTPUT CONFIGURATION
Schematic Diagram of Driver Output Circuit
VDISP
VDISP
OUTPUT
D-GND
D-GND
3/19
¡ Semiconductor
MSM9210
PIN CONFIGURATION (TOP VIEW)
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
GRID1
1
2
3
4
5
6
7
8
9
42 SEG13
41 SEG12
40 SEG11
39 SEG10
38 SEG9
37 SEG8
36 SEG7
35 SEG6
34 SEG5
33 SEG4
32 SEG3
31 SEG2
30 SEG1
29 NC
GRID2 10
GRID3 11
D-GND 12
NC 13
VDD 14
NC: No connection
56-pin Plastic QFP
4/19
¡ Semiconductor
MSM9210
NC
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
GRID1
GRID2
GRID3
D-GND
NC
NC
NC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
NC
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
NC
NC: No connection
64-pin Plastic QFP
5/19
¡ Semiconductor
MSM9210
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
QFP56
QFP64
Power supply pins for VFD driver circuit.
43 pin and 56 pin should be connected externally.
Power supply pin for logic drive.
VDISP
43,56
49,64
—
VDD
14
15
—
—
D-GND is ground pin for the VFD driver circuit. L-GND is ground
pin for the logic circuit. 12pin, 21pin and 49pin should be
connected externally.
D-GND
12, 49
13, 56
L-GND
21
24
—
Segment (anode) signal output pins for a VFD tube.
These pins can be directly connected to the VFD tube.
External circuit is not required.
30 to 42,
44 to 48,
50 to 53
34 to 46,
51 to 55,
57 to 60
SEG1 to 22
O
IOH£–5 mA
Segment (anode) signal output pins for a VFD tube.
These pins can be directly connected to the VFD tube.
External circuit is not required.
1 to 8,
54, 55
2 to 9,
61, 62
SEG23 to 32
O
O
IOH£–10 mA
Inverted Grid signal output pins.
GRID1 to 3
9, 10, 11 10, 11, 12
For pre-driver, the external circuit is required.
IOL£10 mA
Chip select input pin.
CS
18
19
20
21
22
23
I
I
I
Data is not transferred when CS is set to a Low level.
Shift clock input pin.
CLOCK
DATA IN
Serial data shifts at the rising edge of the CLOCK.
Serial data input pin (positive logic).
Data is input to the shift register at the rising edge of the CLOCK signal.
Duplex/Triplex operation select input pin.
Duplex (1/2 duty) operation is selected when this pin is set to VDD
.
DUP/TRI
M/S
24
25
27
28
I
I
Triplex (1/3 duty) operation is selected when this pin is set to L-GND.
Master/Slave mode select input pin.
Master mode is selected when this pin is set to VDD
.
Slave mode is selected when this pin is set to L-GND.
Dimming pulse input.
When the slave mode is selected, the pulse width of the all segment
output are controlled by a input pulse width of DIM IN.
Connect this pin to the master side DIM OUT pin at the slave mode.
When the master mode is selected, the input level of this pin is
ignored and the pulse width of the all grids and segment outputs are
controlled by a built-in 10-bit dimming circuit.
DIM IN
15
18
I
Connect this pin to VDD or L-GND at the master mode.
6/19
¡ Semiconductor
MSM9210
Pin
Symbol
Type
Description
Synchronous signal input.
QFP56
QFP64
When the slave mode is selected, connect these pins to the master
side SYNC OUT 1, and 2 pins.
SYNC IN 1, 2
16, 17
19, 20
I
When the master mode is selected, the input level of these pins are ignored.
Connect these pins to VDD or L-GND at the master mode.
Dimming pulse output.
DIM OUT
SYNC OUT 1, 2
OSC0
28
26, 27
23
31
29, 30
26
O
O
I
Connect this pin to the slave side DIM IN pin.
Synchronous signal output.
Connect these pins to the slave side SYNC IN 1, and 2 pins.
RC oscillator connecting pins.
OSC0
Oscillation frequency depends on
display tubes to be used.
For details, refer to ELECTRICAL
CHARACTERISTICS.
R
C
OSC1
OSC1
22
25
O
ABSOLUTE MAXIMUM RATING
Parameter
Driver Supply Voltage
Logic Supply Voltage
Input Voltage
Symbol
VDISP
VDD
VIN
Condition
Ratings
Unit
V
—
–0.3 to +20
—
–0.3 to +6.5
–0.3 to VDD+0.3
360
V
—
V
Power Dissipation
Storage Temperature
PD
Ta≥25°C
mW
°C
TSTG
IO1
—
SEG1 to 22
–55 to +150
–10.0 to +2.0
–20.0 to +2.0
–10.0 to +20.0
–2.0 to +2.0
mA
mA
mA
mA
IO2
SEG23 to 32
Output Current
IO3
GRID1 to 3
IO4
DIM OUT, SYNC OUT1, SYNC OUT2
RECOMMENDED OPERATING CONDITIONS
Parameter
Driver Supply Voltage
Logic Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Clock Frequency
Symbol
VDISP
VDD
Condition
Min.
8.0
Typ.
13.0
5.0
—
Max.
18.0
5.5
Unit
V
—
—
4.5
V
VIH
All inputs except OSC0
0.8VDD
—
—
V
VIL
All inputs except OSC0
—
0.2VDD
1.0
V
fC
—
—
—
—
MHz
°C
Operating Temperature
TOP
–40
—
+85
7/19
¡ Semiconductor
MSM9210
When a 1/2 duty VFD tube is used
Parameter
Oscillation Frequency
Frame Frequency
Symbol
fOSC
Condition
Min.
1.0
Typ.
1.5
Max.
Unit
MHz
Hz
R=8.2KW 5ꢀ, C=22pF 5ꢀ
R=8.2KW 5ꢀ, C=22pF 5ꢀ
2.0
fFR
122
183
244
When a 1/3 duty VFD tube is used
Parameter
Oscillation Frequency
Frame Frequency
Symbol
fOSC
Condition
Min.
1.5
Typ.
2.25
183
Max.
3.0
Unit
MHz
Hz
R=6.2KW 5ꢀ, C=22pF 5ꢀ
R=6.2KW 5ꢀ, C=22pF 5ꢀ
fFR
122
244
8/19
¡ Semiconductor
MSM9210
ELECTRICAL CHARACTERISTICS
DC Characteristics
Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Symbol Applied pin
Condition
—
Min.
0.8VDD
—
Max. Unit
VIH
VIL
*1)
*1)
—
0.2VDD
+1.0
+1.0
—
V
V
—
IIH
*1)
VIH=VDD
VIL=GND
–1.0
mA
mA
V
IIL
*1)
–1.0
VOH1
VOH2
VOH3
VOH4
VOL1
VOL2
VOL3
VOL4
IDISP
IDD
SEG1-22
SEG23-32
GRID1-3
*2)
VDISP–0.8
VDISP–0.8
VDISP–0.8
VDD–0.8
—
IOH1=–5mA
—
V
V
DISP=9.5V IOH2=–10mA
High Level Output Voltage
—
V
IOH3=–5mA
—
V
VDD=4.5V
IOH4=–200mA
IOL1=500mA
SEG1-22
SEG23-32
GRID1-3
*2)
2.0
V
—
2.0
V
VDISP=9.5V IOL2=500mA
Low Level Output Voltage
Supply Current
—
2.0
V
IOL3=10mA
—
0.8
V
VDD=4.5V
IOL4=200mA
VDISP
fOSC=3.0MHz, no load
fOSC=3.0MHz, no load
—
100
5.0
mA
mA
VDD
—
*1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI
*2) DIM OUT, SYNC OUT 1, SYNC OUT 2
9/19
¡ Semiconductor
MSM9210
AC Characteristics
Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V
Parameter
Clock Frequency
Clock Pulse Width
Data Setup Time
Data Hold Time
CS Off Time
Symbol
fC
Condition
Min.
—
Max.
1.0
—
Unit
MHz
ns
—
—
—
—
—
tCW
400
400
400
20
tDS
—
ns
tDH
—
ns
tCSL
—
ms
CS Setup Time
(CS-Clock)
tCSS
tCSH
—
400
400
—
—
ns
ns
CS Hold Time
(Clock-CS)
—
—
CS Wait Time
tRSOFF
tR
400
—
—
2.0
2.0
100
—
ms
ms
ms
ms
ms
tR=20ꢀ to 80ꢀ
tF=80ꢀ to 20ꢀ
Mounted in a unit
Mounted in a unit, VDD=0.0V
Output Slew Rate Time
CL=100pF
tF
—
VDD Rise Time
VDD Off Time
tPRZ
tPOF
—
5.0
TIMING DIAGRAM
l Data Input Timing
–0.8VDD
–0.2VDD
tCSL
tCSS
CS
1/fC
tCSH
tCW
tCW
–0.8VDD
–0.2VDD
CLOCK
tDS
tDH
–0.8VDD
–0.2VDD
DATA IN
VALID
VALID
VALID
VALID
l Reset Timing
–0.8VDD
–0.0V
tPRZ
tRSOFF
tPOF
VDD
–0.8VDD
–0.0V
CS
l Driver Output Timing
–0.8VDISP
–0.2VDISP
tR
tF
tR
SEG1-32, GRID1-3
10/19
¡ Semiconductor
MSM9210
l Output Timing (Duplex Operation) *1bit time=4/f
OSC
(The dimming data is 1016/1024 at the master mode)
2048bit times (1 display cycle)
VDISP
1016bit times
1016bit times
8bit times
GRID1
D-GND
8bit times
1016bit times
8bit times
VDISP
GRID2
GRID3
D-GND
VDISP
D-GND
VDISP
3bit times
1019bit times
5bit times
5bit times
5bit times
5bit times
5bit times
1019bit times
5bit times
1019bit times
5bit times
SEG1-32
D-GND
VDD
1019bit times
1019bit times
1029bit times
1019bit times
5bit times
1019bit times
5bit times
DIM OUT
L-GND
VDD
1029bit times
5bit times
1019bit times
5bit times
SYNC OUT1
SYNC OUT2
L-GND
VDD
5bit times
1019bit times
1029bit times
L-GND
l Output Timing (Triplex Operation) *1bit time=4/f
OSC
(The dimming data is 1016/1024 at the master mode)
3072bit times (1 display cycle)
VDISP
1016bit times
GRID1
D-GND
VDISP
8bit times
1016bit times
8bit times
GRID2
GRID3
D-GND
VDISP
8bit times
1016bit times
5bit times
D-GND
VDISP
3bit times
1019bit times
5bit times
5bit times
5bit times
5bit times
1019bit times
5bit times
1019bit times
5bit times
SEG1-32
D-GND
VDD
1019bit times
1019bit times
1029bit times
1019bit times
5bit times
1019bit times
5bit times
DIM OUT
SYNC OUT1
L-GND
VDD
1029bit times
5bit times
1019bit times
5bit times
L-GND
VDD
5bit times
1019bit times
1019bit times
SYNC OUT2
L-GND
11/19
¡ Semiconductor
MSM9210
FUNCTIONAL DESCRIPTION
Power-on Reset
When power is turned on, MSM9210 is initialized by the internal power-on reset circuit.
The status of the internal circuit after initialization is as follows:
• The contents of the shift registers and latches are set to "0".
• The digital dimming duty cycle is set to "0".
• All segment outputs are set to Low level.
• All grid outputs are set to High level.
Data Transfer Method
Data can be transferred between the rising edge and the next falling edge of chip select input.
The mode data, segment data and dimming data are written by a serial transfer method. The
serial data is input to the shift register at the rising edge of a shift clock pulse.
The mode data (M0 to M2) must be transferred after the segment data and dimming data
succeedingly.
When the chip select input falls, an internal LOAD signal is automatically generated and data is
loaded to the latches.
Function Mode
Functionmodeisselectedbythemodedata(M0toM2). Therelationbetweenfunctionmodeand
mode data is as follows:
FUNCTION DATA
FUNCTION MODE
OPERATING MODE
M0
0
M1
0
M2
0
0
1
2
3
4
Segment Data for GRID1-3 Input
Segment Data for GRID1 Input
Segment Data for GRID2 Input
Segment Data for GRID3 Input
Digital Dimming Data Input
1
0
0
0
1
0
1
1
0
0
0
1
Segment Data Input [Function Mode: 0 to 3]
• MSM9210 receives the segment data when function mode 0 to 3 are selected.
• The same segment data is transferred to the 3 segment data latches corresponding to GRID 1
to 3 at the same time when the function mode 0 is selected.
• The segment data is transferred to only one segment data latch corresponding to the specified
GRID when the function mode is 1, 2 or 3 is selected.
• Segment output (SEG1to32) becomes High level (lightning) when the segment data (S1to S32)
is set to "1".
[Data Format]
Input Data
: 35 bits
Segment Data : 32 bits
Mode Data
:
3 bits
Bit
Input Data
1
2
3
4
29
30
31
32
33
34
35
S1 S2 S3 S4
Segment Data (32bits)
S29 S30 S31 S32 M0 M1 M2
Mode Data
(3bits)
12/19
¡ Semiconductor
MSM9210
[Bit correspondence between segment output and segment data]
SEG n
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16
SEG n
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32
Digital Dimming Data Input [Function Mode: 4]
• MSM9210 receives the digital dimming data when function mode 4 is selected.
• The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid.
• The 10-bit digital dimming data is input from LSB.
[Data Format]
Input Data
Digital Dimming Data: 10 bits
Mode Data : 3 bits
: 13 bits
Bit
Input Data
1
2
3
4
5
6
7
8
9
10
11
12
13
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 M0 M1 M2
LSB
MSB
Digital Dimming Data (10bits)
Dimming Data
Mode Data
(3bits)
(LSB)
(MSB)
Duty Cycle
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1024
1/1024
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1015/1024
1016/1024
1016/1024
1
1
1
1
1
1
1
1
1
1
1016/1024
Master Mode
Master Mode is selected when M/S pin is set at High level. The master mode operation is as
follows:
• The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be
connected to L-GND or V
.
DD
• The pulse width of GRID1 to 3 and SEG1 to 32 are controlled by the internal digital dimming
circuit.
• The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing
generator.
13/19
¡ Semiconductor
MSM9210
Slave Mode
Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows:
• The internal dimming circuit is ignored.
• The pulse width of SEG1 to 32 are controlled by the pulse width of DIM IN signal.
• The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2
signals.
• The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC
OUT1 and SYNC OUT2 are set at Low level.
[Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] [Correspondence between DIM IN and SEG1 to 32]
SYNC IN 1
SYNC IN 2
Segment Latch
No
GRID
No
DIM IN
SEG1 to 32
Low
0
1
0
1
0
0
1
1
0
1
Latch1
GRID1
GRID2
GRID3
High
Latch2
Note: Low: Lights OFF
High: Lights ON
Latch3
14/19
VDD
VDISP
VDD
VDISP
MSM9210
(MASTER)
MSM9210
(SLAVE)
SEG1
SEG1
VDD
SEG32
SEG32
VDD
VDISP
DUP/TRI
M/S
DUP/TRI
GRID1
GRID1
VDD
M/S
GRID2
GRID3
GRID2
GRID3
GND
S1 S2 S3
S62 S63 S64
SYNC IN 2
SYNC IN 1
DIM IN
CS
DATA IN
CLOCK
OSC 1
SYNC OUT 2
SYNC OUT 1
DIM OUT
SYNC IN 2
SYNC IN 1
DIM IN
CS
DATA IN
CLOCK
OSC 1
SYNC OUT 2
SYNC OUT 1
DIM OUT
G1
G2
Duplex VF Tube
GND
Ef
R
R
C
OSC 0
L-GND
OSC 0
L-GND
C
D-GND
D-GND
GND
GND
GND
VDD
MSM9210
(MASTER)
VDISP
VDD
MSM9210
(SLAVE)
VDISP
SEG1
SEG1
VDD
SEG32
SEG32
VDISP
M/S
GRID1
M/S
GRID1
VDD
DUP/TRI
DUP/TRI
GRID2
GRID3
GRID2
GRID3
S1 S2 S3
S62 S63 S64
GND
SYNC IN 2
SYNC IN 1
DIM IN
CS
DATA IN
CLOCK
OSC 1
SYNC OUT 2
SYNC OUT 1
DIM OUT
SYNC IN 2
SYNC IN 1
DIM IN
CS
DATA IN
CLOCK
OSC 1
SYNC OUT 2
SYNC OUT 1
DIM OUT
G1
G2
G3
Triplex VF Tube
GND
Ef
R
R
C
OSC 0
L-GND
OSC 0
L-GND
C
D-GND
D-GND
GND
GND
GND
¡ Semiconductor
MSM9210
NOTES ON TURNING POWER ON/OFF
• Connect L-GND and D-GND externally to be an equal potential voltage.
• To avoid wrong operations, turn on the driver power supply after turning on the logic power
supply. Conversely, turn off the logic power supply after tuning off the driver power supply.
[Voltage]
VDISP
VDD
[Time]
17/19
¡ Semiconductor
MSM9210
PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.43 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/19
¡ Semiconductor
MSM9210
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
19/19
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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