MSM9223GS-BK [OKI]
Vacuum Fluorescent Driver, 30-Segment, CMOS, PQFP64, 14 X 20 MM, 1 MM PITCH, PLASTIC, QFP-64;
| 型号： | MSM9223GS-BK |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Vacuum Fluorescent Driver, 30-Segment, CMOS, PQFP64, 14 X 20 MM, 1 MM PITCH, PLASTIC, QFP-64 驱动 接口集成电路 |
| 文件： | 总25页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2C0044-19-96
This version: Sep. 1999
Previous version: Aug. 1999
¡ Semiconductor
MSM9223
27-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan
GENERAL DESCRIPTION
The MSM9223 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent
display tube. It conststs of 27-segment driver outputs and 3-grid pre-driver outputs, so that it
can drive directly up to 81-segment VFD.
MSM9223featuresadigitaldimmingfunction, a6-chADC, a5¥5keyscancircuitandanencoder
type switch interface.
MSM9223 provides an interface with a microcontroller only by three signal lines: DATA I/O,
CLOCK and CS.
FEATURES
• Supply voltage (V
)
DD
: 8 to 18.5V (Built-in 5V regulator for logic)
• Duplex/Triplex selectable
• Applicable VFD tube
: 2 Grids ¥ 27 Anodes VFD tube
: 3 Grids ¥ 27 Anodes VFD tube
• 27-segment driver outputs
• 3-grid pre-driver outputs
: I =–5mA at V =V –0.8V (SEG1 to 19)
OH
OH
DD
I
=–10mA at V =V –0.8V (SEG20 to 27)
OH
OH DD
: I =10mA at V =2V
OL
OL
• Built-in digital dimming circuit (10-bit resolution)
• Built-in 6-ch A/D converter
• Built-in 5 ¥ 5 keyscan circuit
• Interface circuit for an encoder type rotary switch
• Built-in oscillation circuit (external R and C)
• Built-in Power-On-Reset circuit
• Package:
64-pin plastic QFP (QFP64-P-1420-1.00-BK)
Product name: MSM9223GS-BK
1/24
¡ Semiconductor
MSM9223
BLOCK DIAGRAM
SEG1
SEG27
GRID1 GRID2 GRID3
D-GND
VDD
27 Segment Driver
Out1-27
3 Grid pre Driver
VCC
(5V)
VREG
(5V)
5V
Regulator
&
POR
Power On
L-GND
81 to 27 Segment Control
in1-27
Reset
in1-27
in1-27
0H
7H
Out1-27
Segment Latch
Out1-27
Segment Latch
Out1-27
Segment Latch
1H
0H
2H
0H
3H
0H
Mode Select
in1-3
1
2
3
POR
POR
POR
POR
in1-27
in1-27
in1-27
CS
CLOCK
Out1-3
3bit Shift Register
Out1-27
27bit Shift Register
in1-10
Dimming Latch
Out1-10
4H
Control
POR
DATA I/O
POR
POR
10bit Digital
Dimming
OSCO
OSC
POR
DIM OUT
SYNC OUT1
SYNC OUT2
Timing Generator
DUP/TRI
6ch, 8bit
A/D Converter
7H 5H
6H
INT
5 ¥ 5 Key Scan and Encoder Switch Interface
CH1
CH6
COL1
COL5
ROW1
ROW5 A1 B1
2/24
¡ Semiconductor
MSM9223
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
51
50
VDD
SEG25
SEG26
SEG27
GRID1
GRID2
GRID3
D-GND
ROW1
VDD
SEG11
49 SEG10
48 SEG9
47 SEG8
46 SEG7
45 SEG6
44 SEG5
43 SEG4
42 SEG3
41 SEG2
40 SEG1
39 CH6
38 CH5
37 CH4
36 CH3
35 CH2
34 CH1
33 VREG
ROW2 10
ROW3 11
12
13
14
ROW4
ROW5
COL1
COL2 15
COL3 16
COL4 17
COL5 18
NC 19
NC: No connection
64-pin Plastic QFP
3/24
¡ Semiconductor
MSM9223
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
Power supply pins.
Pin1 and pin51 should be connected externally.
1, 51
VDD
—
8
D-GND
L-GND
VCC
—
—
O
D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the
logic circuit. Pins 8 and 26 should be connected externally.
5V output pin for internal logic portion and external logic circuit.
Reference voltage (5V) output pin for A/D converter.
Segment (anode) signal output pins for a VFD tube.
These pins can be directly connected to the VFD tube. External circuit is not required.
IOH£–5 mA
26
24
33
VREG
O
40 to 50,
52 to 59
SEG1 to 19
SEG20 to 27
GRID1 to 3
O
O
O
Segment (anode) signal output pins for a VFD tube.
These pins can be directly connected to the VFD tube. External circuit is not required.
IOH£–10 mA
60 to 64,
2 to 4
Inverted Grid signal output pins.
5, 6, 7
For pre-driver, the external circuit is requiend.
IOL£10 mA
Chip Select input pin.
29
28
27
CS
I
I
Data input/output operation is valid when this pin is set at a High level.
Serial clock input pin.
CLOCK
DATA I/O
Data is input and/or output through the DATA I/O pin at the rising edge of the serial clock.
Serial data input/output pin.
I/O
Data is input to / comes out from the shift register at the rising edge of the serial clock.
Interrupt signal output to microcontroller. When any key of key matrix is pressed
or released, key scanning is started. After the completion of the one cycle, this pin
goes to high level and keeps the high level until keyscan stop mode is selected.
Duplex/Triplex operation select input pin.
22
23
INT
O
I
Duplex (1/2 duty) operation is selected when this pin is set at a VCC level.
Triplex (1/3 duty) operation is selected when this pin is set at a GND level.
DUP/TRI
34 to 39
20, 21
CH1 to 6
A1, B1
I
Analog voltage input pin for the 8-bit A/D converter.
Input pin for the encoder type rotary switch. Each input has chattering
absorption function of 620ns typical.
O
Return inputs from the key matrix.
These pins are active low. When key matrix are in the inactive sate, these
pins are at high level through the internal pull-up resistors. All the inputs do
not have the cahttering absorption function for the keyscans.
Key switch scanning outputs.
14 to 18
9 to 13
COL1 to 5
ROW1 to 5
I
Normally low level is output through these pin. When any switch of key matrix
is depressed or released, key scanning is started and is continued until
keyscan stop mode is selected. When keyscan stop mode is selected, all
outputs of ROW1 to 5 go back to low level.
O
4/24
¡ Semiconductor
MSM9223
Pin
Symbol
Type
Description
Dimming pulse output.
32
DIM OUT
O
Connect this pin to the slave side DIM IN pin.
Synchronous signal input.
30, 31
25
SYNC OUT 1, 2
OSC0
O
Connect these pins to the SYNC IN1 and SYNC IN2 pins
of a slave side.
RC oscillator connecting pins.
C3
VCC
OSC0
Connect a resistor (R2) between the VCC and OSC0 pins,
and a capacitor (C2) between the OSC0 pin and the GND,
R2
C2
I/O
and a capacitor (C3) between the VCC and the GND. C3 is for VCC stabilization.
5/24
¡ Semiconductor
MSM9223
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
VDD
VIN
Condition
Rating
–0.3 to +20
–0.3 to +6.0
590
Unit
V
—
Input Voltage
—
V
Power Dissipation
Storage Temperature
PD
Ta = 85°C
mW
°C
TSTG
IO1
—
SEG1 to 19
–55 to +150
–10.0 to +2.0
–20.0 to +2.0
–7.0 to +20.0
–2.0 to +2.0
mA
mA
mA
mA
IO2
SEG20 to 27
Output Current
IO3
GRID1 to 3
IO4
DIM OUT, SYNC OUT1, SYNC OUT2
RECOMMENDED OPERATING CONDITIONS
Parameter
Driver Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Clock Frequency
Symbol
VDD
VIH
Condition
—
Min.
8.0
Typ.
13.0
—
Max.
Unit
V
18.5
5.5
All inputs except OSC0
All inputs except OSC0
—
3.8
V
VIL
0.0
—
0.8
V
fC
—
—
1.0
MHz
MHz
Hz
Oscillation Frequency
fOSC
R2 = 10kW 5ꢀ, C2 = 27pF 5ꢀ
R2 = 10kW 5ꢀ 1/3 Duty
2.6
3.3
269
403
—
4.0
211
317
–40
325
488
+85
Frame Frequency
fFR
C2 = 27pF 5ꢀ
1/2 Duty
Hz
Operating Temperature
TOP
—
°C
6/24
¡ Semiconductor
MSM9223
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=–40 to +85°C, VDD=8.0 to 18.5V)
Parameter
High Level Input Voltage
Low Level Input Voltage
Symbol Applied pin
Condition
—
Min.
3.8
Max. Unit
VIH
VIL
*1)
*1)
5.5
0.8
V
V
—
0.0
IIH1
IIH2
IIL1
*2)
VIH=3.8V
VIH=3.8V
VIL=0.0V
VIL=0.0V
–5.0
–100
–5.0
–300
VDD–0.8
VDD–0.8
VDD–0.8
4.0
+5.0
–5.0
+5.0
–70
VDD
VDD
VDD
5.5
mA
mA
mA
mA
V
High Level Input Current
Low Level Input Current
*3)
*2)
IIL2
*3)
VOH1
SEG1 to 19
I
OH1=–5mA
VOH2 SEG20 to 27
V
IOH2=–10mA
IOH3=–5mA
IOH4=–200mA
Output Open
High Level Output Voltage
Low Level Output Voltage
VOH3
VOH4
VOL1
GRID1 to 3
V
VDD=9.5V
VDD=9.5V
V
*4)
4.5
5.5
V
SEG1 to 19
—
2.0
V
I
OL1=500mA
VOL2 SEG20 to 27
—
2.0
V
IOL2=500mA
IOL3=10mA
IOL4=300mA
VOL3
VOL4
IDD
GRID1 to 3
*5)
—
2.0
V
—
0.8
V
Supply Current
VDD
fOSC=3.3MHz, no load
—
10
mA
V
Supply Voltage for Logic
VL
VCC
C3=0.01mF 10ꢀ, IO=0 to –10mA
4.5
5.5
*1) CS, CLOCK, DATA I/O DUP/TRI, A1, B1, COL1 to 5
*2) CS, CLOCK, DATA I/O DUP/TRI, A1, B1
*3) COL1 to 5
*4) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2
*5) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2, ROW1 to 5
7/24
¡ Semiconductor
MSM9223
AC Characteristics
(Ta=–40 to +85°C, VDD=8.0 to 18.5V)
Parameter
Clock Frequency
Clock Pulse Width
Data Setup Time
Data Hold Time
CS Off Time
Symbol
fC
Condition
Min.
—
Max.
1.0
—
Unit
MHz
ns
—
tCW
—
400
400
400
20
tDS
—
—
ns
tDH
—
—
ns
tCSL
R2=10kW 5ꢀ, C2=27pF 5ꢀ
—
ms
CS Setup Time
(CS-Clock)
tCSS
tCSH
tPD
—
—
—
400
400
—
—
—
ns
ns
ms
CS Hold Time
(Clock-CS)
DATA Output Delay Time
(Clock-DATA I/O)
1.0
tR
tF
tR=20ꢀ to 80ꢀ
CL=100pF
—
—
4.0
4.0
100
—
ms
ms
ms
ms
ms
Output Slew Rate Time
tF=80ꢀ to 20ꢀ
VDD Rise Time
VDD Off Time
CS Wait Time
tPRZ
tPOF
tRSOFF
Mounted in a unit
Mounted in a unit, VDD=0.0V
—
—
5.0
400
—
8/24
¡ Semiconductor
MSM9223
TIMING DIAGRAM
Data Input Timing
–3.8V
–0.8V
tCSL
tCSS
CS
1/fC
tCW
tCSH
tCW
–3.8V
–0.8V
CLOCK
tDS
tDH
–3.8V
–0.8V
DATA I/O
(INPUT)
VALID
VALID
VALID
VALID
Data Output Timing
–3.8V
–0.8V
tCSS
CS
tCSH
–3.8V
–0.8V
CLOCK
tPD
–3.8V
–0.8V
DATA I/O
(OUTPUT)
Reset Timing
–0.8VDD
–0.0V
tPRZ
tRSOFF
tPOF
VDD
–3.8V
–0.0V
CS
Driver Output Timing
–0.8VDD
–0.2VDD
tR
tF
SEG1-27, GRID1-3
9/24
¡ Semiconductor
MSM9223
A/D Converter Characteristics
(Ta = –40 to +85°C, VDD = 8.0 to 18.0 V)
Parameter
Condition
Min.
—
Typ.
—
Max.
1
Unit
LSB
V
A/D Conversion Accuracy
—
Reference Voltage (VREG
Output Current
)
—
4.5
5.0
—
5.5
—
—
–10
VREG
394
mA
V
Input Voltage Range
—
GND
256
—
Conversion Time/Channel
R2 = 10kW 5ꢀ, C2 = 27pF 5ꢀ
310
ms
Keyscan Characteristics
(Ta = –40 to +85°C, VDD = 8.0 to 18.0 V)
Parameter
Keyscan Cycle Time
Keyscan Pulse Width
Condition
Min.
160
32
Typ.
194
39
Max.
246
49
Unit
ms
R2 = 10kW 5ꢀ, C2 = 27pF 5ꢀ
R2 = 10kW 5ꢀ, C2 = 27pF 5ꢀ
ms
Keyscan Timing
Keyscan Cycle Time
ROW1
ROW2
ROW3
ROW4
ROW5
Keyscan Pulse
Width
10/24
¡ Semiconductor
MSM9223
Output Timing (Duplex Operation)
*1bit time=4/f
OSC
(The dimming data is 1016/1024)
2048bit times (1 display cycle)
VDD
1016bit times
1016bit times
8bit times
GRID1
GRID2
GRID3
D-GND
8bit times
1016bit times
8bit times
VDD
D-GND
VDD
D-GND
3bit times
5bit times
5bit times
5bit times
VDD
1019bit times
1019bit times
1019bit times
1029bit times
1019bit times
5bit times
1019bit times
5bit times
SEG1-27
D-GND
5 V
5bit times
5bit times
1019bit times
5bit times
1019bit times
5bit times
DIM OUT
L-GND
5 V
1029bit times
5bit times
1019bit times
5bit times
SYNC OUT1
SYNC OUT2
L-GND
5 V
5bit times
1019bit times
1029bit times
L-GND
Output Timing (Triplex Operation)
*1bit time=4/f
OSC
(The dimming data is 1016/1024)
3072bit times (1 display cycle)
VDD
1016bit times
GRID1
D-GND
VDD
8bit times
8bit times
1016bit times
GRID2
D-GND
VDD
8bit times
1016bit times
5bit times
GRID3
D-GND
VDD
3bit times
5bit times
5bit times
5bit times
5bit times
1019bit times
SEG1-27
1019bit times
5bit times
1019bit times
5bit times
D-GND
5 V
1019bit times
DIM OUT
1019bit times
5bit times
1019bit times
5bit times
L-GND
5 V
1019bit times
SYNC OUT1
1029bit times
5bit times
1019bit times
5bit times
L-GND
5 V
5bit times
1029bit times
SYNC OUT2
1019bit times
1019bit times
L-GND
11/24
¡ Semiconductor
MSM9223
Output Timing (Duplex Operation)
*1bit time=4/f
OSC
(The dimming data is 64/1024)
2048bit times (1 display cycle)
VDD
64bit times
64bit times
GRID1
GRID2
GRID3
D-GND
VDD
960bit times
960bit times
960bit times
64bit times
D-GND
VDD
D-GND
VDD
3bit times 957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
67bit times
67bit times
67bit times
1981bit times
67bit times
67bit times
67bit times
67bit times
1981bit times
SEG1-27
D-GND
5 V
957bit times
67bit times
DIM OUT
L-GND
5 V
957bit times
67bit times
SYNC OUT1
SYNC OUT2
L-GND
5 V
957bit times
1981bit times
L-GND
Output Timing (Triplex Operation)
*1bit time=4/f
OSC
(The dimming data is 64/1024)
3072bit times (1 display cycle)
VDD
64bit times
GRID1
D-GND
VDD
960bit times
960bit times
64bit times
GRID2
D-GND
VDD
960bit times
64bit times
GRID3
D-GND
VDD
3bit times 957bit times
957bit times
957bit times
957bit times
957bit times
957bit times
67bit times
SEG1-27
67bit times
67bit times
67bit times
67bit times
67bit times
67bit times
D-GND
5 V
957bit times
957bit times
957bit times
957bit times
67bit times
DIM OUT
L-GND
5 V
957bit times
67bit times
1981bit times
67bit times
SYNC OUT1
SYNC OUT2
L-GND
5 V
957bit times
1981bit times
L-GND
12/24
¡ Semiconductor
MSM9223
FUNCTIONAL DESCRIPTION
Power-on Reset
When power is turned on, MSM9223 is initialized by the internal power-on reset circuit.
The status of the internal circuit after initialization is as follows:
• The contents of the shift registers and latches are set to "0".
• The digital dimming duty cycle is set to "0".
• All segment outputs are set to Low level.
• All grid outputs are set to High level.
• All the ROW outputs are set to Low level.
• INT output is set to Low level.
Data Input and Output
Data input and output through the DATA-I/O pin is valid only when the CS pin is set at a High
level.
The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial
clock. The data is automatically loaded to the latches when the CS pin is set at a Low level.
10-bit dimming data (D1 to D10) and 27-bit segment data (S1 to S27) are used for inputting of
dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be
sent after each of these data succeddingly.
The output data from the DATA I/O pin is output from the shift register at the rising edge of the
serial clock.
MSM9223 outputs 48-bit (6ch ¥ 8bits) A/D data (A11 to A68) and 29-bit key data (S11 to S55, R1
and Q1 to Q3). To receive these data, the mode data (M0 to M2) mast be sent first and then CS
must be set once to Low level and set again to High level.
Then inputting serial clocks, these data are output from the DATA I/O pin.
When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin.
To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer,
the key scanning is stopped immediately.
Mode Data
MSM9223 has the seven function modes. The function mode is selected by the mode data (M0 to
M2). The relation between function mode and mode data (M0 to M2) is as follows:
FUNCTION DATA
FUNCTION MODE
OPERATING MODE
M0
0
M1
0
M2
0
0
1
2
3
4
5
6
7
Segment Data for GRID1-3 Input
Segment Data for GRID1 Input
Segment Data for GRID2 Input
Segment Data for GRID3 Input
Digital Dimming Data Input
Keyscan Stop
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
Switch Data Output
0
1
1
A/D Data Output
1
1
1
13/24
¡ Semiconductor
MSM9223
Segment Data Input [Function Mode: 0 to 3]
• MSM9223 receives the segment data when function mode 0 to 3 are selected.
• The same segment data is transferred to the 3 segment data latch correspond to GRID 1 to 3 at
the same time when the function mode 0 is selected.
• The segment data is transferred to only one segment data latch that is selected by mode data,
when the function mode is 1, 2 or 3 is selected.
• Segmentoutput(SEG1to27)becomesHighlevelwhenthesegmentdata(S1to27)isHighlevel.
[Data Format]
Input Data
: 30 bits
Segment Data : 27 bits
Mode Data
:
3 bits
Bit
Input Data
1
2
3
4
24
25
26
27
28
29
30
S1 S2 S3 S4
Segment Data (27bits)
S24 S25 S26 S27 M0 M1 M2
Mode Data
(3bits)
[Bit correspondence between segment output and segment data]
SEG n 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16
SEG n
17 18 19 20 21 22 23 24 25 26 27
Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27
14/24
¡ Semiconductor
MSM9223
Digital Dimming Data Input [Function Mode: 4]
• MSM9223 receives the digital dimming data when function mode 4 is selected.
• The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid.
• The 10-bit digital dimming data is input from LSB.
[Data Format]
Input Data
Digital Dimming Data: 10 bits
Mode Data : 3 bits
: 13 bits
Bit
Input Data
1
2
3
4
5
6
7
8
9
10
11
12
13
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 M0 M1 M2
LSB
MSB
Digital Dimming Data (10bits)
Dimming Data
Mode Data
(3bits)
(LSB)
(MSB)
Duty Cycle
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1024
1/1024
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1015/1024
1016/1024
1016/1024
1
1
1
1
1
1
1
1
1
1
1016/1024
15/24
¡ Semiconductor
MSM9223
Keyscan Stop [Function Mode: 5]
• MSM9223 stops a key scanning when function mode 5 are selected.
• To select this mode, the only mode data (M0 to M2) is needed.
• The actual time lag range between receipt of the keyscan stop command and the ceasing of
scanning is 2.4ms to 3.6ms
[Input Data Format]
Input Data
Mode Data
: 3 bits
: 3 bits
Bit
Input Data
28
29
30
M0 M1 M2
Mode Data
(3bits)
Switch Data Output [Function Mode: 6]
• MSM9223 output the switch data when function mode 6 is selected.
• To select this mode, the only mode data (M0 to M2) is needed.
• When MSM9223 recieves this mode, the DATA I/O pin is changed to an output pin.
• 29-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the
clock.
• When the CS pin is set at the low level, the DATA I/O pin returns to an input pin.
• R1=0, implies Right rotation of the knob (Clockwise)
• R1=1, implies Left rotation of the knob (Counter Clockwise)
• Contact Count bits are Q1 (LSB) to Q3 (MSB)
[Input Data Format]
Input Data
Mode Data
: 3 bits
: 3 bits
Bit
28
29
30
Input Data
M0 M1 M2
Mode Data
(3bits)
[Output Data Format]
Output Data
: 29 bits
5¥5 push swithc Data : 25 bits
Encoder switch Data : 4 bits
Bit
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Output Data S11 S12 S13 S14 S15 S21 S22 S23 S24 S25 S31 S32 S33 S34 S35
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29
Output Data S41 S42 S43 S44 S45 S51 S52 S53 S54 S55 R1 Q1 Q2 Q3
Sij : i=ROW1 to 5, j=COL1 to 5
Sij=1 : Switch ON
Sij=0 : Switch OFF
16/24
¡ Semiconductor
MSM9223
A/D Data Output [Function Mode: 7]
• MSM9223 output the A/D data when function mode 7 is selected.
• To select this mode, the only mode data (M0 to M2) is needed.
• When MSM9223 recieves this mode, the DATA I/O pin is changed to an output pin.
• 48-bit A/D data come out from the DATA I/O pin synchronizeing with the rise edge of the
clock.
• When the CS pin is set at the low level, the DATA I/O pin returns to an input pin.
[Input Data Format]
Input Data
Mode Data
: 3 bits
: 3 bits
Bit
28
29
30
Input Data
M0 M1 M2
Mode Data
(3bits)
[Output Data Format]
Output Data
: 48 bits
: 48 bits
A/D Data
Bit
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
A11 A12 A13 A14 A15 A16 A17 A18 A21 A22 A23 A24 A25 A26 A27 A28
Output Data
(LSB)
(MSB)(LSB)
(MSB)
A/D
Bit
CH1
CH2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A31 A32 A33 A34 A35 A36 A37 A38 A41 A42 A43 A44 A45 A46 A47 A48
Output Data
(LSB)
(MSB)(LSB)
(MSB)
A/D
Bit
CH3
CH4
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
A51 A52 A53 A54 A55 A56 A57 A58 A61 A62 A63 A64 A65 A66 A67 A68
Output Data
A/D
(LSB)
(MSB)(LSB)
(MSB)
CH5
CH6
17/24
¡ Semiconductor
MSM9223
The rotary encoder switch function.
As figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt
generation, Up/down counter, Direction latch and Parallel-in serial-out shift register.
A
B
Phase Detection
UP
DOWN
Interrupt
Generation
for INT
UP/DOWN Counter
Direction Latch
R1
Q3 Q2 Q1
P-in/S-out Shift Registor
Output data
Fig.1 The Rotary Encoder Switch Circuit
1) Phase detection
1-1) Clockwise
The input A and B have a chattering absorption circuit of 620ns (typ.). When signal A and B input
as fig. 2, the phase detection circuit outputs UP signal after the chattering absorption period. At
this time, the output INT also goes to high level, so this signal can be used as an interrupt. The
INT stays High level until the switch data-output mode is selected.
A
chattering absorption time
B
UP (internal)
INT
Fig.2 The Input and Output Timing in Case of Clockwise.
18/24
¡ Semiconductor
MSM9223
1-2) counter clockwise
When signal A and B input as fig. 3, the phase detection circuit outputs Down signal after the
chattering absorption period. At this time, the output INT also goes to High level. The INT stays
High level until the switch data-output mode is selected.
A
chattering absorption time
B
DOWN (internal)
INT
Fig.3 The Input and Output Timing in Case of Counter Clockwise.
2) UP/DOWN COUNTER
WhentheUP/DOWNCOUNTERisinputUP, itcountsupandwhenitisinputDOWN, itcounts
down.
But if overcounte of "111" occurs the UP/DOWN COUNTER stays "111".
A
B
Q3, Q2, Q1
001
010
011
100
101
110
111
111
Fig.4
3) Direction latch
When the Direction latch is input DOWN the output R goes "1". But if the UP pulse is input and
the counts value change to plus value, the output R goes to "0".
A
B
R1
Q1, Q2, Q3
100 010
100
000
100
010
Fig.5
19/24
¡ Semiconductor
MSM9223
4) P-in/S-out shift resistor
When the switch data output mode is selected and SC goes L, all the key data send to the shift
resistor, and the up/down counter is reset and the INT signal goes "L".
CS
C1 C2 C3 C4 C5 C1 C2 C3 C4 C5
ROW1 ROW2
C1 C2 C3 C4 C5 R1 Q1 Q2 Q3
ROW5 Rotary
Data I/O
CLOCK
INT
When CS goes L, the up/down counter is reset and the INT goes "L".
Fig.6
20/24
¡ Semiconductor
MSM9223
Keyscan
Keyscanning is started only when depression or release of any key is detected in order to
minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan
stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion
of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be
used as an interrupt signal.
[Keyscan Timing]
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
1 Cycle
INT
Depress/Release
Keyscan stop mode
is selected.
Note: Keyscanning cannot be stopped by selecting the keyscan stop mode only once if:
- keyscanning is started after depression or release of any key is detected, and then
- a key is depressed or released again before the keyscan stop mode is selected.
To stop keyscanning, it is required to select the keyscan stop mode once again.
Depress
Depress
Release
Keyscan
Keyscan
MODE5
INT
CS
MODE5
MODE5 : Keyscan stop
MODE5
21/24
VCC
VDD
VDD
VDISP
MSM9223
MSM9210
(SLAVE)
SEG1
SEG1
SEG27
SEG32
VDISP
DUP/TRI
M/S
DUP/TRI
GRID1
GRID1
VREG
GRID2
GRID3
GRID2
GRID3
GND
S1 S2 S3
S57 S58 S59
CH1 to 6
G1
G2
Duplex VFD Tube
GND
5 ¥ 5
Key matrix
ROW1 to 5
COL1 to 5
Ef
SYNC OUT 2
SYNC OUT 1
DIM OUT
SYNC IN 2
SYNC IN 1
DIM IN
CS
SYNC OUT 2
SYNC OUT 1
DIM OUT
GND
CS
DATA I/O
CLOCK
VCC
DATA IN
CLOCK
OSC 1
OSC0
OSC 0
L-GND
L-GND
GND
GND
VCC
VDD
VDD
MSM9210
(SLAVE)
VDISP
MSM9223
SEG1
SEG1
SEG27
SEG32
VDISP
VREG
CH1 to 6
GRID1
DUP/TRI
M/S
GRID1
GRID2
GRID3
GRID2
GRID3
S1 S2 S3
S57 S58 S59
GND
G1
G2
G3
GND
5 ¥ 5
Key matrix
Triplex VFD Tube
ROW1 to 5
COL1 to 5
Ef
SYNC OUT 2
SYNC OUT 1
DIM OUT
SYNC IN 2
SYNC IN 1
DIM IN
CS
SYNC OUT 2
SYNC OUT 1
DIM OUT
DUP/TRI
GND
CS
DATA I/O
CLOCK
VCC
DATA IN
CLOCK
OSC 1
OSC0
OSC 0
L-GND
L-GND
GND
GND
¡ Semiconductor
MSM9223
PACKAGE DIMENSIONS
(Unit : mm)
QFP64-P-1420-1.00-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.25 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
24/24
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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