MSM9405 [OKI]
IrDA Communication Controller; IrDA通信控制器
| 型号： | MSM9405 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | IrDA Communication Controller |
| 文件： | 总30页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2F0007-18-11
Preliminary
This version: Jan. 1998
¡ Semiconductor
MSM9405
IrDA Communication Controller
GENERAL DESCRIPTION
TheMSM9405isacommunicationcontrollerconformingtoIrDA, theinternationalstandardfor
infrared data communication. The device covers the IrDA physical specifications Ver.1.0 and
1.1.
Since the device performs some of the functions concerning communication protocol control,
the load on the software (firmware) for protocol control can be reduced. By combining the
device with another microcontroller and an infrared transceiver module, a device provided
with IrDA-compliant communication function can be configured.
FEATURES
• Data transfer rates
IrDA 1.0
IrDA 1.1
: 2400, 9600 bps; 19.2, 38.4, 57.6, 115.2 kbps
: 0.576, 1.152, 4 Mbps
• Detection/removal for beginning of frame and end of frame (IrDA 1.0, 1.1)
Insertion for beginning of frame and end of frame (IrDA 1.0, 1.1)
• Generation/check for CRC (IrDA 1.0, 1.1)
• Host interface
8-bit data bus
DMA transfer
Interrupt
: D -D
0 7
: DREQ, DACK, TC
: INTR
: A -A
0 3
Address
Control signal
: CS, RD, WR
• Infrared module control signal : SD
• Built-in 32-byte transmit-receive FIFOs
• Power down mode
• Built-in oscillator circuit
• Crystal oscillation frequency : 18.432 MHz (other than 4 Mbps data rate)
: 48 MHz (when 4 Mbps data rate used)
• Operating voltage (V
• Package:
)
: 2.7 to 3.6 V
DD
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name : MSM9405MB)
1/30
¡ Semiconductor
MSM9405
BLOCK DIAGRAM
Microcontroller I/F
2/30
¡ Semiconductor
MSM9405
PIN CONFIGURATION (TOP VIEW)
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
XIN
2
D7
XOUT
TEST
IRIN-A
IRIN-B
IROUT
SD
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
TC
9
D0
DREQ
DACK
PWDN
RESET
INTR
WR
10
A3
11
A2
12
A1
13
A0
14
CS
15
RD
GND
30-Pin Plastic SSOP
3/30
¡ Semiconductor
MSM9405
PIN DESCRIPTIONS
Function
Transceiver
Pin
Symbol Type
Description
Receive signal input A. (2.4 kbps to 4 Mbps)*1
27
26
IRIN-A
IRIN-B
I
I
Module Interface
Receive signal input B. (0.576 to 4 Mbps)
When connecting this device to a transceiver module,
tie this pin high or low if the number of the receive signal
output pins that the module has is only one.*1
Transmit signal output. Active high.
25
24
IROUT
SD
O
O
Transceiver module control signal output.
Becomes active when PWDN is set low.*1
This pin must be left open if connecting this device to a
transceiver module having no shutdown pins.
9-2
13-10
14
D0-D7
A0-A3
CS
I/O Data input-output.
Microcontroller
Interface
I
I
Register address inputs.
Chip select input. Active low.
When low, read and write signals are enabled.
Read signal input. Active low.
15
17
18
22
21
23
20
RD
WR
I
I
Write signal input. Active low.
INTR
DREQ
DACK
TC
O
O
I
Interrupt request signal output. Active low.
DMA Request signal output. *1
DMA acknowledge signal input. *1
DMA Controller
Interface
I
DMA transfer end signal input. Active low.
Power down control. Active low.
Others
PWDN
I
When set low, oscillation stops and the device enters power
down (low supply current) mode.
System reset input. Active low.
19
RESET
I
When set low, the internal registers are initialized.
28
30
29
1
TEST
XIN
O
I
Test. Must be left open.
Crystal connect.
Crystal connect.
Power supply.
XOUT
VDD
O
—
—
16
GND
Ground.
*1 Either active high or active low can be selected depending on the register setting.
4/30
¡ Semiconductor
MSM9405
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
VDD
Condition
Rating
–0.5 to +4.0
–0.5 to +6.0
230
Unit
V
—
—
—
—
Input Voltage
VI
V
Power Dissipation
Storage Temperature
PD
mW
°C
TSTG
–55 to +150
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
VDD
Condition
Range
Unit
V
—
—
2.7 to 3.6
Operating Temperature
Crystal Oscillation
Frequency
Top
–20 to +70
°C
fOSC
—
18.432 MHz 200 ppm or 48 MHz 100 ppm
—
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 3.6 V, Ta = –20 to +70°C)
Parameter
"H" Input Voltage
"L" Input Voltage
Input Leakage Current
"H" Input Voltage
"L" Input Voltage
Input Leakage Current
"H" Output Voltage
"L" Output Voltage
"H" Output Voltage
"L" Output Voltage
Supply Current
Symbol
VIH
Condition
—
Min. Typ. Max. Unit
Applicable Pin
IRIN-A, IRIN-B, PWDN
A0-A3, CS, RD, WR,
TC, RESET, DACK
2.2
0
—
—
—
—
—
—
—
—
—
—
—
5.5
0.8*1
1
V
mA
V
VIL
—
ILI
VI = VDD/0 V
—
—
2.2
0
VIH
5.5
0.8*1
VIL
—
ILI
VI = VDD/0 V
IO = –4 mA
IO = 4 mA
IO = –4 mA
IO = 4 mA
—
—
2.4
—
2.4
—
—
10 mA
D0-D7
VOH
VOL
VOH
VOL
IDD
—
V
V
0.4
—
IROUT, INTR, DREQ
0.4
20 mA
VDD
VDD
Supply Current
IDPN
When PWDN = "L"
—
—
— mA
(during Power Down)
*1 1.0 V when V = 3.0 to 3.6 V
DD
5/30
¡ Semiconductor
MSM9405
AC Characteristics
(VDD = 2.7 to 3.6 V, Ta = –20 to +70°C)
Parameter
Read Pulse Width
Symbol
trpw
trdd
Condition Min.
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.63
—
—
—
218
—
—
—
125
—
—
—
250
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
%
Note
*1
—
120/70
—
0
Read Data Delay Time
Read Data Hold Time
Read/Write Recovery Time
CS Setup Time
—
60
*2
trdh
—
—
20
*3
trcv
60
60
0
—
tcss
—
—
CS Hold Time
tcsh
—
—
Write Address Hold Time
Write Pulse Width
twah
twpw
twds
twdh
twas
tintr
—
0
—
—
120/70
60
–10
–10
—
60
10
—
–5
10
50
0
—
*1
Write Data Setup Time
Write Data Hold Time
Write Address Setup Time
Interrupt Clear Time
DACK Pulse Width
—
—
—
—
—
—
—
120/70
—
*1
*1
tdak
—
DACK Setup Time
tacs
—
—
DREQ Clear Time
tdrqr
tachr
tachw
ttcw
—
120/70
—
DACK Hold Time (during Read)
DACK Hold Time (during Write)
TC Pulse Width
—
—
—
—
—
TC Setup Time
ttcs
—
—
TC Hold Time
ttch
—
0
—
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
—
—
0.9
—
—
—
100
—
—
—
70
—
—
—
195
70
—
SIR Pulse Width
tspw
SDRT
tmpw
—
0.87
2.0
—
SIR Data Rate Tolerance
MIR Pulse width
%
ns
ns
%
—
0.1
0.2
—
MIR Data Rate Tolerance
FIR Single Pulse Width
FIR Data Rate Tolerance
MDRT
tfpw
%
ns
ns
%
165
0.01
0.1
—
FDRT
%
ns
ns
ns
FIR Double Pulse Width
Reset Pulse Width
tfdpw
trstw
285
—
*1 120 ns when crystal oscillation frequency = 18.432 MHz,
70 ns when crystal oscillation frequency = 48 MHz
*2 That which occurs latest of the following is to be used for the data delay time (t ) :
rdd
thechangeofthestateofA -A , thechangefromCS hightolow, andthechangefrom
0
3
RD high to low.
*3 That which occurs first of the following is to be used for the read data hold time (t ) :
rdh
thechangeofthestateofA -A , thechangefromCS lowtohigh, andthechangefrom
0
3
RD low to high.
6/30
¡ Semiconductor
MSM9405
• Read timing
trdd
trpw
trpw
trpw
trdh
CS
trdd
trdh
A0-A3
trcv
RD
trdd
trdh
D0-D7
tintr
INTR
7/30
¡ Semiconductor
MSM9405
• Write timing
tcsh
tcss
CS
twas
twah
A0-A3
twpw
trcv
WR
twds
twdh
D0-D7
tintr
INTR
8/30
¡ Semiconductor
MSM9405
• DMAC access timing 1
DMA_EN = "1", DMA_SL1 = "0", DMA_SL0 = "0"
MemoryÆM9405
CS
tdrqr
DREQ
(Active low)
tdak
trcv
DACK
trpw
trcv
RD
twds
twdh
D0-D7
M9405ÆMemory
CS
tdrqr
DREQ
(Active low)
trcv
tdak
trdh
DACK
WR
twpw
trcv
trdd
trdh
D0-D7
9/30
¡ Semiconductor
MSM9405
• DMAC access timing 2
DMA_EN = "1", DMA_SL1 = "0", DMA_SL0 = "1"
M9405ÆMemory
DREQ
(Active high)
tdrqr
DACK
tacs
trpw
tachr
RD
trcv
trdd
trdh
D0-D7
MemoryÆM9405
DREQ
(Active high)
tdrqr
DACK
tacs
twpw
tachw
WR
trcv
twds
twdh
D0-D7
WR
TC
ttcs
ttcw
ttch
10/30
¡ Semiconductor
MSM9405
• DMAC access timing 3
DMA_EN = "1", DMA_SL1 = "1", DMA_SL0 = "1" or "0"
M9405ÆMemory
tdrqr
DREQ
trdd
trpw
trdh
CS
trdd
trpw
trdh
A0-A3
trpw
RD
trdh
trdd
D0-D7
MemoryÆM9405
tdrqr
DREQ
tcsh
tcss
CS
twas
twah
A0-A3
twpw
WR
twds
twdh
D0-D7
11/30
¡ Semiconductor
MSM9405
• Infrared interface timing
tspw
SIR
tmpw
MIR
tfpw
tfdpw
FIR
• Reset timing
trstw
RESET
12/30
¡ Semiconductor
MSM9405
FUNCTIONAL DESCRIPTION
Modes
There are four modes provided by the MSM9405 for IrDA communication. Communication
with IrDA1.0 is in SIR mode or Extended-SIR mode, while communication with IrDA1.1 is in
MIR mode or FIR mode. In SIR mode, the MSM9405 has the necessary UART feature for IrDA
communication. The Extended-SIR mode is an original feature of the MSM9405. In this mode,
BOF/EOFinsertionandCRCcalculation/checkareperformedbytheMSM9405. Therefore, the
burden to the CPU can be reduced compared with IrDA1.0 communication using ordinary
UART. Moreover,theExtended-SIRmodeallowsDMAtransfereveninIrDA1.0communication.
In MIR mode, IrDA1.1 communication at up to 1.152 Mbps is possible. The FIR mode supports
4 Mbps transfer for IrDA1.1. Features of each mode are as follows:
MSM9405 Modes Comparison
CE insertion/ "0" insertion/
Preamble
mode
Transfer rate
BOF CRC EOF
removal
SW
removal
—
insertion/removal
SIR
Extended-SIR
MIR
2.4 to 115.2 kbps
2.4 to 115.2 kbps
0.576, 1.152 Mbps
4 Mbps
SW
HW
HW
HW
SW
HW
HW
HW
SW
HW
HW
HW
—
—
HW
—
—
HW
—
FIR
—
—
HW
CE : Control Escape Byte
SW : Software
HW : Hardware
Sending/Receiving Switching Method
Mode switching between sending and receiving is made using the TX_EN and RX_EN bits in
the ICR1 (Infrared Control Register 1). For sending, writing "1" in TX_EN puts the MSM9405
in the sending mode. Writing "1" in RX_EN puts the MSM9405 in the receiving mode. If "0" is
written to both TX_EN and RX_EN bits, the MSM9405 does not perform sending/receiving but
enters the idle state. Each register can be set even during the idle state. Data to be sent can be
written in advance to the FIFO during the idle state.
If "1" is written to both TX_EN and RX_EN, the MSM9405 is put in the receiving mode.
DMA Transfer
The MSM9405 allows DMA transfer. The DMA transfer mode covers the single transfer mode
and demand transfer mode, but not the block transfer mode. When a DMA controller with TC
output is used for sending, the DMA controller and MSM9405 automatically perform high-
speed transfer if the maximum frame length is specified for TFL and the transfer data length for
the TC counter of the DMA controller.
The timing when the DREQ signal is asserted is as follows:
During receiving, DREQ is asserted when data in the FIFO is at or above the receiving threshold
level or time-out occurs.
If all of the received data in the FIFO is read, DREQ is deasserted.
During sending, DREQ is asserted when data in the FIFO is lower than the sending threshold
level. Sent data is written and DREQ is deasserted when the FIFO becomes full or TXE_EV
occurs.
13/30
¡ Semiconductor
MSM9405
Time-out
The MSM9405 outputs an interrupt request or DMA request depending on the register setting
when the following time-out occurs even if the received data is below the receiving threshold
level:
The condition causing time-out in MIR or FIR mode is:
At least 1-byte data is in the receiving FIFO and 69.5 ms has passed after data is written from
the receiving shift register to the FIFO. During this period, the CPU or DMA controller does
not read the FIFO data.
The condition causing time-out in SIR or Extended SIR mode is:
At least 1-byte data is in the receiving FIFO and time (Tout) has passed after data is written
from the receiving shift register to the FIFO. During this period, the CPU or DMA controller
does not read the FIFO data.
Tout = 4 ¥ 8 ¥ 1/baud rate
baud rate: Transfer rate (2.4 to 115.2 kbps)
Register Map
The MSM9405 contains 14 registers, of which 13 are available. Each register can be selected with
theregisteraddressassignedfrom0hthroughCh. Varioussettingoptionsareprovidedforeach
register to allow optimum communication.
The registers are listed below. The register table is given on the next page.
A3-A0
R/W Register Name
Description
R
W
RDR
TDR
ENR
EIR
Receive data register
Transmit data register
Interrupt enable register
0h
1h
2h
3h
4h
5h
6h
R/W
R
Interrupt event and status indication register
Status register
R
LSR
ICR1
ICR2
MSR
R/W
R/W
R/W
Transmit-receive control register
BOF count setting register
Register for setting a transfer mode and a data rate and selecting a
crystal to be used
7h
8h
9h
Ah
9h
Ah
Bh
0h
Bh
Ch
Fh
R/W
R/W
R/W
R/W
R
DSR
DMA mode setting register
FCR
FIFO threshold setting register
TFL (L)
TFL (H)
TCC (L)
TCC (H)
MDS (L)
MDS (H)
RST (L)
RST (H)
TEST
*1 Transmit frame-length setting register (low-order byte)
Transmit frame-length setting register (high-order byte)
*1 Transmitter current-count register (low-order byte)
Transmitter current-count register (high-order byte)
*2 Maximum data size setting register (low-order byte)
Maximum data size setting register (high-order byte)
*2 Receiver frame length stack register (low-order byte)
*1
*1
*2
*2
R
R/W
R/W
R
Receiver frame length stack register (high-order byte)
Used for test.
R
R/W
*1 Whether TFL or TCC is read depends on the setting of the CTEST bit in the MSR
register.
*2 Whether MDS or RST is read depends on the setting of the CTEST bit in the MSR
register.
14/30
¡ Semiconductor
MSM9405
Register Table
Register
Function of each bit
Add
Mode R/W
name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
TDR1
Bit0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR0
0
TDR/RDR
all
R/W
/RDR7 /RDR6 /RDR5 /RDR4 /RDR3 /RDR2 /RDR1 /RDR0
SIR
Ex-SIR
MIR
FIR
*
*
FE_IE
RXH/T
_IE
1
2
3
4
5
ENR
EIR
R/W TXE_IE TXL_IE
MLE_IE
MLE_EV
FLV1
OE_IE
EOF_IE
*
CE_IE
*
AS_IE
ECE_IE
SIR
FE_EV
Ex-SIR
MIR
FIR
RXH/T
_EV
R
R
TXE_EV TXL_EV
OE_EV
EOF_EV
CE_EV
AS_EV
ECE_EV
SIR
Ex-SIR
MIR
FIR
LSR
ICR1
ICR2
FLV5
FLV4
FLV3
*
FLV2
FCLR
FLV0 IR_DET TOUT
SIR
*
*
Ex-SIR
MIR
FIR
R/W MS_EN TCC_EN CRC_
INV
RX_EN TX_EN
S_EOT
IR_PLS
SIR
*
SBF3
MBF3
*
*
SBF2
MBF2
*
*
*
Ex-SIR
MIR
FIR
IRIN
R/W CTEST SD_INV
_SL
SBF1
MBF1
*
SBF0
MBF0
*
RXINV
6
7
8
9
MSR
DSR
all
R/W
R/W
DRS2
*
DRS1
*
DRS0 XT_SL
*
*
IRSL1 IRSL0
DMA_ DMA_ DMA_
SL1 SL0 EN
all
*
*
*
FCR
all
all
all
all
all
all
all
all
all
all
R/W RXTH3 RXTH2 RXTH1 RXTH0 TXTH3 TXTH2 TXTH1 TXTH0
TFL (L)
TCC (L)
TFL (H)
TCC (H)
MDS (L)
RST (L)
MDS (H)
RST (H)
TEST
R/W
R
TFL7
TCC7
*
TFL6
TCC6
*
TFL5
TCC5
*
TFL4
TCC4
*
TFL3
TCC3
TFL11
TFL2
TCC2
TFL10
TFL1
TCC1
TFL9
TCC9
TFL0
TCC0
TFL8
TCC8
R/W
R
A
B
*
*
*
*
TCC11 TCC10
R/W MDS7 MDS6 MDS5 MDS4 MDS3 MDS2 MDS1 MDS0
R
R/W
R
RST7
RST6
RST5
RST4
RST3
MDS11 MDS10 MDS9 MDS8
RST11 RST10 RST9 RST8
RST2
RST1
RST0
*
*
*
*
*
*
*
*
C
F
R/W TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0
15/30
¡ Semiconductor
MSM9405
Registers
• TDR: Transmit Data Register (Write Only)
RDR: Receive Data Register (Read Only) (Address = 0h)
The TDR (Transmit Data Register) and RDR (Receive Data Register) are used to read/write data
directly upon receiving/sending the data. The TDR and RDR share the same address. When
data is written in the sending mode or during the idle state, the TDR works as the top of the FIFO
and 1-byte data can be written to the FIFO. When data is read in the receiving mode, the RDR
works as the bottom of the FIFO and 1-byte data in the FIFO can be read. Serial-to-parallel
conversion is performed by the RSR. Parallel-to-serial conversion is performed by the TSR.
Reading from the TDR or writing to the RDR is invalid. The contents of the FIFO and TDR/RDR
are cleard by writing "1" to FCLR in the ICR1 register. The TSR and RSR cannot be cleared.
• ENR: Enable Register (Address = 1h)
The ENR (Enable Register) is used to control enabling/disabling various interrupts on the
MSM9405. Each of eight bits corresponds to each of eight interrupts provided on the MSM9405.
Each of eight interrupts can be independently controlled by each bit. When the system is reset,
all bits are reset to "0". By writing "1" to the bit corresponding to the desired interrupt, the
specified interrupt is enabled.
ENR ENR ENR ENR ENR ENR ENR ENR
7
6
5
4
3
2
1
0
FE_IE (Enable = "1")
AS_IE (Enable = "1")
ECE_IE (Enable = "1")
OE_IE (Enable = "1")
CE_IE (Enable = "1")
MLE_IE (Enable = "1")
EOF_IE (Enable = "1")
RXH/T_IE (Enable = "1")
TXL_IE (Enable = "1")
TXE_IE (Enable = "1")
16/30
¡ Semiconductor
MSM9405
ENR bit
Table bit
This bit works as FE_IE in SIR or Extended-SIR mode, as AS_IE in MIR mode, and as ECE_IE in FIR
mode.
- FE_IE (Framing Error Interrupt Enable) (SIR mode/Extended-SIR mode): This bit enables/disables
interrupt when an FE (Framing Error : Stop bit not detected) has occurred.
- AS_IE (Abort Sequence Interrupt Enable) (MIR mode): This bit enables/disables interrupt when
an abort sequence has been received.
ENR[0]
- ECE_IE (Encode Error Interrupt Enable) (FIR mode): This bit enables/disables interrupt when an
encode error has occurred.
OE_IE (Overrun Error Interrupt Enable) : This bit enables/disables interrupt when an OE (Overrun
error : Error that occurs when the FIFO is full upon receiving and the next character is completely
received by the RSR) has occurred.
ENR[1]
ENR[2]
ENR[3]
ENR[4]
CE_IE (CRC Error Interrupt Enable) : This bit enables/disables interrupt when a CE (CRC Error) has
occurred. This bit is valid in either Extended-SIR, MIR, or FIR mode. In SIR mode, this bit must
be set to "0" (disable).
MLE_IE (Maximum Length Error Interrupt Enable) : This bit enables/disables interrupt when an MLE
(Maximum Length Error: Error that occurs when a frame exceeding the maximum data size set by
the MDS is received) has occurred.
EOF_IE (End Of Frame Interrupt Enable) : This bit enables/disables interrupt when the last byte in
the frame's data field has been detected in either Extended-SIR, MIR, or FIR mode. In SIR mode,
this bit must be set to "0" (disable).
RXH/T_IE (Receiver High-Data-Level/Timeout Interrupt Enable) : This bit enables/disables interrupt
when the received data is at or above the receiving threshold level or time-out has occurred.
TXL_IE (Transmitter Low-Data-Level Interrupt Enable) : This bit enables/disables interrupt when the
sent data is below the sending threshold level.
ENR[5]
ENR[6]
ENR[7]
TXE_IE (Transmitter Empty Interrupt Enable) : This bit enables/disables interrupt when both the
FIFO and the TSR have become empty upon sending.
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¡ Semiconductor
MSM9405
• EIR: Event Identification Register (Read Only) (Address = 2h)
The EIR (Event Identification Register) indicates factors of various interrupts on the MSM9405.
Each of eight bits corresponds to each interrupt bit assignment set on the ENR. The EIR works
asthestatusregistereveniftheinterruptisdisabled. Whenaneventoccurs, eachcorresponding
bit is set to "1". When the system is reset, all bits are reset to "0".
EIR
7
EIR
6
EIR
5
EIR
4
EIR
3
EIR
2
EIR
1
EIR
0
FE_EV (Framing Error = "1")
AS_EV (Abort Sequence = "1")
ECE_EV (Encode Error = "1")
OE_EV (Overrun Error = "1")
CE_EV (CRC Error = "1")
MLE_EV (Maximum Length = "1")
EOF_EV (EOF = "1")
RXH/T_EV (RX High-Data-Level/Timeout = "1")
TXL_EV (TX Low-Data-Level = "1")
TXE_EV (TX Empty = "1")
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¡ Semiconductor
MSM9405
EIR bit
Description
This bit works as FE_EV in SIR or Extended-SIR mode, as AS_EV in MIR mode, and as ECE_EV in
FIR mode. When the CPU reads the EIR contents, this bit is set to "0".
- FE_EV (Framing Error Event) (SIR mode/Extended-SIR mode): The bit is set to "1" when FE occurs.
- AS_EV (Abort Sequence Event) (MIR mode): The bit is set to "1" when an abort sequence is received.
- ECE_EV (Encode Error Event) (FIR mode): The bit is set to "1" when ECE occurs.
OE_EV (Overrun Error Event): When OE occurs, this bit is set to "1". When the CPU reads the EIR
contents, OE_EV is set to "0". The RSR characters are not transferred to the FIFO but overwritten.
CE_EV (CRC Error Event): When a CRC error occurs, this bit is set to "1". When the CPU reads the
EIR, this bit is set to "0". This bit is valid in either Extended-SIR, MIR, or FIR mode.
This bit is not used in SIR mode.
EIR[0]
EIR[1]
EIR[2]
EIR[3]
EIR[4]
MLE_EV (Maximum Length Error Event): When MLE occurs, this bit is set to "1". When the CPU
reads the EIR, this bit is set to "0".
EOF_EV (End Of Frame Event): This bit is valid in either Extended-SIR, MIR, or FIR mode. When the
last byte in the frame's data field reaches the bottom of the FIFO in receiving mode, EOF_EV
is set to "1". When the CPU reads the EIR, this bit is set to "0". In SIR mode, this bit is not used.
RXH/T_EV (Receiver High-Data-Level/Timeout Event): When received data in the FIFO is at or above
the receiving threshold level or time-out occurs, RXH/T_EV is set to "1".
The condition for setting RXH/T_EV to "0" depends on the following two cases :
If received data in the FIFO is at or above the receiving threshold level : Received data is read.
When received data in the FIFO is below the threshold level, this bit is set to "0".
If time-out occurs :
EIR[5]
After received data in the FIFO is read, this bit is set to "0".
TXL_EV (Transmitter Low-Data-Level Event): When sent data in the FIFO is below the sending
threshold level, this bit is set to "1". When sent data is written and sent data in the FIFO is at or
above the threshold level, this bit is set to "0".
EIR[6]
EIR[7]
TXE_EV (Transmitter Empty Event): When both FIFO and TSR are empty in sending mode, this bit
is set to "1". When the CPU reads the EIR, this bit is set to "0".
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¡ Semiconductor
MSM9405
• LSR: Line Status Register (Read Only) (Address = 3h)
TheLSR(LineStatusRegister)indicatesvariousstatusesoftheMSM9405thatisrunning. When
the system is reset, all bits of the LSR are set to "0". This register is for read only and cannot be
written.
LSR LSR LSR LSR LSR LSR LSR LSR
7
6
5
4
3
2
1
0
TOUT (Timeout = "1")
IR_DET (SIR Pulse detect = "1")
FLV (Byte number in FIFO)
LSR bit
Description
TOUT (FIFO Timeout): When time-out occurs in the FIFO during receiving, this bit is set to "1".
When received data is read from the FIFO, TOUT is set to "0".
LSR[0]
IR_DET (SIR Pulse detect) : This bit is set to "1" when a pulse having a width of tspw (SIR pulse width
upon receiving). It is set to "0" when the CPU reads the LSR.
LSR[1]
LSR[2-7]
FLV (FIFO Level): These bits indicate the number of data items in the FIFO with a value of 0 to 32.
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¡ Semiconductor
MSM9405
• ICR1: Infrared Control Register 1 (Address = 4h)
The ICR1 (Infrared Control Register 1) is used to set various environment so that the MSM9405
can perform IrDA communication under proper conditions. When the system is reset, all bits
of ICR1 are set to "0".
ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1
7
6
5
4
3
2
1
0
TX_EN ("1": Transmit Enable)
RX_EN ("1": Receive Enable)
S_EOT ("1": Set End Of Transmission)
IR_PLS ("1": Send Interaction Pulse)
FCLR ("1": FIFO Clear)
CRC_INV ("1": Send Inverted CRC Enable)
TCC_EN ("0": TCC off, "1": TCC on)
MS_EN ("1": Automatic mode Select)
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¡ Semiconductor
MSM9405
ICR1 bit
Description
TX_EN (Transmit Enable): When "1" is written to this bit, the sending mode is selected. When "0" is
written to this bit, sending terminates when data remaining in the FIFO has all been sent. In this
case, the TXE interrupt does not occur.
ICR1[0]
ICR1[1]
RX_EN (Receive Enable): When "1" is written to this bit, the receiving mode is selected. When "0" is
written to this bit, the device enters receive end mode.
S_EOT (Set End Of Transmission): This bit is valid in Extended-SIR, MIR, or FIR mode. When "1" is
written to this bit, the data written to the FIFO next time is recognized as the end of frame, and
immediately after it, the data added with CRC and EOF is sent as a frame. After a frame is sent,
this bit is automatically set to "0". To use S_EOT, TFL must be set to the maximum value or TCC
must be unused with TCC_EN = "0". This bit is not used in SIR mode.
IR_PLS (Send Interaction Pulse): This bit is valid in MIR or FIR mode. When "1" is written to
this bit, an approximately 2-ms serial infrared interaction pulse is sent immediately after the frame
being sent. After a frame is sent, this bit is automatically set to "0". This bit is not used in SIR
mode and Extended-SIR mode.
ICR1[2]
ICR1[3]
ICR1[4]
ICR1[5]
ICR1[6]
FCLR (FIFO Clear): When "1" is written to this bit, the FIFO (including the TDR and RDR) is made
empty. The FIFO threshold level does not change. The TSR and RSR are not cleared. When the
FIFO is made empty, this bit is automatically set to "0".
CRC_INV (Invert Transmitter CRC): This bit is valid in Extended-SIR, MIR, or FIR mode and is not
used in SIR mode. When "1" is written to this bit, transmission is interrupted if TXE (Transmitter
Empty) occurs. The inverted CRC and EOF are automatically added to the frame that caused TXE,
then the frame is sent. Writing "0" to this bit disables this function.
TCC_EN (TCC Enable): This bit is valid in Extended-SIR, MIR, or FIR mode. When this bit is set to
"1", the TCC is enabled. When TCC_EN is set to "0", the TCC is disabled. To use S_EOT, the TFL
must be set to the maximum value or the TCC must be disabled with TCC_EN = "0".
MS_EN (Mode Select Enable): When "1" is written to this bit, the MSM9405 performs the following
operation depending on the mode. After the operation is completed, this bit is automatically set to
"0".
If the MSM9405 is in FIR mode:
1. The SD pin is set to "H", and the Tx pin to "H".
2. Approximately 300 ns later, the SD pin is set to "L".
ICR1[7]
3. Approximately 300 ns later, the Tx pin is set to "L".
If the MSM9405 is in SIR, Extended-SIR, or MIR mode:
1. The SD pin is set to "H", and the Tx pin to "L".
2. Approximately 300 ns later, the SD pin is set to "L".
3. The Tx pin is held in the "L" level for approximately 300 ns.
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¡ Semiconductor
MSM9405
• ICR2: Infrared Control Register 2 (Address = 5h)
The ICR2 (Infrared Control Register 2) is used to set various environment so that the MSM9405
can perform IrDA communication under proper conditions. When the system is reset, all bits
of ICR2 are set to "0".
ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2
7
6
5
4
3
2
1
0
SBF (SIR Beginning Flags)
MBF (MIR Beginning Flags)
RXINV ("1": Signal Invert)
IRIN_SL ("0": Single Input "1": Double Input)
SD_INV ("0": SD Active High "1": SD Active Low)
CTEST ("0": TCC/RST "1": TFL/MDS)
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¡ Semiconductor
MSM9405
IRC2 bit
Description
These bits work as the SBF when Extended-SIR mode is selected, and as the MBF when the MIR
mode is selected. This function is disabled in SIR mode and FIR mode.
SBF (SIR beginning Flags): These bits determine the number of BOFs to be added during
sending in Extended-SIR mode as shown below.
MBF (MIR Beginning Flags): These bits determine the number of BOFs to be added during
sending in MIR mode as shown below.
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SIR BOFs
MIR BOFs
1
2
2
3
3
4
4
5
5
8
ICR2[0-3]
7
12
16
24
24
24
24
24
24
24
24
24
9
13
17
25
49
49
49
49
49
49
RXINV (IRIN Signal Invert): This bit is used to select active low or active high of the receive signal.
RXINV = "0": Active low
ICR2[4]
ICR2[5]
RXINV = "1": Active high
IRIN_SL (IRIN Select): This bit determines how the receive signal input pin is used.
IRIN_SL = "0": Only the input from the IRIN-A pin (2.4 kbps to 4 Mbps) is accepted.
IRIN_SL = "1": An input from IRIN-A or IRIN-B is automatically selected depending on the transfer
rate. (A: 2.4 to 115.2 kbps, B: 0.576 to 4 Mbps)
SD_INV (SD Signal Invert): This bit changes the polarity (active high/low) of the SD pin output on
the MSM9405.
ICR2[6]
ICR2[7]
SD_INV = "0": Active high ("H" output during shutdown)
SD_INV = "1": Active low ("L" output during shutdown)
CTEST (Counter Test): Normally this bit is set to "0". When TFL/TCC and MDS/RCC are read after
"1" is written to this bit, the TFL and MDS values can be obtained.
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¡ Semiconductor
MSM9405
• MSR: Mode Select Register (Address = 6h)
The MSR is used to select various modes of the MSM9405. When the system is reset, each bit
is set to the initial value.
MSR MSR MSR MSR MSR MSR MSR MSR
7
6
5
4
3
2
1
0
IRSL0 (IrDA mode Select 0)
IRSL1 (IrDA mode Select 1)
Not Used
XT_SL ("0": 48 MHz "1": 18.432 MHz)
DRS (Data Rate Select)
MSR Bit
Description
IRSL (Infrared Mode Select): These bits are used to select the transfer mode as shown below.
The initial value is set to "00".
IRSL1
IRSL0
mode
SIR
0
0
1
1
0
1
0
1
MSR[0-1]
Extended-SIR
MIR
FIR
MSR[2-3]
MSR[4]
These bits are not used.
XT_SL (Crystal Select): This bit determines the crystal to be used.
The initial value is set to "0".
XT_SL = "0": 48 MHz crystal is used
XT_SL = "1": 18.432 MHz crystal is used
DRS (Data Rate Select): These bits determine the transfer rate as shown below. The initial value
is set to "001".
Encoding
000
SIR Data Rate
2400 bps
9600 bps
19.2 kbps
38.4 kbps
57.6 kbps
115.2 kbps
reserved
MIR Data Rate
0.576 Mbps
1.152 Mbps
reserved
FIR Data Rate
reserved
4 Mbps
001
MSR[5-7]
010
reserved
reserved
reserved
reserved
reserved
reserved
011
reserved
100
reserved
101
reserved
110
reserved
111
reserved
reserved
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¡ Semiconductor
MSM9405
• DSR: DMA Mode Select Register (Address = 7h)
The DSR (DMA Mode Select Register) is used to select the DMA mode for the MSM9405. When
the system is reset, all bits of DSR are set to "0".
DSR DSR DSR DSR DSR DSR DSR DSR
7
6
5
4
3
2
1
0
DMA_EN ("1": DMA mode)
DMA_SL0 (DMA Select 0)
DMA_SL1 (DMA Select 1)
Not Used
DSR Bit
Description
DMA_EN (DMA Mode Enable): This bit determines whether the DMA is to be used. The initial value
is set to "0".
When "1" is written to this bit, DSR[1-2] (DMA_SL0, DMA_SL1) setting is enabled and the
MSM9405 enters the DMA transfer standby mode. (DREQ is asserted when the DREQ assert
condition is met.)
DSR[0]
If DMA_EN = "0", DSR[1-2] (DMA_SL0, DMA_SL1) setting is disabled and DMA transfer is not
performed. (DREQ is not asserted even if the DREQ assert condition is met.)
DMA_SL (DMA Select): These bits are used to select the method of interfacing with DMAC.
DMA_SL1
0
DMA_SL0
0
Function
DREQ becomes active low and DACK becomes active high.
When the RD signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the WR signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A0 to A3.
DSR[1-2]
0
1
DREQ becomes active high and DACK becomes active low.
When the WR signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the RD signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A0 to A3.
1
1
0
1
DREQ becomes active low and DACK becomes active high.
DACK is disabled.
DREQ becomes active high and DACK becomes active low.
DACK is disabled.
DSR[3-7]
These bits are not used.
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¡ Semiconductor
MSM9405
FCR : FIFO Control Register (Address = 8h)
The FCR (FIFO Control Register) is used to set the threshold level of the FIFO to be used by the
MSM9405 upon sending/receiving. The FCR setting is applied to both interrupt and DMA.
When the system is reset, the FCR is set to the initial value.
FCR
7
FCR
6
FCR
5
FCR
4
FCR
3
FCR
2
FCR
1
FCR
0
TXTH (TX Threshold Select)
RXTH (RX Threshold Select)
FCR bit
Description
TXTH (Transmit Threshold Select): These four bits set the following 16 sending threshold levels.
The initial value is set to "0111".
FCR (0-3)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TX Threshold Level (Byte)
01
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
FCR[0-3]
RXTH (Receive Threshold Select): These four bits set the following 16 receiving threshold levels.
The relationship between the FCR (4-7) value and receiveing threshold level is the same as the
relationship between the FCR (0-3) and sending threshold level. The initial value is set to "0111".
FCR[4-7]
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¡ Semiconductor
MSM9405
TFL : (Transmitter Frame Length Register
TCC : Transmitter Current-Count Register (Address = 9, Ah)
The TFL (Transmitter Frame Length) and TCC (Transmitter Current-Count Register) are used
to specify the length of the frame to be transferred for sending. The TFL and TCC shares the
same address. Bits 0 to 7 of address 9h and bits 0 to 3 of address Ah (totally 12 bits) are used.
Bit 0 of address 9h is the LSB.
When the TFL/TCC value is read, the CTEST setting is reflected. If CTEST = "0", the TCC
contents can be read. If CTEST = "1", the TFL contents can be read. When the TFL/TCC is
written, the TFL value is rewritten. The TCC cannot be written.
TousetheTFL/TCC, write"1"toTCC_EN, andsettheframelengthintheTFL. Theframelength
to be set does not include the CE, FCS, BOF, and EOF. When "1" is written to TX_EN, the TFL
value that has been set as the frame length is loaded to the TCC. When sending is started, the
TCC value is decremented by 1 each time 1 byte is sent. When the TCC value becomes "0", the
end of frame is assumed and the frame is automatically added with the CRC and EOF and sent.
After one frame is sent, the TFL value is loaded again into the TCC when the BOF of the second
frame is sent.
The TFL/TCC initial value is set to 800h.
MDS : Maximum Data Size Register
RST : Receiver Frame Length Stack Register (Address = B, Ch)
The MDS (Maximum Data Size Register) is used to set the maximum data size. The RST
(ReceiverFrameLengthStackRegister)isusedtostackthereceivedframelength. TheMDSand
RST share the same address. Bits 0 to 7 of address Bh and bits 0 to 3 of address Ch (totally 12
bits) are used. Bit 0 of address Bh is the LSB.
When the MDS/RST value is read, the CTEST setting is reflected. If CTEST = "0", the RST
contents can be read. If CTEST = "1", the MDS contents can be read. When the MDS/RST is
written, the MDS value is rewritten. The RST cannot be written.
To use the MDS, set the maximum data size in the MDS in advance. The frame length to be set
does not include the CE, FCS, BOF, and EOF in the Extended-SIR, MIR, and FIR modes.
(However, itdoesincludethemintheSIRmode.) Whenreceivingisstarted, theinternalcounter
value is incremented by 1 each time one byte is received. If the internal counter value exceeds
the MDS value during receiving, MLE occurs. The MDS initial value is set to 800h.
When a frame is fully received and all the data in the received frame is taken out of the FIFO,
the received frame length counted by the internal counter is stacked in the RST. This value is
stored untill the next frame is fully received. The value stacked in the RST is maintained even
if MSM9405 sending/receiving is switched. The RST initial value is set to 0h.
TEST : Test Register (Address = Fh)
This register is used for testing.
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¡ Semiconductor
MSM9405
APPLICATION CIRCUIT
IRIN-A
IRIN-B
IROUT
RXD-A
(RXD-B)
TXD
D0-D7
A0-A3
Infrared
Transceiver
Module
CS
RD
SD
WR
MSM9405
TC
SD
INTR
DREQ
DACK
RESET
PWDN
XIN
XOUT
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¡ Semiconductor
MSM9405
PACKAGE OUTLINES AND DIMENSIONS
(Unit : mm)
Mirror finish
30-Pin Plastic SSOP
30/30
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