MSM9552 [OKI]
LSI for FM Multiplex Data Demodulation; LSI为FM多重数据解调
| 型号： | MSM9552 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | LSI for FM Multiplex Data Demodulation |
| 文件： | 总7页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
¡ Semiconductor
MSM9552/MSM9553
LSI for FM Multiplex Data Demodulation
GENERAL DESCRIPTION
The MSM9552 and MSM9553 are LSI devices which demodulate FM character multiplex signals in
the DARC (DAta Radio Channel)* format to acquire digital data. The MSM9552 and MSM9553
operate on 5V and 3V, respectively. In the DARC format, baseband signals at ordinary FM
broadcasting frequencies are multiplexed with 16k-bps digital data which are L-MSK-modulated at
76kHz.
Each of the MSM9552 and MSM9553 has a bandpass filter consisting of SCF, frame synchroniza-
tion circuit, error correction circuit, etc. on a single chip.
So, a system for acquisition of digital data can be easily constructed by externally mounting an FM
receiver tuner, microcontroller for control, and memory for temporary storage of data.
The MSM9552 and MSM9553 have a simple configuration, and are equipped with only necessary
functions. By making changes to software for the external microcontroller, the MSM9552 and
MSM9553 can meet the various requirements of FM multiplex broadcasting services which will be
offered in future.
TheseLSIdevicesarebestsuitedtotheradiosetsandinformationdevicesforFMcharactermultiplex
broadcasting, which started in Japan in October 1994. Especially, the MSM9553 is suitable for
portable units.
* DARC is a registered trademark of NHK ENGINEERING SERVICES, INC.
Note that a contract needs to be made with NHK Engineering Service if a manufacturer produces/
sells electronic equipment utilizing the DARC technology.
FEATURES
• Built-in bandpass filter (SCF)
• Built-in block synchronization circuit and frame synchronization circuit
• Setting of the number of synchronization protecting stages
• Regeneration of data clocks by digital PLL
• 1T delay detection
• Built-in error correction circuit
• Built-in layer 4 and layer 2 CRC check circuit
• Microcontroller parallel interface
• Clock output for external devices (64kHz to 8.192MHz selectable)
• International standard frame format
• Power source:
• Package
5V (MSM9552), 3V (MSM9553)
44-pin plastic QFP (QFP44-P-910-0.80-2K)
1
Limitter
Variable
gain
AMP
BPF
(SCF)
+
–
AIN
Clock
regeneration
Block
synchronization
Frame
synchronization
Timing
control
LPF
Vref
SG
Filter
PN
34Byte RAM
Read
Error
correction,
Lay 2 CRC
descrambler
¥
write
Layer 4 CRC
2
register
LSI internal
clock
D
DB2
Q
CK
WR31
Data bus
1T delay
circuit
CLR
DVDD
Addressbus
Limitter
Digital Signal
Processor
CPU interface
LPF
+
Frequency
divider
–
Delay Detection
Data bus
DB0-DB7
Address
AD0-AD5
RD WR CS CLR INT
XOUTC
XOUT
XTAL2
XTAL1
¡ Semiconductor
MSM9552/MSM9553
PIN CONFIGURATION (TOP VIEW)
44
34
MON
ADETIN
AVDD
A0
1
33
XOUT
CS
AGND
SG
XTAL2
XTAL1
DVDD
DGND
DB7
AIN
XOUTC
MOUT0
MOUT1
MOUT2
MOUT3
DB6
DB5
DB4
11
23
12
22
44-Pin Plastic QFP
Note: Leave the NC pins open.
3
MSM9552/MSM9553
PIN DESCRIPTION
¡ Semiconductor
Function
Symbol
WR
Pin
16
Type
Description
Write signal to internal register
Read signal to internal register
Micro-
controller
interface
I
I
RD
18
INT
15
O
Interrupt signal to microcontroller. "L": Occurrence of an
interrupt
CS
CLR
31
40
I
I
Chip select signal.
"L": Read, write, and data bus signals valid
"L" initializes internal registers, and the device enters
power down mode
A0 to A5
33 to 38
I
I/O
I
Address signal to internal register
Data bus signal to internal register
FM multiplex signal input
DB0 to DB7 19 to 26
AIN
SG
6
5
Tuner
interface
O
Analog reference voltage output pin. To prevent noise,
connect a capacitor between this pin and analog ground.
MON
1
2
O
Analog section waveform monitor pin. The analog block is
specified by the analog control register.
Analog
section test
ADETIN
I
I
Analog signal input pin for testing
Digital
section test
IORD
IOWR
41
42
Digital section test signal input pins. Internally pulled up.
MOUT0 to
MOUT6
8 to 14
O
Digital section test signal output and monitor output pins
XTAL1
XTAL2
XOUT
29
30
32
7
I
O
O
I
8.192MHz crystal oscillator connection pin
Clock
8.192MHz crystal oscillator connection pin
Pin for supply of 64kHz to 8.192MHz clock to the outside
XOUTC
XOUT output control pin.
"L"=Clock output, "H"=Output disabled. Pulled up internally.
Power
supply
AVDD
AGND
DVDD
DGND
3
4
—
—
—
—
Analog section power supply pin
Analog ground pin
28
27
Digital section power supply pin
Digital ground pin
4
¡ Semiconductor
MSM9552/MSM9553
ABSOLUTE MAXIMUM RATINGS (MSM9552)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
AVDD
DVDD
–0.3 to +7.0
AVDD=DVDD
Ta=25°C
V
Input voltage
Output voltage
VI
VO
–0.3 to AVDD+0.3
–0.3 to DVDD+0.3
Maximum power dissipation
PD
Ta=25°C per package
Ta=25°C per output
—
400
50
mW
°C
Storage temperature
TSTG
–55 to +150
RECOMMENDED OPERATING CONDITIONS (MSM9552)
Parameter
Symbol
Condition
Range
Unit Applied Pin
Power supply voltage
AVDD
DVDD
AVDD=DVDD
4.5 to 5.5
V
AVDD
DVDD
Crystal frequency
fXTAL
VAIN
TOP
—
8.192MHz 100ppm
0.5 to 2
—
XTAL1
XTAL2
Composite signals,
including multiplex
signals
FM multiplex signal input
voltage
VP-P
°C
AIN
Operating temperature
—
–40 to +85
—
ELECTRICAL CHARACTERISTICS (MSM9552)
Parameter
Symbol
Condition
Min. Typ. Max. Unit Applied Pin
—
16
32 mA
AVDD
DVDD
Current consumption
IDD
During operation, No load
f=8.192MHz
—
—
—
—
20 mA
During power down, No load
3.0 dB
MON
MON
MON
BPF pass band attenuation
BPF reject band attenuation
BPF reject band attenuation
GAIN1
GAIN2
GAIN3
72 - 80kHz
Variable gain amplifier
gain: 0dB
50
50
—
—
—
—
dB
dB
0 - 53kHz
Variable gain amplifier
gain: 0dB
100 - 500kHz
Variable gain amplifier
gain: 0dB
5
MSM9552/MSM9553
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS (MSM9553)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
AVDD
DVDD
–0.3 to +7.0
AVDD=DVDD
Ta=25°C
V
Input voltage
Output voltage
VI
VO
–0.3 to AVDD+0.3
–0.3 to DVDD+0.3
Maximum power dissipation
PD
Ta=25°C per package
Ta=25°C per output
—
400
50
mW
°C
Storage temperature
TSTG
–55 to +150
RECOMMENDED OPERATING CONDITIONS (MSM9553)
Parameter
Symbol
Condition
Range
Unit Applied Pin
Power supply voltage
AVDD
DVDD
AVDD=DVDD
2.7 to 3.3
V
AVDD
DVDD
Crystal frequency
fXTAL
VAIN
TOP
—
8.192MHz 100ppm
0.2 to 0.9
—
XTAL1
XTAL2
Composite signals,
including multiplex
signals
FM multiplex signal input
voltage
VP-P
°C
AIN
Operating temperature
—
–20 to +75
—
ELECTRICAL CHARACTERISTICS (MSM9553)
Parameter
Symbol
Condition
MIN TYP MAX Unit Applied Pin
—
13
22 mA
AVDD
DVDD
Current consumption
IDD
During operation, No load
f=8.192MHz
—
—
—
—
10 mA
During power down, No load
3.0 dB
MON
MON
MON
BPF pass band attenuation
GAIN1
GAIN2
GAIN3
72 - 80kHz
Variable gain amplifier
gain: 0dB
50
50
—
—
—
—
dB
dB
BPF reject band attenuation
(1)
0 - 53kHz
Variable gain amplifier
gain: 0dB
BPF reject band attenuation
(2)
100 - 500kHz
Variable gain amplifier
gain: 0dB
6
MSM9552
8 bits
FM multiplex
data demodulation
LSI
FM
tuner
MSM6794 x 2
LCD control
MCU
CPU
driver
Buffer
RAM
Font
ROM
16 Chinese
characters
x 2 lines
ROM
LCD display
MSM6794: LCD driver with built-in 128-channel
RAM for liquid crystal dot matrix
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